design of 200w llc resonant hb - e2echina.ti.com · cr lr lm n:1:1 vin vo rl q1 q2 d1 d2 * * * t0...
TRANSCRIPT
Cr Lr
Lm
n:1:1
Vin
Vo
RL
Q1
Q2
D1
D2
**
*
t0 t1 t2 t3
Vg_Q1Vg_Q2
Vp
ir
im
is
When switching frequency is below resonant frequency, magnetizing inductor begins to participate in resonant and increase voltage gain
Secondary diode becomes discontinuous
Operation Principles (fsw<fr)
When switching frequency is above resonant frequency, circuit behaves as SRC
Secondary current becomes CCM, reverse recovery loss increases
Operation Principles (fsw>fr)
FHA of LLC Resonant HB
)//(/1//4
4
2
||1
1
RacsLpsLrsCrRacsLp
VV
V
Vn
n
VinnVoG
S
P
S
P
++=
=== π
π
12
21 VsVinVinVs ππ
=⇒=
poorp Vn
VVnnVV4
41
ππ
=⇒==
2222
22
2
22
2
22
)1()]11(11[
1
1]1)[(1)(
)(
)1(]1)([
)1(
)()(1
)()(
//)(1//)(
4
4
2
),,(
nn
nn
rrr
r
nn
ffQ
fL
RacCrLr
LrLmj
LrLrLm
LrLm
LrCrLmjRacCrLrLmLmCrRac
LmRacjCrjLrCrRacLmLr
CrLm
LmRacj
RacLmjRacLmjLrj
Crj
RacLmjRacLmj
RacLmjLrjCrj
RacLmj
VV
V
Vn
n
VinnVoQLfM
F
d
F
Ro
F
d
F
Ro
−⋅+−⋅+=
⋅⋅⋅−⋅+−+
⋅
⋅=
−⋅⋅+−+=
+−
+−=
+++
+=
++=
===
ωω
ωω
ωω
ωω
ωωωω
ωωωω
ω
ωωω
ω
ωω
ωωω
ω
π
π
LrLmLn =
r
swn f
ff =
RacCrLrQ 1
⋅=
out
out
IVnRac ⋅= 2
28π
LrCrfr
π21
=
CrLrLmfp
)(21+
=π
Voltage Gain Equation
1=nL 5=nL
10=nL 15=nL
Voltage Gain of Different Ln
Ln ↑ → Traditional SRC → Enter into ZCS @ fsw<fr → lost gain monotony and MOSFET ZVS operation→ much wider fsw range, not good hold-up time performance
Ln ↓ → if low inductance → Im ↑ → conducted and switched-off losses ↑→ if high inductance, fixed resonant frequency → Cr ↓ → Vcr ↑
“A Novel Precise Design Method for LLC Series Resonant Converter”, Teng liu, etc., INTELEC ‘06
Larger Q value gives smaller start up current with less frequency range
Start Up Current Consideration
Advantages of LLC Resonant HB
Primary ZVS can be achieved with wide load rangeSecondary ZCS can be achieved when fs<frSmaller switch-off loss due to small turn off currentCapacitor filter w/o output inductorLess voltage stress on rectifiers>1 voltage gain during hold-up time
Minimize RMS current under normal operation conditionEnsure ZVS operationEnsure desired input voltage operation range
Design Targets
fsw=fr @ normal operation)sin(2)( _ Φ+= tIti oPRMSLr ω
⎪⎪⎩
⎪⎪⎨
⎧
>−−=
<+−=
2),
2()(
2,)(
_
_
TstTstLmnViti
TsttLmnViti
omLmLm
omLmLm
4Ts
LmnVi o
Lm ⋅=
2
]4
)sin(2[
2
)]()([ 20 _2
0
Ts
dttLmnVTs
LmnVtI
Tsdttiti
nRV
Tsoo
oPRMS
Ts
LmLr
L
o∫∫ −⋅+Φ+
=−
=ω
22
224
_ 424
1 π+=m
SL
L
oPRMS L
TRnnRVI
2
)]()([20
2
_ Tsdttintin
I
Ts
LmLrSRMS
∫ ⋅−⋅=
42
2242
_ 12)485(24
3 ππ
π+
−=
m
SL
L
oSRMS L
TRnRVI
4)sin(2)0( _
TsLmnVIti o
PRMSLr ⋅−=Φ=
Nominal Vin 440VMinimum Vin 360V
Maximum Vin 54VOutput Power 200WResonant Frequency 100kHz
Electrical Parameters
2. Magnetizing Inductance
42
2242
_ 12)485(24
3 ππ
π+
−=
m
SL
L
oSRMS L
TRnRVI
22
224
_ 424
1 π+=m
SL
L
oPRMS L
TRnnRVI
The magnetizing inductance impacts conducted and switched losses,So
On the other hand,the maximum magnetizing current also impacts ZVS operation.
j
oPFC
oLmp
jPFCLmp
CtdTsLm
nVV
TsLmnVI
tdCV
I
162
4
2
⋅<⇒
⎪⎪⎪
⎩
⎪⎪⎪
⎨
⎧
=
=
>
jswj Cftd
CtdTsLm
1616=
⋅=
td=175ns
Cj=195pF, SPP20N60C3
Lm=530
4. Decision Ln and Q
L
mon
n
RnLfQL
LrLmL
RacCrLr
Q
⋅=⇒
⎪⎪
⎩
⎪⎪
⎨
⎧
=
=
2
282
π
π
1 3 5 7 9 11 13 15 17 19 200.05
0.15
0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.951
Ln
Q
1.3
1.3
1.3
1.3
1.6
1.61.6
1.61.6
2
22
22
2.52.5
2.52.5
33
33
Constant Lm
IntersectionFrom the intersection of curves of LnQ and required maximum peak gain to get the appropriate Ln and Q.
Ln=6
Q=0.3
5. Calculation of Lr and Cr
nLLmLr =
LrfCr
o2)2(
1π
=
Lr=68uH, additional 20uH leakage inductor in main transformer
Cr=15nF*2,two capacitor structure to reduce input ripple current
Converter Specification
Primary switching Device
O
in
VVn2
=
Magnetizing inductor
j
deadm C
tTL16⋅
=
1 3 5 7 9 11 13 15 17 19 200.05
0.15
0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.951
Ln
Q
1.3
1.3
1.3
1.3
1.6
1.6
1.6
1.61.6
2
2
2
22
2.52.5
2.5
2.5
33
3
3
Constant Lm
Lm decreases
1 3 5 7 9 11 13 15 17 19 200.05
0.15
0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.951
Ln
Q
1.3
1.3
1.3
1.3
1.6
1.6
1.6
1.61.6
2
2
2
22
2.52.5
2.5
2.5
33
3
3
Constant LmConstant Lm
Lm decreasesLm decreases
Peak gain enough? Yes
Choose cross section of required gain and
constant Lm
No
Reduce Lm
Resonant inductor
n
mr L
LL =
Resonant capacitor
rrCLf
π21
0 =
L
mn
RnLf
QL
2
20
82
π
π=
Flow Chart of Optimal Design
Check gain monotony,min and max fsw, Vcr etc.
Benefits:•Interleaved PFC with UCC28061•LLC Resonant HB with UCC25600•93% Efficiency w/o Secondary SR
time/礢ecs 200nSecs/div
23 23.2 23.4 23.6 23.8 24 24.2 24.4 24.6 24.8 25
A
-4
-2
0
2
4
6
8
time/礢ecs 200nSecs/div
19.6 19.8 20 20.2 20.4 20.6 20.8 21 21.2 21.4
A
-4
-2
0
2
4
6
8
time/礢ecs 200nSecs/div
20.2 20.4 20.6 20.8 21 21.2 21.4 21.6 21.8 22 22.2 22.4
A
-4
-2
0
2
4
48% and 52% 49% and 51%
50% and 50%
Asymmetrical duty cycle makes resonant tank current unbalanced
Load current will be concentrated in one diode and increase conduction loss and switching loss- Controller should provide well matched PWM signal- Different secondary leakage inductance
LLC Issue-Imbalance Current
LLC Issue-Over Current
Add Clamping Diode
Lr
Lm
Q1
Q2
Cr/2
VinRoCo
Cr/2
Lr
Lm
Q1
Q2
Cr/2
VinRoCo
Cr/2
Iin
IQ1
VCR
Iin
IQ1
VCR
ID1
Over Load Operation
Part of resonant tank energy could be feedback to source, which helps limit output current
LLC Issue-MOSFET Failure @ Light Load
To achieve ZVS operation, the body diode of primary MOSFETs conducts first, and then the channel circulates the current.At light load, the reverse voltage between body diode is much small once the channel circulates the small current, such that the reverse recovery time in body diode is much long, resulting in primary MOSFETs shoot-through.
• Bing Lu, “Investigation of High-density Integrated Solution for AC/DC Conversion of a Distributed Power System”, Ph. D. dissertation, Virginia Tech, 2006http://scholar.lib.vt.edu/theses/available/etd-06262006-111218/
• Bo Yang, “Topology investigation of front end DC/DC converter for distributed power system “ Ph. D. dissertation, Virginia Tech, 2003 http://scholar.lib.vt.edu/theses/available/etd-09152003-180228/
References
TI UCC25600 8 Pin Resonant Half Bridge Controller
1
2
3
4 5
6
7
8 GATE1
VCC
GND
GATE2
Td
RT
OC
SS
FeaturesAdjustable Soft start (1ms to 500ms)Adjustable dead timeAdjustable Fswmax & Fswmin (3% accuracy)
Io = +1A /-1.5AEnable (ON/OFF control)
Protection functionsTwo levels over current protection
auto recovery latch
Bias voltage UV and OV protectionOver temperature protectionSoft start after all fault conditions
SOT 8 pin package= Easy design and layout
Ready to Order
Application Circuit360~400V
DC_OUT
Vcc
11
11
11
11
Td
RT
OC
SS
Gate1
Gate2
Vcc
GND
Programmable dead timeFrequency control with minimum/maximum frequency limitingProgrammable soft start with on/off controlTwo level over current protection, auto-recovery and latch upMatching output with 50ns tolerance