Design of a CMOS Test Chip for Package Models and I/O CharacteristicsVerification

Chetan Despande and Tom Chen∗

1 Introduction

Reliable packages for modern chips are crucial for satisfac-tory system performance. In order to ascertain package’s per-formance, an equivalent electrical model is plugged into cir-cuit simulations and the package’s performance characteristicscan be analyzed. However, one implicit assumption design-ers make is that these equivalent electrical models are accu-rate for performance characterization of packages. For modernhigh-speed designs, verification of the accuracy of these mod-els is imperative and can only be carried out on real-silicon. Inaddition, signal integrity for inter-chip communication is cru-cial from a systems perspective. To study the signal integrityof data under different PVT (process variation, voltage, andtemperature) conditions, appropriate test structures are needed.Data can be subjected to controlled variations through thesestructures and its integrity can be studied. And finally, test-ing package reliability at high temperatures is important sinceon-chip temperatures are increasing dramatically as processescontinue to scale. The test chip presented in this design is in-tended to allow 1) circuit and package designers to evaluateand validate the accuracy of package models under a variety ofenvironment conditions; 2) system designers to evaluate pack-age/system level signal integrity issue before actual chips areavailable; and 3) system designers to evaluate on-chip temper-atures and to study thermal integrity of packages. The test chipincludes a variety of features to achieve these goals. The testchip is fabricated at TSMC in a 0.18µm CMOS process. Themeasurement results and the die microphotograph will be sentlater as soon as they are available. This paper presents the lay-out based simulation results.

2 Description of the Test Chip

The chip has six core blocks consisting of a 3to8 decoder. Eachoutput of the decoder drive a different set of ring-oscillators togenerate different current settings. Figure 1 shows the blockdiagram of the core. The decoder is controlled using three bits.Each of the decoder outputs drive 640 ring oscillators drawing

∗This work was partially supported by Hewlett Packard Co. ChetanDespande and Tom Chen are with the Department of Electrical and ComputerEngineering, Colorado State University, Fort Collins, Colorado, USA

Process TSMC0.18µm processPower Supply 1.8v (Core)/1.5v (I/O)

Die Size (9.8 x 13)mmFET Count 1.8 million

I/O pins 122VDD and GND pins 2950

Table 1:Features on the Test Chip

approximately0.54A of average current. By varying the con-trol signals, additional blocks can be turned on, drawing morestep currents. The layout of the core is shown in Figure 2. Fora given package design, the efficiency of the package responseto the current requirements on the chip for varying amounts ofon-chip bypass capacitance can be examined with the test chipusing controllable on-chip bypass capacitance. The chip con-sists of three output pad rings, each driving 16-bit data array.The data array is a 1024 bit shift register, which is loaded usinga single data pattern that is pre-determined. After every 64 reg-isters, the output is taken as input stream to the 16-bit bus in theoutput pad ring. The the slew rate of the output data can be con-trolled. The I/O cell incorporates selectable driver impedancesto drive the data off the chip. To counter power supply droopunder high frequency switching conditions, controllable by-pass capacitors have been incorporated in the I/O cell to studypower supply droop and its effect on data performance underdifferent bypass capacitor configurations. The layout of the I/Ocell is as shown in Figure 2. For thermal-mechanical integrityevaluations, daisy chains have been employed in this design.The test chip has blocks that draw currents to the order of tensof amperes at high operating frequencies. Some of these blockscan be made to switch, generating heat, while other parts of thechip can be controlled to be relatively cooler. Thus, a signifi-cant temperature gradient across the die can be generated andthermal expansion effects can be studied. Temperatures on thechip are collected by 10 temperature sensors placed at differ-ent regions on the die. Table 1 lists the features of the test chip.Figure 3 shows the top level layout with the six core blocks, theinput pad ring for the control signals and the three output padrings to drive data off the chip. At the center of the chip is thedata array that generates the sixteen bit data and the repeatersfor global routes.

1

bloc

k le

vel d

ecod

er

current generation using ring osc.('000')

current generation using ring osc.('001')

current generation using ring osc.('010')

current generation using ring osc.('011')

current generation using ring osc.('100')

current generation using ring osc.('101')

current generation using ring osc.('110')

current generation using ring osc.('111')

global enable

Vdd Vdd

Bypass capacitance within each block

block-levelcontrol

globalenable

Ring-oscillator schematic(Osc0,Osc1, Osc2)

Osc0

Osc1

Osc2

Figure 1:Block diagram of the core.

3212 um

3617

.7um

Figure 2:Layout of the core and I/O cell

3 Simulation Results

We just received the silicon die back from the manufacturerand have not performed measurements of the chip yet. There-fore, the simulation results is presented here. Figure 4 showsthe layout based simulation of the core drawing a step load.Figure 5 are the simulation showing the effect of controllablebypass capacitances to reduce power supply droop. This sim-ulation was done using a given package model to take packageresponse into account. It can be seen that as the amount of by-pass capacitance turned on increases, the quality of the signal atthe pad improves substantially. Figure 5 clearly shows the im-provement in the power supply droop with additional amountsof bypass capacitance.

4 Conclusions

A test chip design for package model verification has been pre-sented. Package models can be practically verified before ac-tual chips are available allowing concurrent engineering of chipdesign, package design, and system design. The programma-bility of the test chip allows it to be used for many differentproducts.

Figure 3:Microphotograph of the test chip

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Figure 5: Power supply droop and data at the pad showing thedroop reduction with increasing bypass cap.

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