design of arithmetic circuits using vhdl

Digital Kommunikationselektronik, TNE027 Lecture on VHDL

1

VHDL code for the full-adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY fulladd ISPORT ( Cin, x, y : IN STD_LOGIC ;

s, Cout : OUT STD_LOGIC ) ;END fulladd ;

ARCHITECTURE LogicFunc OF fulladd ISBEGIN

s <= x XOR y XOR Cin ;Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;

END LogicFunc ;

Design of Arithmetic Circuits using VHDL

Full-adder


2

std_logic_1164: a package containing the definition of STD_LOGIC

Data type: STD_LOGICSome of legal values of STD_LOGIC: 0, 1, Z, -Z: high-impedance state- : don’t care

LIBRARY ieee;USE ieee.std_logic_1164.all;


3

Entity

Entity Declaration

Architecture

Design Entity


4

ENTITY fulladd ISPORT ( Cin, x, y : IN STD_LOGIC ;

s, Cout : OUT STD_LOGIC ) ;END fulladd ;

ENTITY Declaration

ENTITY entity-name ISPORT ( [SIGNAL] signal_name{,signal_name}:[mode] type_name {; [SIGNAL] signal_name{,signal_name}:[mode] type_name} ) ;

END entity_name ;

Example


5

Modes of signals in entity portsMode Purpose

IN Input

OUT Output

The signal only appears on the left of <=.

INOUT Input and output

BUFFER Output

The signal can appear both on the left and right sides of <=.


6

ArchitectureARCHITECTURE architecture_name OF entity_name IS

[SIGNAL declarations]

[CONSTANT declarations]

[TYPE declarations]

[COMPONENT declarations]

[ATTRIBUTE specifications]

BEGIN

{COMPONENT instantiation statement ;}

{CONCURRENT ASSIGNMENT statement ;}

{PROCESS statement ;}

{GENERATE statement ;}

END [architecture_name];

Declaration region

Architecture body


7

VHDL code for a four-bit adder


ENTITY adder4 ISPORT ( Cin : IN STD_LOGIC ;

x3, x2, x1, x0 : IN STD_LOGIC ;y3, y2, y1, y0 : IN STD_LOGIC ;s3, s2, s1, s0 : OUT STD_LOGIC ;Cout : OUT STD_LOGIC ) ;

END adder4 ;

ARCHITECTURE Structure OF adder4 ISSIGNAL c1, c2, c3 : STD_LOGIC ;COMPONENT fulladd

PORT ( Cin, x, y : IN STD_LOGIC ;s, Cout : OUT STD_LOGIC ) ;

END COMPONENT ;BEGIN

stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;stage3: fulladd PORT MAP (

Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;END Structure ;

A four-bit adder usingfulladd as a component


8

Declaration of a package


PACKAGE fulladd_package ISCOMPONENT fulladd

PORT ( Cin, x, y : IN STD_LOGIC ;s, Cout : OUT STD_LOGIC ) ;

END COMPONENT ;END fulladd_package ;

Package Declaration

This code can be stored in a separate VHDL source code file, or it can be included in the same source code file for the fulladd entity.

A package often contains data type declarations and component declarations.


9Using a package for the four-bit adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.fulladd_package.all ;


x3, x2, x1, x0 : IN STD_LOGIC ;y3, y2, y1, y0 : IN STD_LOGIC ;s3, s2, s1, s0 : OUT STD_LOGIC ;Cout : OUT STD_LOGIC ) ;

END adder4 ;

ARCHITECTURE Structure OF adder4 ISSIGNAL c1, c2, c3 : STD_LOGIC ;

BEGINstage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;stage3: fulladd PORT MAP (

Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;END Structure ;

”LIBRARY work; ” is omitted since the VHDL compiler always has access to the working directory ”work”.


10

Representation of Numbers in VHDL Code

SIGNAL C: STD_LOGIC_VECTOR(1 TO 3);

• The data type STD_LOGIC_VECTOR represents a linear array of STD_LOGIC data objects.

• C is defined as a three-bit STD_LOGIC signal.

• Each bit of C can be referred to separately using names C(1), C(2), and C(3).

• The syntax (1TO 3) specifies that the most-significant bit in C is C(1) and the least-significantbit is C(3).


11

C <=’’100’’;

Signal Assignment Statements

C(1) <= ’1’;

C(2) <= ’0’;

C(3) <= ’0’;

Single quotes for one-bit signals

Double quotesfor multibitsignals


12

SIGNAL X: STD_LOGIC_VECTOR(3 DOWNTO 0);

• X is a four-bit STD_LOGIC_VECTOR signal.

• The syntax (3 DOWNTO 0) specifies that the most-significant bit in X is X(3) and the least-significant bit is X(0).

X <=’’1100’’;

X(3) <= ’1’;

X(2) <= ’1’;

X(1) <= ’0’;

X(0) <= ’0’;


13

A four-bit adder defined using multibit signals

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.fulladd_package.all ;


X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;

END adder4 ;

ARCHITECTURE Structure OF adder4 ISSIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;

BEGINstage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;

END Structure ;


14

Arithmetic Assigment StatementsS <= X + Y;

16-bit adder

VHDL code for a 16-bit adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;

ENTITY adder16 ISPORT ( X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;

S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;END adder16 ;

ARCHITECTURE Behavior OF adder16 IS BEGIN

S <= X + Y ;END Behavior ;

The package std_logic_signedshould be used.


15

A 16-bit adder with carry and overflow

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;


X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;Cout, Overflow : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;

END Behavior ;

Adder with carry-in, carry-out, and overflow signals


16

Concatenate operator: &

('0' & X) :

Sum <= ('0' & X) + Y + Cin ;

0 X15 X14 X0…

The concatenate operator is needed since VHDL requires at least one of the operands of an arithmeticexpression to have the same number of bits as the result.


17

S <= Sum(15 DOWNTO 0) ;

The lower 16 bits of Sum are assigned to S.

Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;

Overflow is defined by C15 ⊕ C14 .

C15 = Sum(16).

C14 is not directly accessable.

Verify C14 = X(15) XOR Y(15) XOR Sum(15)


18Use of the arithmetic package

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;


X, Y : IN SIGNED(15 DOWNTO 0) ;S : OUT SIGNED(15 DOWNTO 0) ;Cout, Overflow : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;

END Behavior ;

Use of the arithmetic package


19

USE ieee.std_logic_arith.all ;

SIGNAL Sum : SIGNED(16 DOWNTO 0) ;

Use of the arithmetic package

Data types SIGNED and UNSIGNED are defined in the package std_logic_arith.

For use with unsigned numbers:

Use std_logic_unsigned package with STD_LOGIC_VECTOR signals

or

Use std_logic_arith packge with UNSIGNED signals


20

A 16-bit adder using INTEGER signals

ENTITY adder16 ISPORT ( X, Y : IN INTEGER RANGE -32768 TO 32767 ;

S : OUT INTEGER RANGE -32768 TO 32767 ) ;END adder16 ;

ARCHITECTURE Behavior OF adder16 IS BEGIN

S <= X + Y ;END Behavior ;

16-bit adder using INTEGER signals

No LIBRARY or USE clause appears in the code, because the INTEGER type is predefined in standard VHDL.

It is difficult to modify this code to include carry signals and the overflow signal.


21

VHDL code for a 2-to-1 multiplexer


ENTITY mux2to1 ISPORT ( w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 ISBEGIN

WITH s SELECTf <= w0 WHEN '0',

w1 WHEN OTHERS ;END Behavior ;

Select Signal Assignment


22VHDL code for a 2-to-4 binary decoder


ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGINEnw <= En & w ;WITH Enw SELECT

y <= "1000" WHEN "100","0100" WHEN "101","0010" WHEN "110","0001" WHEN "111","0000" WHEN OTHERS ;

END Behavior ;


23

A 2-to-1 multiplexer using a conditional signal assignment





f <= w0 WHEN s = '0' ELSE w1 ;END Behavior ;

Conditional Signal Assignment


24

Code for a 16-to-1 multiplexer using a generate statement

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.mux4to1_package.all ;

ENTITY mux16to1 ISPORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;

s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux16to1 ;

ARCHITECTURE Structure OF mux16to1 ISSIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGING1: FOR i IN 0 TO 3 GENERATE

Muxes: mux4to1 PORT MAP (w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;

END GENERATE ;Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;

END Structure ;

FOR GENERATE statement


25

w 0

En

y 0 w 1 y 1

y 2 y 3

y 8 y 9 y 10y 11

w 2

w 0 w y 0 y 1 y 2 y 3

0

En

y 0 w 1 y 1

y 2 y 3

w 0

En

y 0 w 1 y 1

y 2 y 3

y 4 y 5 y 6 y 7

w 1

w 0

En

y 0 w 1 y 1

y 2 y 3

y 12y 13y 14y 15

w 0

En

y 0 w 1 y 1

y 2 y 3

w 3

En

Example:

A 4-to-16 decoder


26Hierarchical code for a 4-to-16 binary decoder


ENTITY dec4to16 ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ;

END dec4to16 ;

ARCHITECTURE Structure OF dec4to16 ISCOMPONENT dec2to4

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END COMPONENT ;SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;

BEGING1: FOR i IN 0 TO 3 GENERATE

Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) );G2: IF i=3 GENERATE

Dec_left: dec2to4 PORT MAP ( w(i DOWNTO i-1), En, m ) ;END GENERATE ;

END GENERATE ;END Structure ;

IF GENERATE statement


27

• Process Statement– Sensitivity list– Sequential Assignment Statements:

• IF-THEN-ELSE statement• CASE statement

– When the process becomes active, statements are evaluated in sequential order.

– Assignments to signals are only visible when all the statements in the process have been evaluated.

– If there are multiple assignments to the same signal, only the last one has any visible effect.


28

A 2-to-1 multiplexer specified using an if-then-else statement





PROCESS ( w0, w1, s )BEGIN

IF s = '0' THENf <= w0 ;

ELSEf <= w1 ;

END IF ;END PROCESS ;

END Behavior ;


29

Alternative code for a 2-to-1 multiplexer






f <= w0 ;IF s = '1' THEN

f <= w1 ;END IF ;

END PROCESS ;END Behavior ;


30

Code for a one-bit equality comparator


ENTITY compare1 ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END compare1 ;

ARCHITECTURE Behavior OF compare1 ISBEGIN

PROCESS ( A, B )BEGIN

AeqB <= '0' ;IF A = B THEN

AeqB <= '1' ;END IF ;


AeqB<=´0´assigns a default value.


31

An example of code that results in implied memory


ENTITY implied ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END implied ;

ARCHITECTURE Behavior OF implied ISBEGIN

PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;


END Behavior ;

AeqB<=´0´is removed.


32

Circuit generated due to implied memory

A

B AeqB

…PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;

END IF ;END PROCESS ;…

Implied Memory

The VHDL semantics stipulate that in cases where the code does not specify the value of a signal, the signal should retain its current value. You will probably get a warning: a latch is created for this code.


33

A CASE statement that represents a 2-to-1 multiplexer






CASE s ISWHEN '0' =>

f <= w0 ;WHEN OTHERS =>

f <= w1 ;END CASE ;


CASE statement


34

A BCD-to-7-segment decoder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY seg7 IS

PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;

END seg7 ;ARCHITECTURE Behavior OF seg7 ISBEGIN

PROCESS ( bcd )BEGIN

CASE bcd IS -- abcdefgWHEN "0000" => leds <= "1111110" ;WHEN "0001" => leds <= "0110000" ;WHEN "0010" => leds <= "1101101" ;WHEN "0011" => leds <= "1111001" ;WHEN "0100" => leds <= "0110011" ;WHEN "0101" => leds <= "1011011" ;WHEN "0110" => leds <= "1011111" ;WHEN "0111" => leds <= "1110000" ;WHEN "1000" => leds <= "1111111" ;WHEN "1001" => leds <= "1110011" ;WHEN OTHERS => leds <= "-------" ;

END CASE ;END PROCESS ;

END Behavior ;


35


ENTITY regn ISGENERIC ( N : INTEGER := 16 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Resetn, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END regn ;

ARCHITECTURE Behavior OF regn ISBEGIN

PROCESS ( Resetn, Clock )BEGIN

IF Resetn = '0' THENQ <= (OTHERS => '0') ;

ELSIF Clock'EVENT AND Clock = '1' THENQ <= D ;


END Behavior ;

GENERIC construct

Assignment operator :=

Q <= (OTHERS => '0') ;

An n-bit register with asynchronous clear


36

Code for a shift registerLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY shift4 IS

PORT ( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;Clock : IN STD_LOGIC ;L, w : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END shift4 ;

ARCHITECTURE Behavior OF shift4 ISBEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF L = '1' THEN

Q <= R ;ELSE

Q(0) <= Q(1) ;Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= w ;


END Behavior ;

The four assignments are scheduled to occur only after all of the statements in the process have been evaluated. All four flip-flops change their values at the same time.


37

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY shiftn IS

GENERIC ( N : INTEGER := 8 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Clock : IN STD_LOGIC ;L, w : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END shiftn ;ARCHITECTURE Behavior OF shiftn ISBEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF L = '1' THEN

Q <= R ;ELSE

Genbits: FOR i IN 0 TO N-2 LOOPQ(i) <= Q(i+1) ;

END LOOP ;Q(N-1) <= w ;


END Behavior ;

FOR LOOP statement

An n-bit left-to-right shift register


38

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY upcount IS

PORT ( Clock, Resetn, E : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;

END upcount ;

ARCHITECTURE Behavior OF upcount ISSIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

BEGINPROCESS ( Clock, Resetn )BEGIN

IF Resetn = '0' THENCount <= "0000" ;

ELSIF (Clock'EVENT AND Clock = '1') THENIF E = '1' THEN

Count <= Count + 1 ;ELSE

Count <= Count ;END IF ;

END IF ;END PROCESS ;Q <= Count ;

END Behavior ;

Up-Counter


39

A four-bit counter with parallel load, using INTEGER signals


ENTITY upcount ISPORT ( R : IN INTEGER RANGE 0 TO 15 ;

Clock, Resetn, L : IN STD_LOGIC ;Q : BUFFER INTEGER RANGE 0 TO 15 ) ;

END upcount ;

ARCHITECTURE Behavior OF upcount ISBEGIN

PROCESS ( Clock, Resetn )BEGIN

IF Resetn = '0' THENQ <= 0 ;

ELSIF (Clock'EVENT AND Clock = '1') THENIF L = '1' THEN

Q <= R ;ELSE

Q <= Q + 1 ;END IF;

END IF;END PROCESS;

END Behavior;


40

Code for a down-counter

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY downcnt IS

GENERIC ( modulus : INTEGER := 8 ) ;PORT ( Clock, L, E : IN STD_LOGIC ;

Q : OUT INTEGER RANGE 0 TO modulus-1 ) ;END downcnt ;

ARCHITECTURE Behavior OF downcnt ISSIGNAL Count : INTEGER RANGE 0 TO modulus-1 ;

BEGINPROCESSBEGIN

WAIT UNTIL (Clock'EVENT AND Clock = '1') ;IF E = '1' THEN

IF L = '1' THENCount <= modulus-1 ;

ELSECount <= Count-1 ;

END IF ;END IF ;

END PROCESS;Q <= Count ;

END Behavior ;


41

Code for an n-bit tri-state buffer


ENTITY trin ISGENERIC ( N : INTEGER := 8 ) ;PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

E : IN STD_LOGIC ;F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END trin ;

ARCHITECTURE Behavior OF trin ISBEGIN

F <= (OTHERS => 'Z') WHEN E = '0' ELSE X ;END Behavior ;

An n-bit tri-state buffer


42

VHDL code for a simple FSM

USE ieee.std_logic_1164.all ;

ENTITY simple ISPORT ( Clock, Resetn, w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;END simple ;

ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y : State_type ;

BEGINPROCESS ( Resetn, Clock )BEGIN

IF Resetn = '0' THENy <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

con’t ...

TYPE

Create a user-definedsignal type

VHDL code for Moore-type FSMs


43

CASE y ISWHEN A =>

IF w = '0' THENy <= A ;

ELSEy <= B ;

END IF ;WHEN B =>

IF w = '0' THENy <= A ;

ELSEy <= C ;

END IF ;WHEN C =>

IF w = '0' THENy <= A ;

ELSEy <= C ;

END IF ;END CASE ;

END IF ;END PROCESS ;z <= '1' WHEN y = C ELSE '0' ;

END Behavior ;

VHDL code for a simple FSM (con’t)


44

(ENTITY declaration not shown)

ARCHITECTURE Behavior OF simple ISTYPE State_type IS (A, B, C) ;SIGNAL y_present, y_next : State_type ;

BEGINPROCESS ( w, y_present )BEGIN

CASE y_present ISWHEN A =>

IF w = '0' THENy_next <= A ;

ELSEy_next <= B ;

END IF ;WHEN B =>

IF w = '0' THENy_next <= A ;

ELSEy_next <= C ;

END IF ;Alternative style of code

for an FSM

An alternative style of VHDL code for FSMs:

The first process describes the state tableas a combnational circuit. The secondprocess introduces flip-flops into the circuit.

SIGNAL y_present, y_next: State_type;


45

WHEN C =>IF w = '0' THEN

y_next <= A ;ELSE

y_next <= C ;END IF ;

END CASE ;END PROCESS ;

PROCESS (Clock, Resetn)BEGIN

IF Resetn = '0' THENy_present <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THENy_present <= y_next ;


z <= '1' WHEN y_present = C ELSE '0' ;END Behavior ;

Alternative style of code for an FSM (con’t)


46

• Variable Assignment – Formal Definition:

A variable assignment statement replaces the current value of a variable with a new value specified by an expression.

– Simplified Syntax: variable_name := expression ; – The expression assigned to a variable must give

results of the same type as the variable.– Variables should be declared and used in a

process statement (unless it is a shared variable).– Variable assignment takes effect immediately. See VHDL Language Reference Guidehttp://www.itn.liu.se/~andki/vhdl_refguide/index.htm

design of arithmetic circuits using vhdl

Documents