design of asynchronous circuits materials from falkowski
Post on 21-Dec-2015
227 views
TRANSCRIPT
![Page 1: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/1.jpg)
Design of Asynchronous Circuits
Materials from Falkowski
![Page 2: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/2.jpg)
Design of asynchronous circuits
In general, here is the flow of processing.
Natural Language specification
Timing diagram of input and
output signals
Graph of transitions and outputs
![Page 3: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/3.jpg)
Design of asynchronous Machine
Create the initial transition table
Reduce the initial transition table
Encode rows of reduced table
Determine output functionsDetermine transition function
![Page 4: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/4.jpg)
Reduction of pseudo-equivalent states and equivalent states
x1x000 01 11 10 y2y1y0
S
a a b - g 0--
b - b c - 101
c - e c - 1-1
d d b - g 0-0
e - e f - -01
f - - f g 11-
g d - f g 000
h a h f - -11
i - - j i 000
j - h j - 11-
Stable statesNon-stable states
Equivalent states a-d
Compatible outputs Consistent outputs
Equivalent state Equivalent state
dashes
![Page 5: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/5.jpg)
Reduction of equivalent (compatible) states and pseudo-equivalent states
x1x000 01 11 10 y2y1y0
S
a a b - g 0--
b - b c - 101
c - e c - 1-1
d d b - g 0-0
e - e f - -01
f - - f g 11-
g d - f g 000
h a h f - -11
i - - j i 000
j - h j - 11-
Conditionally compatible states b-e condition c=f
Compatible outputs
Consistent outputsCompatible state
Condition
dashes
Conditionally compatible states g –i (condition f=j)
dashes
Consistent outputs
Pseudo-equivalent states
Compatible inputs
Equivalent state
condition
dashes
![Page 6: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/6.jpg)
Reduction of equivalent (compatible) and pseudo-
equivalent statesx1x0
00 01 11 10 y2y1y0S
a a b - g 0--
b - b c - 101
c - e c - 1-1
d d b - g 0-0
e - e f - -01
f - - f g 11-
g d - f g 000
h a h f - -11
i - - j i 000
j - h j - 11-
Pseudo-equivalent states c-f
Compatible inputs
Consistent outputs
Pseudo-equivalent states
dashes
Consistent outputs
Pseudo-equivalent states
Compatible inputs
Pseudo-equivalent states
dashes
Pseudo-equivalent states
Pseudo-equivalent states f-j
![Page 7: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/7.jpg)
Reduction of equivalent and pseudo-equivalent states
x1x000 01 11 10 y2y1y0
S
a a b - g 0--
b - b c - 101
c - e c - 1-1
d d b - g 0-0
e - e f - -01
f - - f g 11-
g d - f g 000
h a h f - -11
i - - j i 000
j - h j - 11-
States b-h
Compatible inputs
Inconsistent outputs
States e-hCompatible inputs
Inconsistent outputs
![Page 8: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/8.jpg)
Results of reducing compatible and pseudo-equivalent statesx1x0
00 01 11 10 y2y1y0S
a,d a b - g 0-0
b,e - b c - 101
c,f - b c - 111
g a - c g 000
h a h c - -11
i - - j i 000
j - h j - 11-
Compatible states a-d, conditionally compatible states b-e and pseudo-equivalent states c-f.
![Page 9: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/9.jpg)
Reduction of compatible states of Moore Machine
x1x000 01 11 10 y2y1y0
S
a,d a b - g 0-0
b,e - b c - 101
c,f - b c - 111
g a - c g 000
h a h c - -11
i - - j i 000
j - h j - 11-
Compatible states a,d-gConsistent outputs
![Page 10: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/10.jpg)
Result of reduction of compatible states for Moore Machine
x1x000 01 11 10 y2y1y0
S
a,d,g a b - g 000
b,e - b c - 101
c,f - b c - 111
h a h c - -11
i - - j i 000
j - h j - 11-
![Page 11: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/11.jpg)
Reduction of compatible states of Mealy Machine
x1x000 01 11 10 y2y1y0
S
a,d a b - g 0-0
b,e - b c - 101
c,f - b c - 111
g a - c g 000
h a h c - -11
i - - j i 000
j - h j - 11-
![Page 12: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/12.jpg)
Results of reduction of compatible states of Mealy Machine
x1x000 01 11 10
S
a,b,c,d,e,f a b c g
g,h a h c g
i,j - h j i
![Page 13: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/13.jpg)
Outputs in Moore Machine
x1x000 01 11 10 y2y1y0
S
a,d,g a b - g 000
b,e - b c - 101
c,f - b c - 111
h a h c - -11
i - - j i 000
j - h j - 11-
![Page 14: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/14.jpg)
Outputs in Mealy Machinex1x0
00 01 11 10S
a,b,c,d,e,f a b c g
0-0 101 111
g,h a h c g
-11 000
i,j - h j i
11- 000
x1x0y2y1y0
S
a,d 0-0
b,e 101
c,f 111
g 000
h -11
i 000
j 11-
Outputs for stable states
![Page 15: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/15.jpg)
Outputs in Mealy Machinex1x0
00 01 11 10S
a,b,c,d,e,f a b c g
0-0 101 111 0-0
g,h a h c g
0-0 -11 -11 000
i,j - h j i
--- -1- 11- 000
agg 0-0g000 = 0-0
bgg 101g000 = -0-
cgg 111g000 = - - -
haa -11a0-0 = - - -
gaa 000a0-0 = 0-0
hcc -11c111 = - 11
gcc 000c111 = - - -
ihh 000h-11 = - - -
jhh 11-h-11 = - 1 -
Outputs for non-stable states
![Page 16: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/16.jpg)
Encoding an asynchronous machine
x1x000 01 11 10 y1y0
S
a a b a d 00
b d b b b 01
c a c b d 11
d d c d d 10
Moore Machine table
![Page 17: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/17.jpg)
Racesx1x0
00 01 11 10 y1y0S
00 a a b a d 00
01 b d b b b 01
10 c a c b d 11
11 d d c d d 10
a b
cd
00 01
11 10
![Page 18: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/18.jpg)
Elimination of races by cyclic coding
a b
c
d
000
001
101
111
S
100
S
S
S
011
110
010
a b
cd
00 01
11 10
![Page 19: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/19.jpg)
a b
c
d
000
001
101
111
S
100
S
S
S
011
110
010
x1x000 01 11 10 y1y0
S
000 a a b a 100 00
001 b d b b b 01
010 a 0 -
011 b - 1
100 d - 0
101 d d c d d 10
110 010 - 1
111 c 110 c 011 d 11
![Page 20: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/20.jpg)
Encoding of asynchronous Machine
x1x0
00 01 11 10 y1y0S
000 a 000 001 000 100 00
001 b 101 001 001 001 01
011 - - 001 - - 1
010 000 - - - 0 -
110 010 - - - - 1
111 c 110 111 011 101 11
101 d 101 111 101 101 10
100 - - - 101 - 0
![Page 21: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/21.jpg)
Realization of memory and outputs
We design an asynchronous circuit specified by a timing diagram. The method works for both Moore and Mealy.
1 2 3 4 52 1x0
x1
z
![Page 22: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/22.jpg)
Moore Machine – initial table 1 2 3 4 52 1
x0
x1
z
1/0
2/0
3/04/1
5/0
00
1100
10
01
01
00
x1x0
00 01 11 10 ZS
S1 S1 S2 - - 0
S2 S4 S2 S3 - 0
S3 - S2 S3 - 0
S4 S4 - - S5 1
S5 S1 - - S5 0
01
1100
10
![Page 23: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/23.jpg)
We reduce the equivalent states
x1x0
00 01 11 10 ZS
S1 S1 S2 - - 0
S2 S4 S2 S3 - 0
S3 - S2 S3 - 0
S4 S4 - - S5 1
S5 S1 - - S5 0
Only states S1 and S4 are in the same column
But these states have inconsistent outputs
![Page 24: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/24.jpg)
Reduction of compatible states for Moore Machine
x1x000 01 11 10 Z
S
S1 S1 S2 - - 0
S2 S4 S2 S3 - 0
S3 - S2 S3 - 0
S4 S4 - - S5 1
S5 S1 - - S5 0
• For Moore Machine, compatible are states S1, S3 and S5.
• These states have consistent outputs.
• State S2 does not belong to this group because it includes state S4, which has inconsistent output with respect to remaining states
x1x000 01 11 10 Z
S
S1,S3, S5 S1 S2 S3 S5 0
S2 S4 S2 S3 - 0
S4 S4 - - S5 1
After reduction, table of Moore Machine is created
![Page 25: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/25.jpg)
Reduction of compatible states for Moore Machine
x1x000 01 11 10 Z
S
S1 S1 S2 - - 0
S2 S4 S2 S3 - 0
S3 - S2 S3 - 0
S4 S4 - - S5 1
S5 S1 - - S5 0
For Moore Machine compatible are states S1 and S5 as well as S2 and S3. These states have consistent outputs.
x1x000 01 11 10 Z
S
S1, S5 S1 S2 - S5 0
S2, S3 S4 S2 S3 - 0
S4 S4 - - S5 1
After reduction, we get Moore Machine table.
![Page 26: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/26.jpg)
Reduction of compatible states of Mealy Machine
x1x000 01 11 10
S
S1 S1 S2 - -
S2 S4 S2 S3 -
S3 - S2 S3 -
S4 S4 - - S5
S5 S1 - - S5
x1x000 01 11 10
S
S1, S3,S 5 S1 S2 S3 S5
S2, S4 S4 S2 S3 S5
S Z
S1 0
S2 0
S3 0
S4 1
S5 0
x1x000 01 11 10
S
S1, S3,S 5 0 0 0 0
S2, S4 1 0 0 0
State table
Output table
![Page 27: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/27.jpg)
Encoding
Encoding is done for Moore (first) and next for Mealy Machine.
x1x000 01 11 10 Z
S
00a={S1,S3,
S5}a b a a 0
01 b=S2 c b a - 0
10 c=S4 c - - a 1
a b
c
00 01
11
10
![Page 28: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/28.jpg)
Encoded table of Moore Machine
x1x000 01 11 10 Z
S
00a={S1,S3,
S5}a b a a 0
01 b=S2 11 b a - 0
11 c - - - -
10 c=S4 c - - a 1
x1x000 01 11 10 Z
Q1Q0
00 00 01 00 00 0
01 11 01 00 - 0
11 10 - - - -
10 10 - - 00 1
![Page 29: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/29.jpg)
Transition Function of Moore Machine
x1x000 01 11 10
q1(t)q0(t)
00 0 0 0 0
01 1 0 0 -
11 1 - - -
10 1 - - 0
x1x0
00 01 11 10q1(t)q0(t)
00 0 1 0 0
01 1 1 0 -
11 0 - - -
10 0 - - 0
q1(t+1)
q0(t+1)
1 1
1
1
1 1
1 1
0
0 01
0
0 0
q t x
q t
q t +1 = +
q t +1 = +
q t +1
x
q t x
q t x
q t x
q t x=
1 0
1 0
1 0 1
1 0 1
0 1 0
0
1 0 1
0
q t q t x
Q
q t 1
q t 1
q t
x x
x x
x x
t Q t
q1
x
t q t x
![Page 30: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/30.jpg)
Output function of Moore Machine
q1(t)q0(t) Z
00 0
01 0
11 -
10 1
1Z t = q t
![Page 31: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/31.jpg)
Realization with logic gatesU1
NAND2
U2
NAND2
U3
NAND2
U4
NAND3
U5
NAND2
U6
NAND2
U7
NOT
U8
NOT
x0
x1
Q1
Q0
U9
NOT
Simulation: przyklad002.msm
![Page 32: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/32.jpg)
Realisation using type sr asynchronous FFs.
We will use asynchronous sr FF, that has the following transition table.
q(t)q(t+1) s r
0 0 0 -
0 1 1 0
1 0 0 1
1 1 - 0
![Page 33: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/33.jpg)
SR FF has two inputs for which we have to find corresponding inputs, using transition table of the FF
x1x0
00 01 11 10q1(t)q0(t)
0 0 0 0 0 0
0 1 1 0 0 -
1 1 1 - - -
1 0 1 - - 0
Q1(t+1)
q(t)q(t+1) s r
0 0 0 -
0 1 1 0
1 0 0 1
1 1 - 0
x1x0
00 01 11 10
q1(t)q0(t)
0 0 0 0 0 0
0 1 1 0 0 -
1 1 - - - -
1 0 - - - 0
s1(t+1)
x1x0
00 01 11 10
q1(t)q0(t)
0 0 - - - -
0 1 0 - - -
1 1 0 - - -
1 0 0 - - 1
r1(t+1) 1 0 0s t +1 = q t x 1 1r t +1 = x
![Page 34: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/34.jpg)
q0(t+1) q(t)q(t+1) s r
0 0 0 -
0 1 1 0
1 0 0 1
1 1 - 0
x1x0
00 01 11 10
q1(t)q0(t)
0 0 0 1 0 0
0 1 - - 0 -
1 1 0 - - -
1 0 0 - - 0
s0(t+1)
x1x0
00 01 11 10
q1(t)q0(t)
0 0 - 0 - -
0 1 0 0 1 -
1 1 1 - - -
1 0 - - - -
r0(t+1) 0 1 0s t +1 = x x
0 1 1
0 1 1
0 1 1
r t +1 = q t + x =
r t +1 = q t + x
r t +1 = q t x
x1x0
00 01 11 10q1(t)q0(t)
00 0 1 0 0
01 1 1 0 -
11 0 - - -
10 0 - - 0
![Page 35: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/35.jpg)
Realisation using asynchronous SR FR.U7
NOT
U8
NOT
x0
x1
Q1
Q0
U10
SR_FF
Q
~Q
S
R
U11
AND2
U3
SR_FF
Q
~Q
S
R
U1
AND2
U4
NAND2
Simulation:przyklad003.msm
![Page 36: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/36.jpg)
Solution for Mealy Machine
x1x000 01 11 10
S
S1, S3,S 5 S1 S2 S3 S5
S2, S4 S4 S2 S3 S5
x1x000 01 11 10
S
S1, S3,S 5 0 0 0 0
S2, S4 1 0 0 0
State Table
Output table
![Page 37: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/37.jpg)
Encoded Mealy Machine Table
x1x000 01 11 10
S
S1, S3,S 5 0 S1 S2 S3 S5
S2, S4 1 S4 S2 S3 S5
x1x000 01 11 10
q(t)
0 0 1 0 0
1 1 1 0 0
![Page 38: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/38.jpg)
Transition and output functions of Mealy Machine
x1x000 01 11 10
q(t)
0 0 1 0 0
1 1 1 0 0
q(t+1)
1 1 0q t xq 1 = + x+ xt
x1x000 01 11 10
q(t)
0 0 0 0 0
1 1 0 0 0
State table
Output tableZ
1 0Z q t x x
![Page 39: Design of Asynchronous Circuits Materials from Falkowski](https://reader031.vdocuments.net/reader031/viewer/2022032521/56649d585503460f94a37a3a/html5/thumbnails/39.jpg)
Realization using logic gates
U8
NOT
x0
x1
Q1
U11
AND2U1
OR2
U2
AND2
X1
pamiec
x0
x1
Q1
T R
X
X
X
X
0
0
0
0
15
016
31
XWG1
QC T
1
F
XLA1
U1
NOT
U2
NOT
U3
AND3
Simulation:przyklad005.msm