UNIVERSITY OF SOUTHAMPTON

Design of CMOS OpAmp

for a D/A Converter

Buffer MSc Design Assignment

Manraj Singh Gujral

msg1g10

16th

May 2011

1

Contents 1. Introduction .................................................................................................................................... 2

2. Hand Calculations ........................................................................................................................... 2

3. Circuit Simulation ............................................................................................................................ 8

i. AC Analysis Small Signal: ............................................................................................................. 8

ii. DC Sweep Simulation: ................................................................................................................. 8

iii. AC small signal Gain/Phase Simulation – Set-up vs. Common Model Level ............................... 9

1. Modifications .......................................................................................................................... 9

iv. Large Signal Step Response simulation ................................................................................. 11

v. Large Signal Sine Full Power Bandwidth Simulation ................................................................. 13

vi. Slew Rate Simulation ............................................................................................................ 14

4. Result ............................................................................................................................................ 16

5. Conclusion ..................................................................................................................................... 16

6. References .................................................................................................................................... 16

7. Appendix: ...................................................................................................................................... 17

Test 1 ................................................................................................................................................. 17

Test 2 ................................................................................................................................................. 17

Test 3 ................................................................................................................................................. 18

Test 4 ................................................................................................................................................. 19

Test 5 ................................................................................................................................................. 20

TABLE for HAND CALCULATION PROCESS PARAMETERS .................................................................. 20

Body connections Connected to VDD for the Differential Pair PMOS .............................................. 21

Ac Analysis of OpAmp with Bulk connected to Vdd (Std NWell Process) ......................................... 21

2

1. INTRODUCTION

This report describes the design process of a simple CMOS OpAmp with specified parameters. The

Design is carried out in 0.35µm N-Well Process. The Specifications of the Design are as shown in the

Table below:

Parameter Value

Power Supply, VDD 3.3V

VSS 0V

Input Signal Range 0.2V to 1.2V

App. Mode Gain x 2 non-inverting mode using 10kΩ

Output Range 0.4V - 2.4V

Output Load Conditions Capacitance of 0 to 30pF

Resistance : 10kΩ to infinity

DC Gain > 60dB (with all specified loads)with input

common mode of 0.2V to 1.2V

Full power Bandwidth > 100kHz at 2V p-p

Phase Margin > 45deg

Settling Time within 1% of final value within 500ns with less

than 15% overshoot

Bias Current 25µA

The report accompanies a list of items in Appendix. Appendix contains the MOS Parameter Sheet

that was used for calculations. The Test circuits, those were specified in the specification sheet, have

been listed in the Appendix to avoid duplication they whereas their waveforms form a part of the

main body of Report.

2. HAND CALCULATIONS

For this exercise we will employ the use of a 2 stage OpAmp.

It can be shown from the transfer function of an OpAmp that

≅ 0.22 × - for a Phase Margin of atleast 60o

[2]

Table1 : A list of specifications

Fig. 1 : A 2-Stage OpAmp model which gives an advantage by Better output voltage swing and Compensation[1]

3

= 0.22 × 30 × 10 = 6.6 ≈ 5.85(. ) - Since we do not need a phase margin of

60o but atleast better than 45

o .

=!"1!"6#!"6 + %&'()!"6 − %&'%&' +,() = 1!"6 -.ℎ0., =!"1%&'

i.e, for 234526 = 1 , i.e, unity Gain Bandwidth, we have

&' = !"1, , 27,' = !"1 - Eqn. (1)

Degrees

Fig. 2: (a) 2-Stage Op-amp circuit (b) equivalent small signal model [1]

Fig. 3: Bode Plot as per the Specifications

4

From the bode plot of the specification as shown in figure 3 , we assume a single pole drop of -

20dB/Dec from 40dB at 100 kHz to arrive at unity gain frequency of about 10 MHz. Also at this point

the Phase margin required should be more than 45O.

Therefore we substitute, f = 10MHz in Eqn. (1).

2710 × 108 × 5.85 × 10 = !"1

Eqn. (2)

It is specified that the OpAmp should have full power bandwidth greater than 100 kHz at 2V peak to

peak.

i.e., we can find out Slew Rate, as '9:;<=>;?@:<=>A= . Where time is nothing but 1/frequency

Therefore, B( ≥ D EEFFGH ≥ 1.25 V/µs.

We improve the Slew Rate of our design, and take SR = 5 V/µs (assumption)

Since, SR = ITAIL / CLoad

5 ×108 = IJ:>@30 × 10 IJ:>@ = 150 × 10−6K

Therefore with a Tail Current of 150µA, we use the Trans-conductance formula to calculate the W/L

of the MOS 1, as represented in Figure 2. (a)

We know that for a MOS device in Saturation,

!" =L2IMNOPQ RS

T = ;<AUVWXY3Z Eqn. (3) [1]

Assuming a Tail Current, ITAIL = 150µA and OP= 50 x 106

µA/V2 , n (at VBS=0V) = 1.33 for PMOS, we

get

Eqn. (4)

According to the specifications the Inputs to the OpAmp are in the range of

Vmin = 0.2V, and V max =1.2V

We need to ensure that none of the MOS transistors in the first stage goes into the Triode Region in

this range of input voltages. It is critical that we look at the various voltage w.r.t Gate, Source and

Drain terminals for P- and N-MOS devices.

RS , = 28.29

!"1 = 4 ×10 ]"ℎ =gm2

5

D

S

G+

-

+

(2) In Saturation Region

Vth

D

S

G

-

+

+

(2) At the Edge of Triode Region

D

S

G-

+

+

(1) In Triode Region

D

S

G+

-

-

(1) In Triode Region

Vth

D

S

G+

-

-

(2) At the Edge of Triode Region

D

S

G-+

-

(3) In Saturation Region

(a) PMOS Regions

(a) NMOS Regions

It is not readily straight forward when we try to write the Triode-Saturation boundary voltage

equations for POMS and NMOS. In our Amplifier we have PMOS in our differential pair (M1 and M2,

ref figure 2. (a)) and the current mirrors are made from NMOS (M3 and M5). We would need to

revisit this figure 4 when taking in terms of VSG , i.e., Voltage of Source w.r.t Gate, and VGD ,i.e.,

Voltage of Gate w.r.t Drain, when solving for Vmax and Vmin. Please note that , for example, in an

NMOS the voltage at Drain is higher than the Source voltage even though both are labelled as

negative (-). – and + signs are for representation purpose only attempting to explain the relationship

between Gate and Source potential in terms of magnitude.

First we attempt to study the effect of Vmin on the Current mirrors, M3 and M4.

Vsd

Vsg

Vmax

Vdd

M1

M5

M3

Vsd

Vgd

Vmin

Vdd

M1

M5

M3

Vss VssVgs

Vsd across M5 will be low and the

device might slip into Triode region

of Operation

Vsd across M3 will be low and the

device might slip into Triode region

of Operation

(a) (b)

Vbias Vbias

M4

Fig. 4: Conceptual Visualization of voltage references in

Saturation & Triode Regions for PMOS and NMOS [3]

Fig. 5: Vmax and Vmin of the input voltage and its effect on the 1st

Stage

(Neglecting Back Gate effects in M1 (and M2: its pair) since it is connected to Source)

6

When minimum voltage is applied at the input, it should be over VSS by the amount as

A>; = NN + M(_) + N(_`) Eqn. (5)

At the edge of the saturation region (and also from figure 4) we know that

MN = N(_`) − |J(;)|

VT(n) is the Threshold voltage of the NMOS. We have assumed that the bulk and the source terminals

of both NMOS and PMOS are connected to their resp. source terminals, and therefore no body

effect comes into play.

Also VGD is the potential difference between Gate and Drain terminals of PMOS M1. Analysing the

PMOS at the edge of saturation region in figure 4, we modify Equation (5) as

A>; = NN + b−cJ(d)ce + bMN(_`) +cJ(;)ce A>; = NN + (−cJ(d)c) + (f×VWXg×;Yh3Zij +cJ(;)c) Eqn.(6)

It is assumed that the Back Gate effect on Threshold voltage is zero. Although it is a standard 0.35µm

N-Well Process, but the Bulk is connected to the Source for calculation purpose.

Substituting the Values of Vmin = 0.2 V, IDS1= ITAIL/2 , and remaining values from the Hand Calculations

Process Parameters Chart, attached in the Appendix, we get the values of W/L of the Current mirror

NMOS as

Eqn.(7)Similarly for maximum value of input voltage we can write the equation as

A:P = MM − NM(_o) −N^(_)

A:P = MM − NM(_o) −NM(_) −cJ(d)c A:P = MM − NM(_o) −f×VWXE×;Yp3Zij −cJ(d)c Eqn.(8)

Substituting the values for VDD = 3.3V , IDS1= ITAIL /2 and from the given Hand Calculations Process

Parameters Chart, we find that

Eqn.(9)

Now,

!A8 = 2.2!A DjqH = 2.2 × 4 ×10 ] × .22 Eqn.(10)[2]

RS `,] = 11.08

RS o = 11.08

7

Eqn.(11)

BtQu., RS 8RS `v = #!"8!"`+

Eqn.(12)

Kwx, IMN8 = RS 3y!"6!"3

z = IMN8 = 6.75 × 10 8K

RS | =

RS o #

IMN8IMNo+

Eqn.(13)

!"6 4.52 10`"/

R

S 8

99.89

R

S |

25.76

Fig.6: Op-Amp Circuit designed with the following parameters:

W/L (1,2) = 28 W/L (3,4) = 11

W/L (5) = 11 W/L (6) =100

W/L (7) = 27 W/L (8) = 1

Cc = 6pF

8

3. CIRCUIT SIMULATION

i. AC Analysis Small Signal:

ii. DC Sweep Simulation:

Fig. 7 : Waveform for AC Analysis – Small Signal (at DC offset of 0.2V):

1. Low frequency gain > 62o

2. Gain at 100kHz ≈ 43dB

3. Phase Margin > 54o

Fig.8 : Waveform for DC sweep simulation

9

iii. AC small signal Gain/Phase Simulation – Set-up vs. Common Model

Level

Clearly, the Low frequency Gain at low DC offset is not as per the requirement. Although the

specification requiring 40dB at 100 kHz is achieved.

1. Modifications

Therefore certain changes were made to increase the gain.

1. Tail current in Stage-I was reduced by lowering the W/L ratio to increase the overall

output gain.

2. M6 Transistor size was increased.

3. Compensation Capacitance, Cc, lowered from 5.8pF to 4.5pF to maintain the 40dB at

100 kHz.

Please note that these changes were made iteratively by re-plotting the waveforms after

small (delta) changes- parametric sweep of M6 Transistor keep all other values constant.

The final values of the W/L of Tail Current MOS (M3) and the output stage M6 to achieve a

low frequency gain of at least 60dB are shown in Fig.10

Fig.9 : Waveform for AC small signal Gain/Phase Simulation – Set-up vs. Common Model Level

1. Low frequency gain at Dc offset 0.2V ≈ 48o

2. Low frequency gain at Dc offset 1.2V ≈ 57o

10

Fig.10 : Re-Calculated Op-Amp parameters. The Changes made are:

1. W/L of M6 = 400

2. W/L of M5 = 3

Fig.11 : Waveform for the recalculated OpAmp in

AC small signal Gain/Phase Simulation – Set-up vs. Common Model Level

1. Low frequency gain at Dc offset 0.2V > 60o

2. Gain at 100kHz ≈ 40o

3. Phase margin of 71o

(at DC offset of 0.2V) and 60o (at DC offset of 1.2V)

11

Input Voltage (mV) Output Voltage(mV) Offset Voltage(mV)

306.771 610.72 9.20E-03

619.271 1235.67 4.64E-03

903.125 1803.29 3.28E-03

Average Offset 5.70E-03

The value of offset is generally very low. If we take an average offset is about .0057 mV in the feedback

system.

iv. Large Signal Step Response simulation

Fig.12: Waveform for DC sweep simulation for recalculated OpAmp, with intermediate points to show offset

Fig.13: Waveform for Large Signal Step Response simulation

Table 2: Offset at various points on the waveform

12

From the waveform in figure 14, we can calculate the rise time of our OpAmp.

Vmax = 2.39659 V

Vmin = 1.9974 V

Vmax –Vmin = 0.39951

Therefore, we calculate the Rise time as the time taken from 10% of the voltage range to

90% of the voltage range.

10% of Voltage range = 2.036V

90% of the Voltage range = 2.356V

These values can be seen on the waveform.

Rise Time (for the final step) ≈ 55.82ns

Fig.14 : Zoomed in view of the Signal Step Response simulation

13

v. Large Signal Sine Full Power Bandwidth Simulation

Fig. 15 : Waveform for Large Signal Sine wave at 10 kHz

Fig.16 : Waveform for Large Signal Sine wave at 100 kHz

Fig.17 : Waveform for Large Signal Sine wave at 1MHz

(2)

(1)

14

From the waveform in figure 17, we can observe two important points:

1. The maximum peak of the output is reduced from 2.19V in 10 kHz to 2.18V in

1MHz test. This is due to the AC characteristics of the OpAmp as illustrated in

Figure. As the frequency increases the Gain starts to roll off.

2. The Peaks of input voltage and output voltage occur at different time. Vpeak –input

occurs at 1.252µs where as Vpeak –output at 1.287µs. This is due to the reducing

phase margin as we go to higher frequencies. This can also be seen from the AC

characteristics in Figure 11

vi. Slew Rate Simulation

We are driving this circuit a little higher than the required output range for the sake of this

test.

Fig.19 : OpAmp being driven to an output of 0.8V to 2.8V.

Fig.18 : Circuit to simulate the Slew Rate. R-load = 10k, and Capacitance =10pF

15

Rise time, Tr = 0.6715µs

Slew Rate = ∆2

∆

=.~o .|~|

.8o

S.R. = 3.46/Ox

Since we had reduced the Tail Current in the Design Process, therefore our initial calculated

Slew Rate of 5 V/ µs (approx.) is reduced to 3.46 V/ µs.

Fig. 20: A Zoomed-in view of the rising edge of the output waveform.

90% ∆Vout = 2.712 V , 10%∆Vout = 1.0091V

16

4. RESULT

All the design parameters listed in table1 are achieved. The tests and their test circuits (in

Appendix) are accompanied by waveforms. Below is the list of values calculated for the

OpAmp Parameters. There are deviations from the calculated values and the cause of those

is listed in the remarks.

Calculated Values Actual Simulation values Remarks

M1 28/1 28/1 -

M2 28/1 28/1 -

M3 11/1 11/1 -

M4 11/1 11/1 -

M5 11/1 3/1 To reduce the Tail Current

M6 100/1 400/1 To improve the Gain for Large

signal AC Test.

M7 27/1 27/1 -

M8 1/1 1/1 -

Cc 5.8pF 4.5pF To improve the 100kHz Gain value

IBias 25µA 25µA -

5. CONCLUSION

Although a lot of design equations and results match the final calculated values, there still

remains the issue of accuracy of calculations and usage of various formulae. In this

particular exercise, VBS = 0V. If for the PMOS differential pair, the Body was connected to

VDD then the Threshold Voltages would have changed and our design would require

different set of values.

An AC analysis of Body connected to VDD, with the actual simulated values obtained in Table

4, is simulated and attached in Appendix for reference.

6. REFERENCES

[1] Prof. W Redman-White, Analogue & Mixed Signal CMOS Design, Lecture Notes 2011, Dept. of Electronics & Computer Science,

University of Southampton. 2010-11

[2] Phillip E. Allen, Douglas R. Holberg, CMOS Analog Circuit Design, 2nd edition.2002

[3] Behzad Razavi , Design of Analog CMOS Integrated Circuits, 17th Reprint, Tata McGraw-Hill Edition 2002.

Table 4: A list of Calculated vs. Actual Simulation Values

17

7. APPENDIX:

Test 1

Test 2

OP-AMP BASIC AC (Small Signal) GAIN/PHASE SIMULATION TEST SET-UP

Vout

10 ΩΩΩΩ

Vin:

AC - Use AC value of 1V for small signal simualtions

+

_

VSS 0V

VSS +3.3V

10

1µµµµF

VinCM:

Put DC source in series to set common mode of input Minimum range 0.2V - 1.2V

RL

CL

OP-AMP DC SWEEP SIMULATION TEST SET-UP

Vout

Vin:

Sweep DC value to obtain output range

+

_

VSS 0V

VSS +3.3V

RL = 10kΩ −> οοΩ −> οοΩ −> οοΩ −> οο

10kΩΩΩΩ

10kΩΩΩΩ

18

Test 3

OP-AMP AC (Small Signal) GAIN/PHASE SIMULATION TEST SET-UP vs COMMON MODE LEVEL

Vout

Vin:

AC - Use AC value of 1V for small signal simualtions

+

_

VSS 0V

VSS +3.3V10 ΩΩΩΩ

10

100µµµµF

VinCM:

Put DC source in series to set common mode of input Minimum range 0.2V - 1.2V

RL

CL

10 ΩΩΩΩ10

Resistors set DC output level to 2X input DC, but AC gain is open loop due to large capacitor

RFB = 20kΩΩΩΩ

Loading of feedback resistor network needed for X2 gain added in parallel for open loop gain test

19

Test 4

OP-AMP LARGE SIGNAL STEP RESPONSE SIMULATION TEST SET-UP

Vout

Vmin DC value 0.2V

+

_

VSS 0V

VSS +3.3V10kΩΩΩΩ

10kΩΩΩΩ RL

CL

t

V1

V2

V3

V4

V5

V1

V2

V3

V4

V5

V1-5 Pulse sources. Each 1ns rise time, 0V - 0.2V step, Time between edges when added = 1us

20

Test 5

TABLE for HAND CALCULATION PROCESS PARAMETERS

(Lmin = 0.35µm, Vdd max = 3.3V) Parameter N P Units

µCox 200 50 µµµµA/V2

Cox 4.3 4.3 fF/µµµµ2

n (at VBS = 0) 1.33 1.33

θθθθ 0.3 0.3 V-1

εC 1.75 4.5 V/m

CGDo 250 250 aF/µµµµ CGSo 250 250 aF/µµµµ

λλλλ 0.05/(L – 0.1) 0.05/(L – 0.1) V-1

VTO 0.6 0.7 V

CDB 1.1 1.1 fF/µµµµ2

Assume Drain & Source area are (0.7xW)µµµµ2 2 2 2 CSB 1.1 1.1 fF/µµµµ

2

γγγγ 0.4 0.6 V1/2

ΦB 0.7 0.7 V

OP-AMP LARGE SIGNAL SINE FULL POWER BANDWIDTH SIMULATION TEST SET-UP

Vout

Vin:

Sine 0.5V pk 10kHz, 100kHz 1MHz

+

_

VSS 0V

VSS +3.3V

VinCM:

Put DC source in series to set common mode of input at 0.6V

10kΩΩΩΩ

10kΩΩΩΩ RL

CL

21

Body connections Connected to VDD for the Differential Pair PMOS

Ac Analysis of OpAmp with Bulk connected to Vdd (Std NWell Process)

Fig. 22 : For Bulk Connections connected to VDD for Differential Pair PMOS.

The performance degrades. Gain at 0.2V DC offset ≈ 29 dB

Fig. 21 : OpAmp Circuit showing body connection