design of control unit_old

8/17/2019 Design of Control Unit_old

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Design of Control Unit:

To execute an instruction, the control unit of the CPU must generate the requiredcontrol signal in the proper sequence. As for example, during the fetch phase, CPU

has to generate PCout signal along with other required signal in the first clock pulse.

In the second clock pulse CPU has to generate PCin signal along with other requiredsignals. So, during fetch phase, the proper sequence for generating the signal to

retriee from and store to PC is PCout and PCin.

To generate the control signal in proper signal, a write ariet! of techniques exists.

"ost of these techniques, howeer, fall into one of the two categories.

#. $ardwired control%. "icro programmed Control

Hardwired Control:

In this hardwired control techniques the control signals are generated &! means ofhardwired circuit. The main o&'ect of control unit is to generate the control signal in

proper sequence.

Consider the sequence of control signal required to execute the add instruction that is

explained in preious lecture. It is o&ious that eight non(oerlapping time slots arerequired for proper execution of the instruction represented &! this sequence.

)ach time slot must &e at least long enough for the function specified in the

corresponding step to &e completed. Since, the control unit is implemented &! hardwaredeice, and eer! deice is haing a propagation dela!, due to which it requires some

time to get the sta&le output signal at the output port after giing the input signal. So, toout the time slot is a complicate design task.

*or the moment, for simplicit!, let us assume that all time slots are equal in duration.

Therefore the required controller ma! &e implemented &ased upon the use of a counterdrien &! a clock.

)ach state, or count, of this counter corresponds to one of the steps of the control

sequence of the instructions of the CPU.

In the preious lecture, we hae mentioned control sequence for execution of two

instructions onl!. +ne is for add and other one is for &ranch-. ike that we need todesign the control sequence of all the instructions.

/! looking into the design of CPU, we ma! sa! that there are arious instruction for addoperation. As for example

Add 0um 1# Add the contents of memor! location specified &! 0U" to the

Contents of register 1#. 1# 1# 2 30U"4


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Add 1%, 1# Add the contents of register 1% to the contents of register 1#.

1# 1# 2 1%

The control sequence for execution of these two add instruction are different, of course,

the fetch phase of all the instruction remain same.

It is clear that control signals depend on the instruction, i.e the contents of the instruction

register. It is also o&sered that execution of some of the instructions depend on the

contents of condition code or status flag register, where the control sequence depends onthe condition code. This is o&sered in conditional &ranch instruction.

$ence the required control signals are uniquel! determined &! the following

• Contents of the control counter

• Contents of instruction register

• Contents of the condition code and other status flags.

The status flags represent the arious state of the CPU and arious control lines

connected to it, such as "*C status signal.

The structure of control unit can &e represented in a simplified iew &! putting it in &lock

diagram. The detached hardware inoled ma! &e explored step &! step. The simplified

iew of the control unit is gien in the figure. +A-

The decoder5encoder &lock is simpl! a com&inational circuit that generates the required

control outputs, depending on the state of all its input.


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The decoder part of decoder5encoder part proide a separate signal line for each control

step, or slot in the control sequence. Similarl!, the output of the instructor decoder

consists of a separate line for each machine instruction. That is, for an! instruction loadedin the I1, one of the output line I0S# to I0Sm is set to # and all others lines are set to 6.

All input signals to the encodes &lock should &e com&ined to generate the indiidualcontrol signals.

In the preious section we hae mentioned control sequence of the instruction. Addcontents of memor! location

Address in memor! direct mode to register 1# +A778"7-, 9Control sequence for an

unconditional &ranch instruction +/1-:, also we hae mentioned a&out /ranch on

negatie +/10-. Consider those three CPU instructions A778"7, /1, /10.

It is required to generate man! control signals &! the control unit. These are &asicall!

coming out from the encoder circuit of the control signal generator. The control signals

are like, PCin, PCout, ;in, ;out, "A1in, add, )nd etc.

/! looking into the a&oe three instruction, we can write the logic function for ;in as<

;in = T# 2 T>

*or all instructions, in time step # we need the control signal ;in to ena&le the input to

register ; in time c!cle T> of A778"7 instruction, in time c!cle T? of /1 instruction

and so on.

Similarl!, the /oolean logic function for add signal is

Add = T# 2 T>.A778"7 2 T?./1 2 @@@@@@@.

These logic functions can &e implemented &! a two leel com&inational circuit of A07

and 1 gates.

Similarl!, the )nd control signal is generated &! the logic function<

)nd = T.A778"7 2 "B./1 2 +TB.0 2 T.0&ar-./10 2 @@@@@.

This )nd signal indicates the )nd of the execution of an instruction, so this )nd signalcan &e used to start a new instruction fetch c!cle &! resetting the control step counter to

its starting alue.

The circuit diagram +partial- for generating ;in and )nd signal is shown in the diagram.


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The signal A7787", /1, /10 etc. are coming from instruction decoder circuits which

depends on the contents of I1.

The signal T#, T%, TD are coming out from step decoder which depends on control stepcounter.

The signal 0 +0egatie- is coming from condition code register.

Ehen wait for "*C +E"*C- signal is generated, then CPU does not do an! works and it

waits for an "*C signal from memor! unit. In this case, the desired effect is to dela! theinitiation of the next control step until the "*C signal is receied from the main memor!.

This can &e incorporated &! inhi&iting the adancement of the control step counter for the

required period.

et us assume that the control step counter is controlled &! a signal called 1U0.

/! looking at the control sequence of all the instructions the E"*C signal is generated

as<

E"*C = T% 2 T?.A778"7 2 @@@@@

The 1U0 signal is generated with the help of E"*C signed and "*C signal. The

arrangement is shown in the figure.


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The "*C signed is generated &! the main memor! where operation is independent ofCPU clock. $ence "*C is an as!nchronous signal that ma! archie at an! time relatie

to the CPU clock. It is possi&le to s!nchroniFed with CPU clock with the help of a 7 flip

flop.

Ehen E"*C signal is high, then 1U0 signal is low. This run signal is used with the

master clock pulse through an A07 gate. Ehen 1U0 is low, then the clock signalremains low, and it does not allow to progress the control step counter.

Ehen then "*C signal is receied, the run signal &ecomes high and the CG signal

&ecomes same with the "CG signal and due to which the control step counter progresses. Therefore, in the next control step, the E"*C signal goes low and control

unit operates normall! till the next memor! access signal is generated.

The timing diagram for an instruction fetch operation is shown in the figure.

Timing of control signals during instruction fetch.

In this discussion we hae presented a simplified iew the wa! in which the sequence ofcontrol signals needed to fetch and execute instructions ma! &e generated.

It is o&sered from the discussion that as the num&er of instruction increase the num&erof required control signals are also increased. Therefore the complexit! of the encoder

circuit will also increase.


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In HSI technolog!, structure that inole regular interconnection patterns much easier to

implement than the random connections.

ne such regular structure is PA +programma&le logic arra!-. PAs are nothing &ut the

arra!s of A07 gates followed &! arra! of 1 gates. If the control signals are expressed

as sum of product form, then with the help of PA it can &e implemented. The PAimplementation of sequence controller is shown in the figure.

design of control unit_old

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