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DESIGN OF LOW VOLTAGE CMOS TRISTATE BUFFER
Nurul Huda binti Zulkifli
Bachelor of Engineering with Honours
(Electronic and Telecommunication Engineering)
2010
UNIVERSITI MALAYSIA SARAWAK
R13a
BORANG PENGESAHAN STATUS TESIS
Judul: DESIGN OF LOW VOLTAGE CMOS TRISTATE BUFFER
SESI PENGAJIAN: 2009/2010
Saya NURUL HUDA BINTI ZULKIFLI
(HURUF BESAR)
mengaku membenarkan tesis * ini disimpan di Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak
dengan syarat-syarat kegunaan seperti berikut:
1. Tesis adalah hakmilik Universiti Malaysia Sarawak.
2. Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dibenarkan membuat salinan untuk
tujuan pengajian sahaja.
3. Membuat pendigitan untuk membangunkan Pangkalan Data Kandungan Tempatan.
4. Pusat Khidmat Maklumat Akademik, Universiti Malaysia Sarawak dibenarkan membuat salinan tesis ini
sebagai bahan pertukaran antara institusi pengajian tinggi.
5. ** Sila tandakan ( ) di kotak yang berkenaan
SULIT (Mengandungi maklumat yang berdarjah keselamatan atau kepentingan
Malaysia seperti yang termaktub di dalam AKTA RAHSIA RASMI 1972).
TERHAD (Mengandungi maklumat TERHAD yang telah ditentukan oleh organisasi/
badan di mana penyelidikan dijalankan).
TIDAK TERHAD
Disahkan oleh
(TANDATANGAN PENULIS) (TANDATANGAN PENYELIA)
Alamat tetap: KAMPUNG TERSUSUN AIR
KUNING,
31800 TANJONG TUALANG, MDM. SHARIFAH MASNIAH WAN
MASRA
Nama Penyelia
PERAK.
Tarikh: Tarikh:
CATATAN * Tesis dimaksudkan sebagai tesis bagi Ijazah Doktor Falsafah, Sarjana dan Sarjana Muda.
** Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak berkuasa/organisasi
berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini perlu dikelaskan sebagai
SULIT dan TERHAD.
This Final Year Project attached here:
Title : Design of Low Voltage CMOS Tristate Buffer
Student Name : Nurul Huda binti Zulkifli
Matric No : 17052
has been read and approved by:
_________________________ _________________
Mdm. Sharifah Masniah Wan Masra Date
(Supervisor)
DESIGN OF LOW VOLTAGE CMOS TRISTATE BUFFER
NURUL HUDA BINTI ZULKIFLI
This project is submitted in partial fulfillment of
The requirements for the degree of Bachelor of Engineering with Honours
(Electronics and Telecommunication Engineering)
Faculty of Engineering
UNIVERSITI MALAYSIA SARAWAK
2009/2010
ii
Dedicated to my beloved family and friends.
iii
ACKNOWLEDGEMENT
First and foremost, I would like to express my utmost gratitude to God for
His abundant blessings and for the idea for me to successfully accomplished this
Final Year Project. Secondly, I am very grateful to my patience supervisor, Mdm.
Sharifah Masniah Wan Masra for all the idea and guidance without which this study
would have been very difficult to complete. Also for Mdm. Maimun Huja Hussain
and Dr. Bakri Madon for helping me with Pspice software and circuit design. Next, I
would fell indebted to my dearest friends for their moral and material supports. Last
but not least, I would like to thank my beloved parents Encik Zulkifli bin Haji
Zakaria and Puan Noraisah binti Mohd Isa that always have trust in me. Also for my
treasured sisters and brothers who are always be my source of motivation.
iv
ABSTRAK
CMOS tristate buffer banyak digunakan dalam sistem elektronik. Dengan
meningkatnya pengggunaannya, juga menuntut bahawa buffer yang beroperasi di
kelajuan tinggi. Jadi kelajuan tinggi CMOS tristate buffer direkabentuk. Sistem
kelajuan tinggi adalah mudah untuk dilaksanakan, tetapi untuk kelajuan tinggi
dengan sistem voltan rendah yang sukar dicapai. Kerana voltan yang digunakan
adalah rendah, kuasa yang digunakan juga akan menjadi rendah. Tujuan projek ini
adalah untuk merekabentuk suatu tristate buffer voltan rendah yang boleh
menggerakkan beban kapasitif lebih besar. Masalah yang timbul adalah bagaimana
untuk mengawal throughput kerana dalam kebanyakan kes jika voltan sistem
diturunkan, kelajuan sistem akan menurun juga. Dengan melakukan pensaizan
transistor terhadap litar kelajuan tinggi itu, voltan bekalan yang digunakan dalam
litar ini diturunkan dari voltan bekalan litar kelajuan tinggi. Nilai optimum yang
dipilih untuk voltan bekalan adalah 1.6 V sementara nilai yang dipilih untuk beban
kapasitif adalah 10 pF. Disebabkan nilai voltan yang digunakan semakin rendah,
pada masa yang sama didapati PDP dan EDP juga menurun, sementara kelajuan
tinggi dikekalkan.
v
ABSTRACT
CMOS tristate buffer are widely used in electronic systems. As the increasing
of its usage, it is also demanding that the buffer is operating in high speed. So the
high speed CMOS tristate buffer is designed. High speed systems are easy to be
implemented, but for a high speed with low voltage system are difficult to achieve.
As the voltage used is low, the power consumption will be also low. The objective of
this project is to design a low voltage tristate buffer that can drive a larger capacitive
load. The problem is how to maintain the throughput while in most cases, lowering
voltage of the system will lowering the system speed too. By applying transistor
sizing to the high speed circuit, the supply voltage used in this circuit is lowered
from the high speed design. The chosen optimum value used for supply voltage is
1.6 V while chosen value for capacitive load is 10 pF. As the value of the supply
voltage is getting lower, it is shown at the same time that the Power Delay Product
and Energy Delay Product also decreasing while maintained the high speed.
vi
TABLE OF CONTENTS
CONTENT Pages
DEDICATION ii
ACKNOWLEDGEMENT iii
ABSTRAK iv
ABSTRACT v
TABLE OF CONTENTS vi
LIST OF TABLES ix
LIST OF FIGURES x
ABBREVIATIONS xii
Chapter 1 INTRODUCTION
1.1 Introduction 1
1.2 Problem Statement 3
1.3 Project Objectives 5
1.4 Project Scope 6
1.5 Report Structures 6
Chapter 2 LITERATURE REVIEW
2.1 Basic Concept of CMOS 8
2.2 Inverter 10
2.2.1 Area and Complexity 10
2.2.2 Functionality and Robustness 10
2.2.3 Noise Margins 11
vii
2.2.4 Ideal Digital Gate 12
2.2.5 Performance 13
2.2.6 Power and Energy
Consumption
15
2.3 CMOS Inverter 16
2.4 Buffer 18
2.5 Tristate Buffer 20
2.5.1 Uses of Tristate Buffer 22
2.6 CMOS Tristate Buffer 23
2.7 CMOS Power Consumption 25
2.7.1 Capacitive voltage transitions
2.7.2 Short-Circuit Component of
Power
25
28
2.7.3 Leakage Component of Power 29
2.7.4 Technology Optimization 30
2.8 Charge Pump 33
Chapter 3 METHODOLOGY
3.1 Introduction 34
3.2 Design Flow 35
3.3 Pspice Software 37
3.4 Conventional CMOS Tristate Buffer 39
3.5 High Speed CMOS Tristate Buffer 40
3.6 Proposed CMOS Tristate Buffer 42
3.7 The W/L Values 43
viii
3.8 Transistor Sizing 45
Chapter 4 RESULTS AND DISCUSSIONS
4.1 Introduction 49
4.2 During pull down (En=1, Vin= High to
Low)
50
4.3 During pull up (En=1, Vin= Low to High) 55
4.4 Short Circuit Current 59
4.5 Power Delay Product 61
4.6 Energy Delay Product 62
4.7 Discussion 64
Chapter 5 CONCLUSIONS AND
RECOMMENDATIONS
5.1 Conclusions 67
5.2 Recommendations 68
5.3 Problems Encountered 68
5.4 Conclusion 69
REFERENCES 70
APPENDICES
APPENDIX A 73
APPENDIX B 74
ix
LIST OF TABLES
TABLES PAGES
2.1 Enable Tristate Buffer 23
x
LIST OF FIGURES
FIGURES PAGES
2.1 Cascaded inverter gates: definition of noise margins 12
2.2 Ideal digital gate 13
2.3 The propagation delay from waveform circuit 14
2.4 Static CMOS inverter 17
2.5 Transistor Symbols 17
2.6 Inverter and buffer 18
2.7 Definition of fan-out and fan-in of a digital gate 19
2.8 Tristate buffer with active high and low control 20
2.9 Tristate buffer as a switch 22
2.10 General CMOS Tristate Buffer Circuit 23
2.11 Normalized delay vs. Vdd for a typical gate in a standard
CMOS process
30
2.12 Effect of threshold reduction on the delay for various supply
voltages
32
2.13 Compromise between dynamic and leakage power dissipation
through Vt variation
32
3.1 Tristate Buffer Design Process Flow 35
xi
3.2 Conventional CMOS Tristate Buffer Circuit 39
3.3 High Speed CMOS Tristate Buffer Circuit 40
3.4 Proposed CMOS Tristate Buffer Circuit 41
3.5 Circuit model for analyzing the effect of transistor sizing 45
3.6 Plot of Energy vs. Transistor Sizing factor for various
parasitic contributions
47
4.1 Inputs and output of conventional design during pull down 50
4.2 Output of high speed design during pull down 50
4.3 Output of proposed design during pull down 50
4.4 Inputs and output of conventional design during pull up 55
4.5 Output of high speed design during pull up 55
4.6 Output of proposed design during pull up 55
4.7 Conventional tristate buffer short circuit current through
NMOS transistor
59
4.8 High speed tristate buffer short circuit current through NMOS
transistor
60
4.9 Proposed tristate buffer short circuit current through NMOS
transistor
60
4.10 Graph of the propagation delays versus capacitive load 64
4.11 Graph of the propagation delays versus supply voltage 65
4.12 Graph of the Energy Delay Product versus supply voltage 65
4.13 Graph of the Energy Delay Product versus propagation delays 66
xii
ABBREVIATIONS
AC - Alternating current
ASIC - Application-Specific Integrated Circuit
BiCMOS - Bipolar Complementary Metal Oxide Semiconductor
BSIM - Berkeley Short-Channel IGFET Model
CMOS - Complementary Metal Oxide Semiconductor
COS-MOS - Complementary-Symmetry Metal-Oxide-Semiconductor
DC - Direct Current
EDP - Energy Delay Product
I/O - Input/Output
IC - Integrated Circuit
MOS - Metal Oxide Semiconductor
MOSFET - Metal Oxide Semiconductor Field Effect Transistor
NMOS - N-type Metal Oxide Semiconductor
PDP - Power Delay Product
PMOS - P-type Metal Oxide Semiconductor
TTL - Transistor-Transistor Logic
VLSI - Very Large Scale Integration
W/L - Width/Length
1
CHAPTER 1
INTRODUCTION
1.1 Introduction
Recently, all digital circuits are demanded to operate with low power
consumption as power dissipated by electronic circuit affect the portability and size
of electronic systems. The most important technology consideration in minimizing
power consumption for digital systems is the threshold voltage and its control which
allows the reduction of supply voltage without significant effect on logic speed.
Since CMOS circuits do not dissipate power if they are not switching, a
major focus of low power design is to reduce the switching activity to the minimal
level required to perform the computation. This can range from simply powering
down the complete circuit or portions of it, to more sophisticated schemes in which
2
the clocks are gated or optimized circuit architectures are used which minimize the
number of transitions [1].
An important attribute which can be used in circuit and architectural
optimization, is the correlation which can exist between values of a temporal
sequence of data, since switching should decrease if the data is slowly changing
(highly correlated) [1].
So for achieving this goal, the effect of sizing and supply voltage on the
circuit is extensively considered. The optimization to minimize area at all costs has
only been secondary to the fixation on increasing circuit speed, but this should be
examined with respect to its effect on power consumption. Energy Delay Product
(EDP) and Propagation Delay Product (PDP) have been the main objectives of this
research as it is compromise between the attempt to reduce the energy and time
consumption.
The tristate buffer are extensively used as a bus in digital systems such as
microprocessor, ASIC and memory. When one device is sending on the bus, another
sending device should be disconnected. This can be achieved by setting the output
buffers of those devices in high impedance state (Hi-Z) that effective disconnects the
gate from output wire. Such a buffer has three possible states that are 0, 1 and Hi-Z
therefore called tristate buffer. Owing to a bundle of wires connected to a bus, a
large capacitive load driving capability is one of the most importance properties of
tristate buffer [2].
3
CMOS is more attractive than BiCMOS in electronic system because of its
simplicity, low power consumption and optimization of purity in circuit compared to
BiCMOS circuit which utilizing CMOS and BJT in the same circuit [3]. For this
reason, a low voltage tristate buffer based on CMOS technology that can drive larger
capacitive load that is suitable for driving a data bus will be designed.
1.2 Problem Statement
Designs of high speed tristate buffer have been developed by some
researchers. However, only [1] have developed high speed and low voltage tristate
buffer using BiCMOS with large capacitive load driving capability. Recently
attention on BiCMOS circuit technology has increased because of their high speed
and driving capability over CMOS. However, electronic industry still chooses
CMOS over BiCMOS because BiCMOS process complexity that contributes to
higher cost and longer fabrication cycle time. Thus, a low voltage CMOS tristate
buffer that can drive larger capacitive load for driving a data bus will be designed.
Problems arise with building low voltage products to be compatible with
existing products that utilize a higher power supply potential.
One problem exists with the compatibility of conventional input/output (I/O)
buffers using CMOS low-voltage processing technology. If conventional output
buffers are used in CMOS products operating with a low voltage supply, then current
leakage problems may arise when higher voltages are driven into the output pad
4
while the buffer is in a tristate mode. Obviously, current leakage problems are
undesirable in an integrated circuit, especially in cases where the magnitude of the
leakage violates accepted I/O bus standards [4].
Other problems also exist when tristateable output buffers operating from a
low voltage supply are connected to a higher voltage bus. In addition to the leakage
problem, there are two long-term reliability issues to consider. These problems are
commonly referred to as “hot electron reliability” and “p-device stability” [4].
Hot electron reliability denotes the phenomenon wherein the operating
performance of a transistor degrades due to a build up of trapped carriers in the gate
oxide region. Because electron carriers have a higher mobility than hole carriers, this
problem is more pronounced for n-channel devices as compared to p-channel devices
[4].
The performance of a transistor degrades as the electric field of the trapped
carriers interact with the electric field applied at the gate of the transistor. Hot
electron reliability is a probabilistic model where the probability of a carrier being
trapped in the oxide is a function of the energy of the carrier as it passes through the
channel of the transistor. At the operating point of saturation devices have the
highest probability of injecting carriers into the gate oxide. Among the factors that
determine if a transistor will experience hot electron reliability problems include
frequency of switching, size of load, operating temperature, driving potential, device
channel length, device channel width, the rise/fall times of the signal on the gate, and
the expected lifetime of operation of the transistor in the field [4].
5
Another long-term reliability risk, referred to as p-device stability, involves
the undesirable shift in the threshold voltage when excessive electric fields have
been applied across the gate oxide of a p-channel transistor. Note that n-channel
devices are also susceptible to a shift in their threshold voltage as a result of
excessive electric fields being experienced across their gate oxide. However, p-
channel devices are usually more sensitive to this phenomena [4].
Other problem is that, how to design a low voltage supply without degrade
the performance because it is extensively known that the speed degradation at low
supply voltage is the major limitation factor of both CMOS and BiCMOS in
submicron technologies [2].
1.3 Project Objectives
In this project, the following goals will be achieved:
1. To design and simulate using Pspice a low voltage tristate buffer that can
drive larger capacitive load.
2. To obtain lower EDP than previous researchers’ EDP.
3. To find the optimized tradeoff value between voltage and speed of CMOS
tristate buffer.
6
1.4 Project Scope
This project is a research on how to design a low voltage CMOS tristate
buffer while maintained or improved speed of the previous proposed design. The
new proposed design will improve recent driving capability where wasted power can
be reduced.
1.5 Report Structures
This report details overall process in developing the project starting from the
early idea of development, circuit development planning, software simulation until
report writing. This report is divided into five chapters including introduction;
literature review; methodology; results and discussion; and conclusion and
recommendation. The brief information of each chapter is described as below:
Chapter 1 provides background information, problem statement and
objectives of the project. It also provides scope of the project, project planning and
project structures.
Chapter 2 summarizes and reviews onto the overall studies and researches
work. Preliminary literature search included existing issues such as design of high
speed and low voltage tristate buffer using BiCMOS and minimizing power
consumption in digital electronic circuit are explained in detail.
7
Chapter 3 discusses the methodology and focuses on the use of Pspice
simulator to obtain the result to be achieved. The first part of this chapter
concentrates about the circuit development methodology. The second part shows the
proposed design circuit as well as the circuits of conventional design and high speed
design to be compared. The descriptions of the circuits are also have been discussed.
Chapter 4 exhibits the results and data obtained from the Pspice simulation. It
carries out analysis and discussion onto the data. It also examines whether the
simulation results fulfil the predicted or expected results as mentioned in the early
part of the project. Besides, different approaches and testing taken out to examine the
project in achieving its objectives are listed in details.
Chapter 5 summarizes the overall finding of the project. The problems faced
throughout the project are discussed too. In addition, further investigation which can
be implemented or future improvement of the project is being discussed.
Appendices and references are also included at the end of the report.
8
CHAPTER 2
LITERATURE REVIEW
2.1 Basic Concept of CMOS
Complementary metal-oxide-semiconductor (CMOS) is a technology for
making integrated circuits. CMOS technology is used in microprocessors,
microcontrollers, static RAM, and other digital logic circuits. CMOS technology is
also used for a wide variety of analog circuits such as image sensors, data converters,
and highly integrated transceivers for many types of communication. Frank Wanlass
successfully patented CMOS in 1967 (US Patent 3,356,858) [4].
CMOS is also sometimes referred to as complementary-symmetry metal-
oxide-semiconductor (or COS-MOS). The words “complementary-symmetry” refer
to the fact that the typical digital design style with CMOS uses complementary and
9
symmetrical pairs of p-type and n-type metal oxide semiconductor field effect
transistors (MOSFETs) for logic functions [4].
Two important characteristics of CMOS devices are high noise immunity and
low static power dissipation. CMOS dissipates power only when the transistors in
the CMOS device are switching between ON and OFF states. This shows that
CMOS devices do not produce as much waste heat as other logic devices such as
transistor-transistor logic (TTL) and NMOS logic, which uses all n-channel devices
without p-channel devices [4].
Other than that, CMOS is better than bipolar junction transistor (BJT) in the
aspect of power dissipation, noise margin, packing density, a good switch and also
the ability to integrate large and complex circuits and functions with high yield. This
is the reason why CMOS become the most used technology to be implemented in
VLSI chips [3].
From all of the reasons above, we can see why CMOS is preferred to be used
in most digital logic circuits rather than other logic circuits. Even though BiCMOS
become technology choice recently, CMOS still become electronic market choice.
Inverter and tristate buffer will be explained in the following section.