design of on-chip switched capacitor converters - indico · design of on-chip switched capacitor...

Design of on-chip switched capacitor converters

M. Bochenek, W. Dabrowski, F. Faccio, J. Kaplon, S. Michelis

This research project has been supported by a Marie Curie Initial Training Network Fellowship of the European Community’s & Seventh Framework Programme under contract number (PITN-GA-2008-211801-ACEOLE)

Outline

ATLAS–CMS Power Working Group 31 March 2010

● Overview of step-down converters,

● Switched capacitor step-down converter proposed for the serial and the DC-DC powering scheme,

● Results from the Cadence simulations,

● Overview of step-up charge pumps,

● Switched capacitor voltage doubler proposed for the serial powering scheme,

● Results from the Cadence simulations.

Switched capacitor step-down converter


Simple switched capacitor DC-DC step-down converter

● Four switches● Two capacitors

The simplest model for the 2:1 converter contains:


Phase 1:● Switches S1 and S3 are closed,● Switches S2 and S4 are opened,● CX and CL are connected in series.

Phase 2:● Switches S1 and S3 are opened,● Switches S2 and S4 are closed,● CX and CL are connected in parallel.

Simple step-down converter


Practical solution for the DC-DC step-down converter

Power efficiency = 97%


● VDD = 1.9 V● VOUT = 926 mV● IOUT = 60 mA● CX = 1000 nF● CL = 200 nF● f = 500 kHz

Schematic diagram of the non-overlapping clock generator used

in the step-down converter

2 x NOR gate3 x inverter2 x current starved

inverter

C1 = C2 = 20fF


Schematic diagram of the buffer used in the step-down converter


M4 M3 M1M2

570μ570μmm

200μ

200μ

mm

M4 buffer M3 buffer M2 bufferNon-overlappingclock generator M1 buffer

Layout of the step-down DC-DC converter


Time response of the converter


20 mV20 mV

Power efficiency and output voltage versus output current


Results from the corner analysis for the step-down converter


Switched capacitor step-up converter


Overview of the simplest voltage doubler

The simplest model contains:

● Three switches● One capacitor


Simple voltage doubler

Phase 1:● Switches S1 and S3 are closed,● Switch S2 is opened,● Capacitor is charged to the supply voltage VDD

Phase 2:● Switches S1 and S3 are opened,● Switch S2 is closed,● Bottom plate of the capacitor on VDD, while the capacitor maintains its charge VDDC (from the previous phase).


Solution for the voltage doubler pumping on both clock edges

● M1 and M2 use thin (2.2nm) gate oxide,● M3 - M6 use thick (5.2nm) gate oxide,● VIN = 0.9V, CPUMP = 470nF, CHOLD = 470nF, CPOL = 10pF.

● VDD = 0.9 V● VOUT = 1.59 V● IOUT = 30 mA● CPUMP = 470 nF● CHOLD = 470 nF● f = 1 MHz

= 85% Power efficiency


Practical solution for the level shifter


430μ430μmm

265μ

265μ

mmLayout of the step-up DC-DC converter


Time response of the converter


15 mV 15 mV

Power efficiency and output voltage versus output current


Results from the corner analysis for the step-up converter


Conclusions:


● The results from the simulations are promising:97 % for the step-down converter,85 % for the step-up converter,

● The core layouts of both designs are (almost) ready,

● The final assembly of the chip still has to be done,

● We are going to submit the chip in the IBM 130nm technology in May 2010.

Thank you for your attention!

design of on-chip switched capacitor converters - indico · design of on-chip switched capacitor...

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