design of pvt tolerant bandgap reference circuit for low noise and low current

University of Southampton

School of Electronics and Computer Science

Design of PVT Tolerant Bandgap Reference Circuit for

Low Noise and Low Current By

Manraj Singh Gujral msg1g10

22nd September, 2011

Project supervisor: Dr. Peter R Wilson Second Examiner: Dr. Koushik Maharatna

A project report submitted for the award of Master of Science in System‐on‐Chip

Manraj Singh Gujral msg1g10 University of Southampton 2

AbstractWith each new process technology, essentially driven by digital electronics, the transistor

sizes are being shrunk to their limits so that they can be packed in millions in a small silicon

area. This increases the complexity for analogue circuits which are required to produce an

accurate output despite increased performance‐degrading parameters, over a range of

conditions like temperature, voltage fluctuation and process errors. Therefore, with every

leap in process technology, more and more intelligent ways of implementing the analogue

and mixed signal circuits are being sought after.

This project deals with the design of one the most common blocks used in almost all system‐

on‐chip designs, a Bandgap Reference circuit. A reference signal or a voltage source which is

the first signal generated on a chip that and then can be used for biasing, generating other

signals across the chip etc. The design focuses on the Noise performance and its effect on the

other systems connected to it. A detailed step‐by‐step approach is presented in this report

towards an ultra low noise performance. The Bandgap is tested for worst case industrial

Corners, is laid out, extracted and finally verified with Schematic vs. Extracted checks.

AcknowledgmentsI would like to thank Dr Peter Wilson, my supervisor, for encouraging me to take on this

project.

Also, I would thank Dr Ke Li for offering me his time and assistance whenever I got stuck.

Special thanks to Mr. Ajaib Hussain, UK Engineering Manager, Rakon UK Ltd., for providing

me a chance to work on this project in Rakon with industrially acceptable specifications and

performance criteria.

I would also like to thank the Design Team in Rakon UK Ltd., Mr. Kevin Aylward (Principal IC

Designer), Mr. Karl Ward (Principal Design Engineer), Mr. Ravi Ramakrishna (Sr. IC Design

Engineer) , Mr. Robbie Robinson (Sr. Layout Engineer) & Mr. Mark Broad (Sr. Layout

Engineer) for their constant feedback and support throughout this project.


TableofContentsAbstract ...................................................................................................................................... 2

Acknowledgments ...................................................................................................................... 2

Chapter 1: Introduction ............................................................................................................. 4

1.1 Thesis Structure ............................................................................................................... 4

1.2 Bandgap Principle ............................................................................................................ 5

1.3 Temperature Coefficients ................................................................................................ 8

1.4 Negative Temperature Coefficient .................................................................................. 8

1.5 Positive Temperature Coefficient .................................................................................. 10

1.6 Temperature Independence .......................................................................................... 11

Chapter 2: Basic Building Blocks .............................................................................................. 15

2.1 Basic Amplifier ............................................................................................................... 15

2.2 Current Mirror ................................................................................................................ 17

2.3 Startup Circuits ............................................................................................................... 19

Chapter 3: Bandgap Models .................................................................................................... 21

3.1 Bandgap‐1 ...................................................................................................................... 21

3.2 Bandgap‐2 ...................................................................................................................... 23

3.3 Bandgap‐3 ...................................................................................................................... 25

Chapter 4: Corner Simulations for Bandgap ‐3 ........................................................................ 30

Chapter 5: Layout & Extraction ................................................................................................ 35

5.1 Theory ............................................................................................................................ 35

5.2 Extraction ....................................................................................................................... 40

5.3 Current Sources for the Output Stage ........................................................................... 42

Chapter 6: Schematic vs. Extracted Bandgap Simulations (with university corners) .............. 48

Chapter 7: Summary ................................................................................................................ 52

Specification Compliance Matrix ......................................................................................... 52

Chapter 8: Noise Analysis ........................................................................................................ 53

8.1 LDO Phase Noise ............................................................................................................ 57

8.2 Control Supply Phase Noise ........................................................................................... 60

8.3 Experiment ‐1: Low Pass Filter ....................................................................................... 62

8.4 LDO and Control Supply Phase Noise Regions ............................................................... 63

Chapter 9: Conclusion .............................................................................................................. 65

9.1 Scope of Improvement .................................................................................................. 65

References ............................................................................................................................... 66


Chapter1:Introduction

All circuits and systems incorporate a reference signal which sets the foundation of all other

signals to be generated from it. Since these references are responsible for generating all the

biasing in a given chip it is very important these sources are independent of parameters like

the variations in supply voltage, temperature fluctuations and process variations. One of the

common techniques used is to have a Bandgap reference. As a starting guideline, a set of

specification is provided is shown in the table 1 below

Table 1 : Bandgap Specifications

Specification

Parameter Min Nom Max Units

Power supply, Vcc 1.7 1.8 1.9 V

Temperature ‐40 27 85 °C

BGR o/p, Vref const. V

BGR o/p Accuracy ‐30m +30m V

BGR o/p Ref Currents

10µ A

20µ A

40µ A

100µ A

Output Impedance (for 10µA o/p ) 1M Ω

PSRR ‐40 dB

Noise (at 10kHz) 100 nV/√(Hz)

Quiescent Current, Idd ( BGR) 100µ A

Before we understand what these numbers mean we will first look at the basic principles of

a “Band Gap” and how it can be used to generate our reference. These are explained from

section 1.2

1.1ThesisStructureChapter 1 provides the introduction to Bandgap. It discusses the basic principles and origins

of temperature coefficients and how it can be used to make a Bandgap Reference voltage

source.

Chapter 2 marks the beginning of a design strategy exploring common building blocks that

we could play around with in an analogue circuit. The properties of these building blocks are

seen in detail and how they can be modified to suit specific needs.


Chapter 3 The bandgap models are then developed in this chapter. Each model is checked

and simulated to see if it can be improved any further. Finally the chosen model is simulated

for worst case corners in Chapter4.

Chapter 5 & 6 deal with the Layout and extraction of the selected bandgap schematic. A

detailed Layout‐flow discussion is carried out in this section. After layout, DRC checks and

LVS the circuit is then extracted and a Schematic vs. Extracted bandgap simulation is

performed. A summary of all the results are presented in Chapter 7.

To understand Noise and its effects on the system we then run simulations on a test circuit

provided by Rakon, in Chapter 8. This test circuit is an actual piece of circuitry used in Rakon

systems. The noise profiles are therefore actual values seen in their systems and several

tests are conducted to see how it is distributed across the system.

Finally Chapter 9 concludes the findings and presents further scope of improvements

1.2BandgapPrincipleBandgap references are derived directly from the silicon, i.e., the potential between the

Valance Band and the Conduction band of the Silicon. Hence they are the only true bandgap

references. The current references are derived from these absolute voltages.(1)

Figure 1: A simplified band diagram of a semiconductor.

An almost empty conduction band represents the electrons which have moved to a higher

energy level and can now conduct. The difference in the Energy in the electrons in the

Conduction band over the Valance Band (non conducting band) is seen as the Bandgap

energy. Valence band edge is shown as Ev (not electron volts). Conduction Band Edge is

shown as Ec. The energy of an electron outside the crystal is E (vacuum)


Figure 2: Energy Bands for Metals, insulators and Semiconductor

This bandgap energy tends to decrease with the temperature because of the increased

inter‐atomic spacing due to the thermal vibrations. The increase in spacing reduces the

potential seen by the electrons and therefore the relative gap between the energy bands is

also reduced.(2) . That’s why we see a CTAT voltage as shown in figure 3.

The experimental expression for the dependence between the Energy bandgap and

temperature is found out to be

0

Equation 1(2)

Where α and β are called the fitting parameters and Eg (0) is the Energy at 0 K. The fitting

values are listed below for Germanium, Silicon and Gallium Arsenide in Table 2

Table 2: Table for fitting parameters for calculating the Energy Bandgaps.(2)

Germanium Silicon GaAs

Eg(0) (eV) 0.7437 1.166 1.519

α (me V/K) 0.477 0.473 0.541

β (K) 235 636 204

And therefore if we run a temperature sweep on these materials we would get a result as

shown in Figure 3


Figure 3: Temperature and Bandgap energy relationship (2)

How we make a CTAT voltage source into a temperature independednt voltage source will

be discussed in the next chapter.

From a circuit point of view, a reference voltage set all the other baising voltages in the

entire circuit. For example a reference voltage can be used in a Voltage regulator using a

feed back loop with a resistor ratio.

Figure 4: Vref used in a voltage regulator

Similarily a Current reference can also be generated from a Bandgap voltage

Figure 5: Vref used in a Current source (1)

In this case a reference voltage is converted to a current through a resistor and and opamp.

As a result it is possible to generate further references if we have a VREF that stays true to its

name, i.e., stable over an entire range of temperature.

00.20.40.60.8

11.21.41.6

0 500 1000 1500

En

ergy

Ban

dga

p (

eV)

Temperature (K)

GaAs

Si

Ge


1.3TemperatureCoefficientsMany circuit related parameters and processes vary with temperature. It is therefore

interesting to see how the temperature independence is achieved. It is suggested if two

equal quantities of opposite temperature coefficients are added then the net result is nil. ,

i.e., the result could have a zero (near zero) temperature coefficient.

Concept being, if we have two voltages , V1 and V2 and they vary with temperature

opposite to each other , then we have a start. We can choose a multiplying factor (or a

scaling factor), α1 and α2, such that the rate of change of these voltages can be equated to

give a net result of something like

1 1 2 2

(3)

Such that

1 2 0

I.e.

1 2

Equation 2

Therefore we need to look for two such sources where, similar to equation 2, the

temperature coefficients are opposite (and scaled) equal to one another.

1.4NegativeTemperatureCoefficientA diode connected transistor has a current‐voltage relation quite accurately given by an

exponential. Usually, in a Pure CMOS process, forward biased diodes are avoided and the

designer might have to ask for special request from the fabrication house if he/she intends

to use it. Unless specially made, diodes tend to pollute the substrate with forward biased

currents and many‐a‐times the model supplier will limit the forward biasing currents to a

maximum level with warnings (4). Therefore, if the same operation is achieved by a

transistor connected diode then it is advised to use it instead of an actual diode.

Figure 6: Diode connected transistor.(3)

where, ⁄

IS : saturation current ∝ µkTn2 . µ: mobility of the minority Charge

carriers.

n: majority charge carrier concentration

k: Boltzmann const.

and kT/q is also represented as VT, early voltage


If we take this current equation and re‐write it in the form of VBE, we get

ln , or ln

Equation 3

Taking the derivative of equation 3 we find,

ln

Equation 4

Equation 4 can be further proved to have a negative temperature coefficient or has a

Complementary To Absolute Temperature (CTAT) slope, by subsequent derivation, so we

perform a simple test in Cadence if this can be proved true.

In the circuit schematic shown in figure 7(a), an IBM 180nm BiCMOS library npnx bipolar

device is used which is connected in the form of a diode. The current source (I3) is supplying

25µA with a power supply of 1.2 V. This circuit is then tested over a temperature range of ‐

45°C to +125°C. Figure 7 (b) shows the VBE voltage across the pn junction through this

temperature range.

(a) (b)

Figure 7 : (a) Diode connected Transistor circuit, (b) Its VBE vs. T characteristic

As can be seen by the figure 7 (a) & (b), the slope of the VBE, i.e., the Temperature

coefficient is negative. The precise value can be seen from the graph to be

1.34mV/°C.

Equation 5

This seems to give us a fairly constant negative temperature coefficient slope over the

entire range of our operation. Although this looks like a linear slope, if this were plotted

over a long temperature it would appear to follow a second order slope, similar to a

parabola, but that is a second degree effect and for the purpose of this exercise we can

treat it as a linear slope.


Interestingly, even though the voltage across the diode connected transistors is CTAT, the

current through it is a Proportional to absolute Temperature or PTAT. This could be further

discussed and analyzed. This is an interesting concept which can be looked into and is not

quite apparent or discussed in many books.

1.5PositiveTemperatureCoefficientIt was found that if the two diode connected transistors are made to operate under

different current densities, then the difference in their base emitter voltage is a PTAT

voltage.(3)

VDD

nI I

∆Vbe

+ ‐

Q1 Q2

1 : r

Figure 8 : PTAT Voltage generation

Likewise, a small test circuit is made similar to figure 8 with I = 25µA, n = 10 and Transistor

size Q2/Q1 = 1, i.e., r = 1. Based on the Equations presented in figure 8, we can expect,

ln 0.087 10 ln 10 1 . / Equation 6

A temperature sweep test is carried out to check for validity of the PTAT voltage source.

(a) (b)

Figure 9 : (a) Diode connected Transistors circuit, (b) Its ΔVBE vs. T characteristic

In figure 9 a Positive temperature coefficient can be seen between ∆VBE and Temp with

coefficient value being 0.206 mV/°C, which matches our estimation in Equation 6.

∆

ln ln

ln

ln

Therefore,


From the two analysis of Positive and Negative temperature coefficients it can be seen that

both types are indeed possible. Therefore Equation 2 (page 8) seems possible and can be

implemented with correct magnitudes of the multiplying factor α1 and α2.

1.6TemperatureIndependenceWe can now come to a conclusion that there are two types of Temperature coefficient’s we

can play around with. If we can find a way to add these two voltages, theoretically, we can

obtain a temperature independent output.

There are a number of ways in which this can be implemented and a lot of papers have been

presented on this subject over the years. Therefore, let’s start with the basic concepts and

build on it further

Consider a circuit, as presented by Willy M.C .Sansen(1)

Figure 10 : a PTAT voltage circuit generation

In this case assuming the currents in the two arms are the same, i.e., n = 1, but the

Transistor Sizes are different Q2/Q1 = r, we can derive our PTAT equation as

So, ∆

Since V V lnII

Therefore

∆ V lnII

V lnII

Hence , ∆ V ln

II

V ln r

Equation 7

where r is the Ratio of the Transistor size.

Taking the differential with respect to temperature we can see our PTAT equation as


ln

Equation 8

Now on one arm we have a CTAT voltage, which is the VBE and on the other arm we have a

PTAT which is the ΔVBE, if we add them together we can very easily get a Temperature

independent voltage.

Similar to the circuit shown in figure 10, we employ a current mirror, Q3‐Q4, to make sure

the currents in both the arms are the same. Moreover, we can add a ratio in that current

mirror and therefore vary the current in the second arm depending on the scaling required

to maintain an equal and opposite PTAT and CTAT slope.

Q1Q2

1 : r

R1 ∆Vbe

+

-

Q4 Q3

n : 1

R2Vr2+

-

Vref

+

-

Figure 11 : Basic Bandgap

Since the currents are now n times each other the ΔVBE, in equation 6, becomes

∆ lnn

ln

∆ ln nr Equation 9

Therefore the Current, Ic, in the arm is set by the resister, R1 as

∆ Equation 10

This is then mapped on to the second arm by the current mirror with a ratio of n. Hence the

voltage across the resistor, R2 is given by

V

∆ Equation 11

This is nothing but a PTAT voltage scaled by a factor of: n.R2/R1.

i.e., the reference voltage now, shown as VREF becomes

VEquation 12


So here, we have a PTAT and a CTAT voltage adding to give a reference voltage. Let’s put

this theory into practise and build a small circuit that should prove the above concepts.

We select the Transistor size as 1:4, the current mirror as 10:1 and R1 as 50kΩ.

First, our ΔVBE value, (Equation 9) becomes

∆ ln nr 0.026 ln 10 4

∆ 95mV Equation 13

Therefore, Ic (Equation 9) is given as

∆ 0.095

50 10

2μA Equation 14

Figure 12 : Basic Bandgap schematic

We mirror this current, to 20µA and pass it through the resistance R2. R2 is assigned as

20kΩ therefore the PTAT voltage generated on the resistance R2 is

V n.2

1ΔVbe 2μ 20k

V 0.4V Equation 15


In figure13, we can look at the expected values of Voltages and currents. The currents are

shown in dotted lines with legends printed alongside.

Figure 13 : Basic Bandgap output wave

Here, among the criss‐cross of waveforms in figure 13, we can see the Actual temperature

insensitive voltage (labelled Vref) being generated. On closer inspection we see that it is still

drooping at lower temperature. This means we have to adjust the slopes of PTAT and CTAT

so that they exactly match each other in opposite direction.

n. ΔVbe : PTAT Voltage

Vbe , CTAT

Vref: Temperature Independent Voltage

Ic2

Ic1

ΔVbe


Chapter2:BasicBuildingBlocks

Before we begin to construct the bandgap circuit, let’s look at a few important building

blocks which are widely used in analogue and mixed signal design. These will also be used in

our bandgap circuit.

2.1BasicAmplifier

(a) (b)

Figure 14 : (a) Basic Amplifier circuit (b) IDS vs. VDS curve with varying VGS

For Linear Region, where VDS < VGS + VT, the Schichman‐Hodges Drain current equation is given

by

2

2

Equation 16

For Saturation Region, where VDS > VGS + VT,

2

1 Equation 17

The term 1 represents the channel length modulation.

µCOX and n are the Process parameter for the Oxide layer and the sub threshold slope resp.

W/L is the width over length of the channel

VGS, VDS, VT specify the Gate‐Source Voltage, the Drain‐Source Voltage and the Threshold

voltage for the MOS resp.

Equation 16 and 17 gives us the basics to perform hand calculations. Further accuracy can be

gained if we include other effects such as the body effect, the vertical field mobility

degradation etc.

Linear Saturation

VGS + VT = VDS

ΔIdsΔVds


MOS devices have a behaviour pattern with increasing current densities within their channel.

When a voltage is applied across the Gate‐Source terminal and is gradually increased the

characteristics of a MOS changes from Weak Inversion, where the drift current is very small

and the diffusion current dominates, to Strong Inversion, where the channel is now formed

w.r.t. to the voltage and finally to Velocity Saturation, when the electrons in the channel

reach the maximum speed. This analysis is critical since it gives us an idea about the

maximum transconductance or gm of a MOS device.(4)

(a) (b)

Figure 15 : MOS Characteristics (a) Various regions of Inversion (b) Rate of change of gm w.r.t VGS

During the point of velocity saturation the gm does not increase any further, but the current

increases linearly. Therefore, for analogue designers, this gives an idea of where the working

VGS of the MOS should be set. Usually it is assigned just below the velocity saturation point so

that any changes in the bias do not affect the current budget of the design.(1)

In analogue design it is advisable not to use the minimum possible channel length (L) as per the

technology. So It will be interesting to see how the gm of the transistor is affected by its W/L

parameters.

(a) (b)

Figure 16 : MOS Characteristics for gm vs. VGS (1)

Gm

becomes

constant in

velocity

saturation Weak

Inversio

Strong

Inversion

Velocity

Saturation

L>>Lmin

L= Lmin L>>Lmin

L= Lmin


(a) Varying L, keeping W/L constant (b) Varying only L, and keeping W constant

From figure 16 it can be seen that the Inversion points for Strong, Weak and Velocity saturation

can be manipulated by varying the parameters in W/L. This is an important concept when

designing a circuit in which MOS devices are supposed to turn on at either low voltages or high

voltages depending on the need

Although, enough parameters can be analyzed for a MOS used as an Amplifier with its small

signal analysis, gain analysis etc, we will revisit the amplifier in next chapter when considering

designs for Bandgap topologies.

2.2CurrentMirrorIn this topic we try and understand one of the critical building blocks in electronic design,

the Current mirrors. Current mirrors are widely used in both Analogue and digital domains.

They are very useful when copying a current source across an IC and deriving multiple

current references from just one ideal source.

From Equation 16 we know that the current equation of a MOS, in saturation, is given as

2

Equation 18

Neglecting short channel effects.

Where, µCOX is technology dependent parameter; n is the sub threshold slope.

VT is the threshold voltage.

Therefore, the current is a function of Voltage at Gate w.r.t Source (Base w.r.t emitter in

Bipolar) i.e., IDS = f (VGS).

This also means that, VGS = f‐1(IDS), which means, if a transistor is biased at IDS current it

generates a specific voltage VGS across it. Hence if this voltage, VGS, were to be applied at

the gate of another transistor with same function f, we can expect

IOUT = ff‐1(IDS) = IDS

Figure 17 : Diode connected transistor with inverse function, basic current mirror

As a result, we can get the same current at the output of another, identical MOS device.(3)


This concept can be further stretched to copying currents when W/L ratios are made

deliberately different. It is very simple in theory to perform current multiplication to just

about any number, but practically that is not the case.

Figure 18 : Current mirror concept extension to copying currents for reference

(a) Schematic description of Current copying (b) Possible Layouts of for the schematics

Current mirrors do give us the flexibility of generating our own current but an important

aspect to remember is that this device has to be physically made on a chip, like every other

part of the circuit. Therefore, from a layout perspective a ratio of 1:2, or 1:8 is practical

whereas a ratio of 1:7.3 or 1:100 might not be practical for matching. We will come across

this problem in the chapter 5 in Layout matching where we see how these impractical ratios

can give rise to various problems.

Since these current mirror are used for copying a reference current elsewhere in the circuit,

these current sources are required to have high output impedance so that they can drive

large loads irrespective of the voltage drop across it (as long as it’s in Saturation region).

We attempt a small experiment where we use a standard current source like the ones

discussed above and plot their output characteristics. Then we use the same circuit and

implement a cascade on top of it.

(a) (b)


Figure 19 : Current Mirrors (a) Simple current mirror (b) Cascoded current Mirror (Bias Set at 1V)

Figure 20 : Output characteristics of the two types of current mirror.

The output impedance of the circuit is shown in figure 19. We can observe per figure 20, we

can observe that the output impedance of the device can be increased by adding a cascode.

This is in line with the theory that output impedance of the circuit shown in figure 19 (a),

1

Equation 19

Is increased to,

Equation 20

Where gm2 is the transconductance of the bias transistor.

RDS1, RDS2 are the output resistance of the two output side MOS respectively.(4)

2.3StartupCircuitsAnother critical aspect in an IC design is the use of Start Up circuit. Most of the circuits have

two distinct stable points. One with zero current in the system and the other at a specific

desired bias point to which the system is actually designed. It is critical that no IC sent to

fabrication with a probability that it might not start. The start up circuits ensures that the

system reaches its desired operating point, always. Also, without startup circuits, softwares,

for example Spectre, might not simulate the system properly since it can always find a stable

solution at zero current. To stress on this point let us examine a test case shown in figure 21

Voltage

Cu

rren

t

Bipolar curve

Bipolar+ resistor curve

Stable point 1

Stable point 2

cascoded

Simple current


Figure 21 : An example of two stable operating points(5)

A bipolar device will have an exponential curve where as a Bipolar with a resistor in series

(or even a MOS device) will have a straight line characteristic (also shown in figure 15 (a)).

These two curves will therefore intersect at two distinct points, one at (0, 0) and other at a

specified current and voltage value.

Start‐up circuits are used to bring the system into active state by supplying an initial current

during power ON that aids a self sustaining current to be generated in the main system.

These circuits are so designed that after starting up, they isolate themselves from the main

system and do not play a part in its general functioning.

Figure 22 : Startup Circuit basic principles

There are a number of ways to devise a start up circuit and there is no hard‐and‐fast rule.

There are several factors for a designer to consider when making such a circuit, for example:

The start up circuit is required to either feed the current into the circuit, or drain the

current from the circuit (sink it). These are the two fundamental topologies.

When sourcing a current “into” the circuit the current should be fed into a part of

the main circuit that aids build‐up of other circuit currents, i.e., to have a positive

feedback in nature within the circuit. It is because of this positive feedback, we can

only provide a tiny amount of current that builds itself to the main circuit current.

A feedback, or a sense, can be feed the status of the system back to the start‐up

circuit, for example a voltage sense that can switch the start up circuit off.

The start‐up circuit in this exercise that I have used uses a resistor across which a voltage is

developed that pulls a PMOS transistor off. One of the drawbacks is that it is a trade‐off

between the size of the resistor and the area of the circuit. Since the specification included a

current budget, I have made the resistor value (and hence the area) high.


Chapter3:BandgapModels

There are a lot of papers on Bandgap designs dealing with low voltage, high PSRR, high

precision etc. There were several circuits attempted in order to reach the final circuit that

matched the specifications. These circuits are briefly discussed with their design strategies.

3.1Bandgap‐1In this design, a modular approach was taken where the bandgap circuit is comprised of the

diode connected transistor and ΔVBE, and an OpAmp to ensure that the voltage in the two

arms are the same. A Start‐up Circuit is not included at this point.

Figure 23 : a Typical Bandgap Approach.

Figure 24 : Output Voltage performance of the Bandgap‐1 Circuit. ΔVmax = 17mV (approx)


(a) (b)

Figure 25 : Output Performance.

(a) Output Noise performance 1Hz Noise = 210.87 µv/√Hz, 10kKhz Noise = 1Hz Noise = 2 µv/√Hz

(b) PSSR , ‐47 dB at 1 Hz and 10k Hz

Table 3: Performance table of Bandgaps, with Bandgap‐1

Output Accuracy, ΔVmax Noise (1Hz) Noise (10 kHz) PSRR

Specification 60mV NA 100nV/√Hz ‐ 47dB

BandGap‐1 17mV 210.87 µv/√Hz 2 µv/√Hz ‐ 40dB

This circuit has an output voltage performance ΔVmax = 19mV which is fairly good when

compared to our specifications (of +/‐ 30mV). The output Noise performance is just about in

the range with minimum PSSR of about ‐45dB compared to ‐40dB in the specification. The

Noise performance, however, is extremely poor at 1Hz and 10Hz Noise being 210.87 µv/√Hz

and 2 µv/√Hz resp. We would like to have noise levels in range of several nV/√Hz.

These high levels of Noise can be explained by looking at the Op‐Amp used in this circuit.

The circuit diagram of the 2‐Stage Op‐amp used in this circuit is shown below in figure 26

Figure 26 : A 2‐Stage Op‐Amp used in bandgap circuit.


Figure 27 : A 2‐Stage Op‐Amp Output characteristics. Phase Margin of 74° (approx)

This circuit contains many MOS devices. MOS is specially known for its bad 1/f Noise which

was seen in figure 25, output performance. Therefore, this leads us to a new circuit can be

implemented without MOS devices.

3.2Bandgap‐2A new Bandgap topology is shown in, figure 28. Here we use a single stage op‐Amp with an

output buffer to see if we can reduce the noise.

Figure 28 : Circuit for 2nd Bandgap design

Figure 29 : Output voltage for Bandgap2 across the range of temperature. ΔVmax = 9mV (approx)

Bandgap output

Output Buffer


(a) (b)


(a) Output Noise performance 1Hz Noise = 91.5 µV/√Hz, 10kKhz Noise = 3.08 µV/√Hz

(b) PSSR , ‐47 dB at 1 Hz and 10k Hz

Table 4: Performance table of Bandgaps, with Bandgap‐1 & 2

Vsupply Output Accuracy Noise (1Hz) Noise (10 kHz) PSRR

Spec 1.8 60mV NA 100nV/√Hz ‐45 dB

BandGap‐1 1.5 17mV 210.87 µv/√Hz 2 µv/√Hz ‐40 dB

BandGap‐2 1.8 9mV 91.5 µv/√Hz 3.08 µV/√Hz ‐47dB

We do get a much better noise performance with this topology, since the noise is almost

reduced more than 50% of the Bandgap‐1 Noise. That is a significant improvement.

The Output Accuracy also has increased considerably to only +/‐ 9mV.

Although this gives a marked improvement in the output, the output noise still remains

quite high. We have enough margins in terms of Bandgap voltage output but the Noise and

PSRR still remains an issue.

The circuit still has a lot of scope of improvement.


Figure 31 : Diagram illustrating extra MOS components

We can attempt to reduce the number of MOS devices by using the same circuit topology

without the tail current MOS. Also we can use a bipolar device instead of the TN0 MOS as

shown in zoomed in view of the Bandgap‐2 circuit in figure 31.

3.3Bandgap‐3

Figure 32 : Circuit diagram of bandgap ‐3 with start‐up circuit

Figure 33 : Output voltage for Bandgap‐3 across the range of temperature. ΔVmax = 5mV (approx)


(a) (b)


(a) Output Noise performance 1Hz Noise = 306 nV/√Hz, 10kKhz Noise = 109 nV/√Hz

(b) PSSR , ‐83 dB at 1 Hz and ‐60 dB at 10k Hz

Table 5: Performance table of Bandgap Circuits, with Bandgap‐1, 2 & 3

Vsupply Output Accuracy Noise (1Hz) Noise (10 kHz) PSRR

Spec 1.8 60mV NA 100nV/√Hz ‐45 dB

BandGap‐1 1.5 17mV 210.87 µv/√Hz 2 µv/√Hz ‐ 40 dB

BandGap‐2 1.8 9mV 91.5 µv/√Hz 3.08 µV/√Hz ‐ 47dB

BandGap‐3 1.8 5mV 306 nV/√Hz 109 nV/√Hz ‐ 83dB

The values coming out of this bandgap are much better in terms of Noise performance.

Industrially the Noise due to bandgap is in the range of several 10’s of nV at 10kHz. This

circuit comes quite close to the industrial standards and serves as the base from which

further improvements can be made.

This Bandgap was tweaked about and worked upon in various ways to get to these low

output noise levels. From the given library of IBM7WL, all resistors were tested for the least

amount of noise at the output.

Table 6: Bandgap output Noise with different types of resistors and their sheet resistance

Resistor Type nV/√Hz (at 1 Hz) Sheet Resistance Ω/

oprppcres 631 260

oprrpres 2751 1600

oppdres 431.9 105

opndres 438 72

nwrrpres 2751 1600

nwrppres 631 260

nwppcres 660 NA

k1res 437 61


The readings in table 6 were obtained during the design of the bandgap when I was looking

to lower the noise of the whole system. Hence the values are not as per the output

performance shown in the figure 34. The Sheet resistance was referred from the IBM Design

Manual for their IBM7WL process.(6)

Two parameters were considered, firstly, and with a higher priority, was to achieve a low

output noise by changing the type of resistor. It can be seen that the Noise at the output

ranges from a minimum of 431.9 nV/√Hz to 2751 nV/√Hz. That is roughly 8 mes apart.

Therefore before changing the circuit topology it was prudent to change the type of

resistance which would provide the lowest resistance.

Secondly, with lower priority, the size of resistances. As can be seen from Table 6 the Noise

due to k1res (metal resistor) is fairly low, but the sheet resistance is extremely low. That

would mean a resistance in the range of several kΩ is not practical in this circuit.

Also, nwrrpes type of resistor have the highest sheet resistance, i.e., taking up least space in

the layout. But this has a very high output noise affect on the Bandgap when used as the

main resistors which lie in the signal path, i.e., R1 or R2 in Equation 22. In the startup circuit,

for Bandgap ‐3, the resistance value is in the range of MΩ and it does not lie in the signal

path, i.e., not affecting the output noise. In this case, the resistance is then used as the

nwrrpres type. This enables us to have the highest resistance in the minimum possible area

with no effect on the noise.

It is interesting to see the noise distribution inside the bandgap.

Table 7: Noise Summary for Bandgap‐3.

Spot Noise Summary (in V^2/Hz) at 1K Hz Sorted By Noise Contributors

Total Summarized Noise = 1.04402e‐14

Device Noise Contribution % of Total

I0.RP0.rma 1.88E‐15 18.01

I0.RP0.rmb 1.88E‐15 18.01

I0.Q20.q 8.59E‐16 8.22

I0.Q19.q 8.36E‐16 8.01

I0.Q1.q 8.32E‐16 7.97

The highest noise contributor is the Resistance RP0 (in Cadence Schematic), or R3 in

Equation 22. Another adjustment which was made was to make this resistance very thick in

size. I.e., the width of the resistance was set to 3µm and the equivalent length of the

Resistance depending on its resistance value was set. We can see that 3µm, serves the

purpose by being just big enough to have low 1/f noise and being small enough to have a

fairly low contribution in area when laying out.


The general Bandgap output is given by the equation

1 1 2 2

Equation 21

Which implies addition of a CTAT Voltage slope to a PTAT voltage slope to finally give an

output which is temperature independent?

In this bandgap circuit the output can be written as

∆ 1

Equation 22

Since the temperature dependence of VBE1, as given in Equation 6, if we assume n and r are

both equal to 1, then

0.087 /

Equation 23

And from equation 5 we can see that the,

1.3 /

Equation 24

Therefore from equation 22 and 23, it can be seen that the Bandgap‐3 is made to work with

α1 =1

V1 = VBE1 , which forms the CTAT part of the equation

α2 = (R2/R1 +1)

and, V2 = ΔVBE , which forms the PTAT part of the equation

Therefore to match the slope of both these parts, we need to ensure

2 1

Equation 25

Expanding α2 = (R2/R1 +1) in the above equation

2

31 1

Equation 26

Equation 26 is now the foundation of our bandgap. This not only sets the slope of the VREF

but also shows us how to set it.

We can adjust the slope in two ways.

1. Varying Resistor Ratio, R1 and R2, to make sure (R2/R3 +1) x 0.087 x 10‐3 = 1.3 x 10‐3.

As seen in the previous section, one of major noise contributor is the resistance

itself. Therefore to some extent, we have to increase the resistance value but there

is a limit up to which it starts impacting on the noise. Therefore increasing the

resistance value might not serve the purpose.


2. Varying the to make 1 . Where ln , r

being the ratio of the bipolar size.

There are further two ways of performing this:

a. By varying the size ratio of transistor size, r. This also has its practical limits.

Similar to Figure 18, the diode connected transistors have to be matched

during layout. So in theory we might be able to increase the ratio r to any

value we want, however in practise there is only up to a certain ratio at which

we can ideally march. Some of the acceptable ratios are 1:8, 1:16, 1:32 and

1:64. Beyond this it becomes difficult to match.

b. Another technique used for ultra low bandgaps is known as the stacking

Figure 35 : Block Diagram to illustrate the ΔVBE stacking(7)

To avoid large transistor ratio, r, the concept of ΔVBE addition can be used. The circuit

shown in figure 35 uses this approach presented in a thesis report from Mr William T

Holman, which helps lowering the noise since dependence on the resistance ratio is reduced

considerably. The author simulated this concept and measured the output noise in the level

of 30nV/√Hz (at 10kHz)

A patent on a similar concept was filed by Sander Gierkink (8)

This technique could be further used to reduce the noise to ultra low levels in bandgap‐ 3

aswell.


Chapter4:CornerSimulationsforBandgap‐3

Bandgap‐3 circuit is now selected to be used for next stage, to perform the worst case

corner simulation. These corners are industry based actual samples from Rakon. The

following points explain the setup.

1. Temperature : ‐45 to 90C (Although ‐45 to 125 is also successful for Typical Model)

2. Supply Voltage , Vdc : 1.6V ,1 .8V, 2.0V (Vdc has been tested for 1.5V to 2.2V for a

Typical Case)

3. Strong & Weak characteristics for the following Model files (Also simulated for the

Nominal/Typical Corner):

a. Bip.scs : npn Bipolar devices

b. Bipp.scs: pnp Bipolar devices

c. Nmos.scs : NMOS devices

d. Pmos.scs: PMOS devices

e. Rescap.scs : All Resistances and Capacitances in the IBM7Wl library.

4. Total Number of Corners , therefore 3(Vdc) x 2 (bip) x 2 (Bipp) x 2x(Nmos) x 2 (Pmos)

X 2(ResCap) + Nominal = 97

5. Simulation Type = 3σ

Figure 36 : Bandgap Output Voltage across all Corners


Table 8 ΔV Values across all corners

Deviation from Mean

ΔV (negative) ΔV (Positive)

Best Corner ‐5.73m 0

Max. Positive Deviation Corner ‐20.5m 9.68m

Max. Negative Deviation Corner ‐14.8 3mV

Worst ΔV among Corners |ΔV/2| 53mV

General Industrial standard before trimming the output is 5% of absolute value. Our

Bandgap supplies a Raw voltage of 1.18V therefore a range of +/‐ 60 mV. We have a

deviation of +/‐ 53mV from the mean for worst case corners

Any further accuracy can be implemented by adding trimming circuits to the bandgap.

Figure 37 :Output Noise of the Bandgap (measured at Vref in figure1)

Table 9 Noise Values across all corners

Across All 96 Corners

Min Noise Typical Noise Max Noise units

at 1Hz 142 305.9 1385 nV/√Hz

at 10 kHz 92 101 114 nV/√Hz


Figure 38 : PSRR

Table 10 PSRR Values across all corners at 1 Hz

Max Typical Min units

‐121.7 ‐83 ‐76 dB

Figure 39 : The Bandgap starts working at about 1.3V. the corner simulations were tested for 1.5V


Figure 40 : Current Output from Bandgap

Figure 41 : BGR Output Currents corners

This Design was transferred from the current Rakon machine to the University system and a

sample run was performed with the University Models for tt, sf, ss at 1.6V , 1.8V and 2.0 V

(i.e., a total of 9 corners). The University wave is shown in Figure 42 below.


Figure 42 : BGR Output Currents for university corners

ΔV across all corners, for worst case = 5.9mV.


Chapter5:Layout&Extraction

5.1TheoryAfter we fixed a schematic design the next step is to Lay it out. In this exercise we continue

to use the tools by Cadence IC design Suite, and have used Cadence Layout XL. The Layout

techniques which have been listed below are techniques based on this specific layout and

each circuit will have its own priorities when laying it out.

1. In the Schematic of any Design there will be PMOSes and NMOSes closer to the VDD

and GND/VSS. A good tip to begin layout will be to move the PMOSes up and NMOSes

down.

Figure 43 Basic layout techniques attempted

2. In this exercise initial routing was done as per the standard practice of M1 and Metal

3 in Vertical and Metal 2 and Metal 4 in Horizontal , but later modified to reduce the use of

Metal 3 in the layout, thereby reducing the effective cost of fabrication. Although this is a

very small design, it highlights the use of designer’s choice in order to have the same layout

in different ways.

All the elements supposed to

be connected to VDD

All the elements supposed to

be connected to vss

Diode Connected Transistors in a 3x3

matrix


Figure 44 : Routing using Metal 3 in Revision 1 of Layout

Figure 45 : Routing reduced to Metal 2 in Revision 2 of Layout

Metal‐3 (Vertical)

Metal‐2 (Horizontal)

M3 – M2 Taps

Metal‐1 ( 0.75 µm Wide)

Metal‐1 (Horizontal)

Metal‐1 ( 0.35 µm Wide)

No Taps



Figure 46 : Routing using Metal 3 in Revision 1 of Layout, 2nd Example

Figure 47 : Routing using Metal 2 in Revision 2 of Layout, 2nd Example

This has enabled us to reduce a metal layer without increasing the area of the layout,

however one has to be careful while attempting to do this since it can cause routing

problems later in the Layout stage or might increase the metal track lengths to achieve the

same connection. Therefore it comes down to designer’s judgement.

3. The MIM Capacitor (metal‐insulator‐metal) is relatively small for the same

capacitance, therefore is a big advantage if looking for a smaller footprint.

M1 – M3 Taps


M1 – M2 Taps



(a)

(b)

Figure 48: Layouts (a) with 1pF MIM Capacitor, and (b) with 1pF vncap capacitor.

Therefore using this seems a much better option, without degrading the performance.

4. “Mimhk” type capacitors, unlike regular capacitor are formed on the top layers in

the process.

MIM Capacitor

vncap Capacitor


(a)

(b)

Figure 49: 1pF Capacitor used in the design (a) as a component (b) split up in different layers

This means that the space beneath the capacitors can be used to place the component.

Therefore this is the second advantage with this type of capacitor, that components using

up to M3 can be placed underneath it, thereby saving area.

Since this component uses the top two layers in a process, this also changes the wiring

scheme. Unlike conventional capacitor, this is not formed with poly‐gateoxide‐nWell but is

formed at the top level metals. Also the two terminal are supposed to be pulled from the

same highest layer, to prevent dielectric breakdown (9)

LAYER: E1

(dwg)

LAYER: MT (dwg)


Figure 50 A test circuit to be used for MIM Layout

Figure 51 Layout for a test circuit to be used for MIM Layout

Figure 46 and 47 explain the concept of wiring to MIM capacitor with a sample circuit.

5.2ExtractionThe bandgap was extracted and cleared for all the DRC, LVS and Floating Gate and NWell

Errors. The following figures shows the full laid out circuit and additional features

incorporated to clear all the design rules.

MT to E1 VIA before connecting

to VSS Pin

M1 to E1 (Through M2‐M3‐M4‐

MT layers) VIA for connecting to

the top Plate of the Capacitor


Figure 52 Extracted view of the Bandgap‐3. Size of 100x131µm2.

NWELL

Protective Diode

ConnectionVDD

Figure 53 NWELL Protection

NWELL

P Substrate

VDD

Reversed Biased Diode

VSS

Figure 54 NWELL Protection Schematic


P-Substrate Taps

Polysilicon Gate

Protection

Figure 55 Gate Protection

Size of the cell could further be reduced by about 5% to 10% with proper laying out of

components.

5.3CurrentSourcesfortheOutputStage1. Ideally, the currents coming out of the current mirrors are precise and Drain‐source

voltage independent. As the design moves towards more practical models these

non‐Ideal effects start to creep in and depending on the Output Nets voltage (and its

swings) the output current derived might not be as per theoretical calculations.

Figure 56 Output Stage current sources for the Bandgap Reference

Bandgap Voltage


2. In figure 11, we can see the outputs are labelled as :

a. vdd_10u

b. vdd_20u

c. vdd_40u

d. vdd_100u

These outputs were tested for constant VDD conditions. Depending on the usage of

these current references, e.g.: a Tail Current bias for an OpAmp, or an output Stage

Bias, etc., the desired accuracy will change and also the Voltage across these nMOS

devices will vary. Therefore these circuit level changes can either be acknowledged

and the required amount of accuracy in the output current can be implemented, or

less stringent accuracy levels can be accepted.

3. Possible ways to improve the accuracy :

a. One of the conventional ways would be to provide a high output impedance

for these current mirrors. Either by a cascode or using an enhancement type

MOS.

b. Adding extra resistor on the Source.

4. To finish the trial within the given time frame a considered decision was taken to

make changes in the Width of the Transistors , and leave out the other options

enumerated in Point 3 above. In order to match the output currents, parameterized

simulations of width were run to find out the approximate widths that would supply

the best output current over the entire Temperature range. The result is we have

Width ratios as:

a. W0:W1 = 2 : 2

b. W0:W2 = 2 : 3.9

c. W0:W3 = 2: 7.64

d. W0:W4 = 2: 18.9

Where W0, W1, W2, W3 and W4 are the corresponding widths of the

Transistors TN0, TN1, TN2, TN3, and TN4 in figure 1.

5. This meant that the conventional matching in the Interlocking Fingered way, as

shown in Figure 12 and Figure 13 wouldn’t work.

Figure 57 Conventional Inter fingered matching as DDCABCDD. Transistors A(TN0) and B(TN1) are of the same size.


Figure 58: Zoomed in view between TN2 TN0 highlighting the errors due to notches. Transistors A(TN0) and B(TN1) are of the same size. Scale shown in Microns

6. In conventional matching this would not be a problem since the Transistors sizes are

an integral multiple of each other and such notches are therefore avoided.

7. Since I had already made the schematic without realizing the Layout issues, I can

either make the Widths Integral multiples, for example W0:W4 = 2:20 instead of

2:18.9, or try to lay them compromising the effective matching.

8. I am currently working on a slightly unconventional Layout. Since the Lengths of all

the transistors are same, I plan to stack them vertically instead of horizontally.

Figure 59 Transistors Stacked on their Gates, instead of Drain and Sources

PolyPoly

RX RX

Since Transistor Lengths are constant. They have

been stacked vertically

Metal‐1

(Commo

n DRAIN

Or

SOURCE

)


The Matching technique for this design is described below, were we have 5 set of transistors

to match. Figure 60 and 61 presents the matching diagrams

Figure 60 Present Transistors Matching representation, A and A0 represent the same W/L Transistor

A

B

C

C

D

D

D

D

D

A0

B

C

C

D

D

D

D

D

Dummy

Dummy

Dummy

Dummy

Dummy

Dummy

Figure 61 Another Matching scheme that can be used, A and A0 represent the same W/L Transistor

Using the same concept as in figure 60 we stack the transistors on top of each other and

connect the same transistor with their respective Vdd’s. A zoomed in version of the

matching used in this exercise is shown below in figure 62


Figure 62 Transistors Stacked on their Gates, instead of Drain and Sources

The overall layout of both the Current sources and the Band Gap are shown below in figure

63.

(a) (b)

Figure63: (a) Layout for Current Sources 17µm X 81µm, (b) placed alongside Bandgap Reference

Common Gate

Common Source Connection,

VSS

VRef

Vdd_10u

Vdd_20u

Vdd_40u


The layout of the Output current sources, Figure 63 (a), is made lengthwise also because it

can easily be stacked next to the main bandgap reference circuit. Although a much tighter

packing of these two structures was possible, it was not attempted to go beyond this

current one. Since the area is not a major concern in this exercise more emphasis was given

to the Matching and overall accuracy than the size.

The size of the Output current sources comes out to be 17µm X 81µm, and the size of the

Bandgap circuit is about 131µm X 100µm.

We will check these extracted models for their accuracy in the next chapter.


Chapter6:Schematicvs.ExtractedBandgapSimulations(withuniversitycorners)The following figures show the tests conducted for Schematic vs. Extracted bandgap circuits and compare the output to see it still matches the

specifications. The Test setup is shown below in figure 64

Figure64: Schematic vs. Extracted Circuit

Bandgap reference ‐

Schematic Bandgap reference ‐

Extracted

Current Sources ‐

Schematic

Current Sources ‐

Extracted

Voltage source (vdc_out) sweep to test

the output Impedence of the 10µA

current sources on both the schematic

and Extracted circuit


Figure 65 Output Voltage from ‐45 to 90 °C, with VDD varying from 1.6V to 2.1V

The maximum ∆Vout (across all waveforms = 5.9mV)

Figure 66 PSSR Wave from 1 Hz to 10G Hz.

Min ‐76.8dB, Max = ‐125dB


Figure 67 Output Noise Wave

Noise at 10k Hz = 101.9V, Noise at 1Hz = 308.53Hz

Figure 68 Quiescent Current


Figure 69 Output Currents for Simulated and Extracted circuits.

Table 11 Output Current Results (Units in µA)

(at 25°C) 100µA Source

40µA Source

20µA Source

10µA Source

Simulated 101.81 40.1 19.97 10.041

Extracted 94.78 38.3 19.57 10.041

Figure70: Output Impedance for Simulated and Extracted circuits. Worst Case 2.5MΩ


Chapter7:Summary

SpecificationComplianceMatrix

Table 12 Specification Compliance Matrix

Specification Simulation (Rakon Corners,96No.s)

Extracted (University Corners, 9 No.s)

Parameter Min Nom Max Min Nom Max Min Nom Max Units

Power supply, Vdd 1.7 1.8 1.9 1.6 1.8 2.0 1.6 1.8 2.0 V

Temperature ‐40 27 85 ‐45 27 90 ‐45 27 90 °C

BGR o/p, Vref Const. 1.18 1.18 V

BGR o/p Accuracy ‐30m +30m

‐30m

+58m ‐5.8mV

0mV

V

BGR o/p Ref Currents 10 10.04 10.04 µ A

(at 25°C) 20 19.97 19.57 µ A

40 40.1 38.3 µ A

100 101.8 94.78 µ A

Output Impedance (for 10µA o/p Ref Current) 1M 2.5M 2.5M Ω

PSRR ‐40 ‐75 ‐83 ‐99 ‐76.8 77 ‐125 dB

Noise (at 1Hz) N.A 142 309 1380 308.5 nV/√(Hz)

Noise (at 10kHz) 100 92 101 114 101.9 nV/√(Hz)

Quiescent Current, Idd ( BGR) 100µ 66 µ 56.5 µ A


Chapter8:NoiseAnalysis

A Noise producing elements pass on the noise to connected elements. The final output

noise of a system can be affected either by certain types of noise profiles, from certain types

of elements, or a noise producing element can affect the final system noise at particular

frequencies.

A typical connection of a BGR associated circuit is shown in figure 71.

Figure 71 : Typical Noise Producing Elements in an example system

The power supply noise can be expected to have an effect on the final oscillator noise. Since

the oscillator is connected to multiple units, such as the Crystal itself, the Control supply to

adjust the frequency of operation, and the LDO output the effect of the oscillator noise

might be different from different sources.

In this exercise we examine the effects of different noise sources on our main output.

Similar to the scheme shown figure 71, we will use a circuit equivalent in a schematic editor.

These are the actual circuits provided by Rakon UK Ltd. and the simulations were carried out

to understand the noise flow through their system. In this case the Bandgap was assumed to

be an Ideal Voltage source, i.e., with no Noise, and the remaining circuit was tested.

The purpose of the test was to analyze the circuit with different noise producing elements

and how it affects the final output noise.

Figure 72 shows the circuit under test where we use the Industrial LDO, Oscillator and its

oscillator control circuit.

This test bench is pre‐arranged so that the output frequency of the Oscillator = 26MHz.


Figure 72 Noise analysis circuit

Vcontrol


1. As a tool: In Cadence a Noise can be simulated by

a. Either placing noisy elements , such as a Resistor (for Flat band

Noise/Thermal Noise)

b. By placing MOS devices to add 1/f noise etc.

c. Uploading a Noise profile .txt file can be added onto an ideal voltage source

2. In the Initial test conducted Analogue library Sources were used to give us an

estimate of the performance of system in an Ideal case. This result can then be used

to compare the results obtained with actual Noisy elements.

(a) (b)

Figure 73 (a) Output Phase Noise of the Oscillator and (b) Periodic steady state of the Oscillator output.

a. Here the Noise at 1Hz = ‐62.4 dBc

b. Noise at 10kHz = ‐ 147 dBc

[dBc is the Noise w.r.t to the carrier frequency]


Vcontrol is the input to the Oscillator Tuning Circuit shown in figure 72, which is responsible

for setting the oscillator operating frequency. Keeping all other sources Ideal, a Noise profile

was added on top of Vcontrol and the Phase Noise at the output of the Oscillator was

measured.

Figure 74 Phase Noise due the addition of a typical Noise profile (/ravi/noise.txt1) on Vcontrol.

A difference of 5.18 dBs can be seen at 1 Hz frequency, in figure 74. This noise affects the

lower frequency (1/f) region of the noise slope.

Similarly a test for VLDO was performed , keeping every this else Ideal added to see the Noise

at the Oscillator output

Figure 75: Phase Noise due the addition of a typical Noise profile (/ravi/noisel.txt2) on LDO Output (fig 72).

1 noise.txt file was an actual noise profile for Control supplied by Mr Ravi , IC Design Engineer in Rakon 2 noisel.txt file was an actual noise profile for LDO supplied by Mr Ravi , IC Design Engineer in Rakon

Output Noise due

to noise in LDO

Output Noise due to

noise in the Control

Supply

Output Noise

performance of

the Oscillator due

to Ideal Voltage

Sources


In this case the Noise affects the higher frequencies region of the Noise slope. A difference

of almost 2 dB is observed between the Ideal case and the Noise addition at about 300kHz.

At this instance we are interested in finding out the region of slope at which the deviation

starts due to LDO Noise and due to Control Noise.

8.1LDOPhaseNoiseA series of simulation runs were carried out to see the affect of additional LDO Noise over

Ideal Source and corresponding frequency beyond which the effects were pronounced.

The typical Noise profile file for the LDO, noisel.txt was modified to have a range of noise

values. The values of Noise were changed so that the tests could be performed with

increasing severity of noise as:

Ideal Case, Noise, 10x Noise, 100xNoise and 1000xNoise.

A sweep of this was carried out to see the affect of these on the output performance.

Figure 76: Phase Noise profiles at the Output of the Oscillator. Each wave is represented by the Noise X

<value> in the same corresponding order.

This output performance was then analysed to see at what frequencies the deviation is

maximum. The Noisy waveforms were each subtracted from the ideal waveform to see their

differences w.r.t frequency.


Figure 77: Standard output Phase Noise for different profiles, and the difference of each wave from the ideal

one.

As can be seen from waveforms in Figure 77, the Effect of LDO Noise reaches a peak just

before 104 Hz and reaches a second peak just after 105Hz. These waves are the levels of

Noise over the ideal performance.

It can also be seen that the affect of LDO noise starts impacting as soon as 102Hz. At this

point there is a sharp rise in its value until it reaches the first peak.

Another set of waveforms is plotted which shows the rate of change of noise w.r.t the ideal

curve in figure 78. This helps us identify the place from where the noise starts to rise and

how fast.

Figure 78: a 2x Noise and 10xNose wave differential of noise (difference from the Ideal )wave .

It can be seen that the peak occurs between 102 and 103 Hz. After which, although the

absolute error remains, it starts to decelerate and after 104Hz becomes almost constant.


Figure 79: : A summary of output phase noise performance for different LDO input noise levels.


8.2ControlSupplyPhaseNoiseSimilarly Control Supply Phase Noise was added onto an ideal system to observe the

Oscillator output noise.

The levels of noise added can be seen in the waveforms below in figure 80. Similar to LDO

Phase Noise Analysis, a difference of Output Noise performance for different Control Supply

noise vs. the Ideal case were plotted to observe the relative magnitudes.

Here again, the Noisy waveforms were each subtracted from the ideal waveform to see the

difference between w.r.t frequency.

Figure 80: (top)Oscillator Output Phase noise for different levels of noise at control supply.

(bottom) Difference between output noise waves w.r.t Ideal wave

In this case, we can see that the Phase Noise on Control Supply affects the lower

frequencies more. The difference starts appearing at 1 Hz noise.

This difference then peaks between 102 and 103 Hz and begin to drop to almost 0 at about

105Hz.

Here also, we can see the rate at which the difference occurs, in figure 82 : The summary of

waveforms.


Figure 81: A summary of output phase noise performance for different Ctrl input noise levels.


From figure 81 it can be observed that the rate of change of Noise is maximum at lower

frequencies and the rate of change becomes almost constant beyond a few 100Hz.

8.3Experiment‐1:LowPassFilterA small experiment was carried out based on the findings of figure 13 to try and reduce the

output noise from LDO by passing it through a low‐pass filter. The highest rate at which the

error starts to pick up lies at very low offset frequencies, in the region of 10Hz.

Ideal Voltage Source

Oscillator

Ctrl Supply

Oscillator Output + noise

+

filter

Figure 82: an experimental setup by adding a filter in front of the Ctrl supply noise

Now since the control supply voltage source, with its specific Noise Profile, affects at low

offset frequencies, a Low Pass filter, for these low frequencies were added to see if the

noise can be further removed.

Figure 83: Waveforms for Output Phase Noise of the Oscillator with Low Pass filter at the input Ctrl Supply line

Although the noise is pulled closer to the Ideal curve, the value of capacitance and

resistance involved increased quite significantly. The capacitance values, marked in circles,

increase to very high values in scales of nF.

Ideal Noise Profile of

the Oscillator

Noise Profile without a

Filter


8.4LDOandControlSupplyPhaseNoiseRegionsAt this point another set of tests were performed to see at which frequencies (or a range of

frequencies) the effect of LDO Noise and Control supply noise begins to impact the

Oscillator Output Phase Noise.

If we get an idea at what range of frequencies below certain level only Control supply Noise

affects more , and above a certain frequency LDO Noise Starts to dominate we can adjust

the noise performance of these units accordingly, to give an overall Oscillator Output noise

which is controllable.

Figure 84: Oscillator O/P Phase Noise waves for Ctrl voltage source noise from Ideal to 1000 Times its std noise

profile & LDO Source Noise from Ideal to 1000 Times the std noise Profile.

In this bunch of waves, we have the control supply noise affecting at lower frequencies, and

LDO supply noise affecting at higher frequencies. We intend to find out the tipping point

where the dominance of Ctrl Supply ends and LDO noise beings.

For this we subtract the noise due to Ctrl Supply from the noise due to LDO supply and see

the difference.


Figure 85: Output Phase Noise dominance between Ctrl Supply and LDO supply.

From figure 85 a clear point on frequency scale can be seen between 30kHz and 40kHz

where the Noise due to Ctrl Supply and LDO becomes almost equal, and hence their

difference becomes zero.

It can be inferred that if the Oscillator output Noise is to be targeted for lower offset

frequencies ‐then the adjustments in Control supply will have a higher impact. Similarly, if

the target is at higher offset frequencies beyond 30kHz then the LDO circuit will have a

higher impact.

Ctrl Supply

Dominance

LDO supply

dominance


Chapter9:Conclusion

A thorough description of bandgap principles were discussed and critical components used

in analogue and mixed signal designs were look at . Several important tests were carried out

to understand the parameters in these building blocks and how these could be tailored to

meet a designer’s needs. The results of these tests were used to design a Bandgap circuit

which went through a design cycle keeping the required specification in mind.

A low Noise Bandgap circuit was developed and simulated for stringent Industrial Corners,

supplied by Rakon UK Ltd., as well as University specified corners for the same IBM7WL

process. The lowest noise levels achieved were in the range of 100nV/√Hz and the accuracy

matched the specifications. A detailed compliance matrix is shown in Chapter 7, Table 12.

9.1ScopeofImprovement Although the Bandgap reaches the target specification in terms of Noise

Performance which is industrially acceptable, it can be lowered even further by using ΔVBE

Techniques. ΔVBE stacking theory explains the concept in making a bandgap relying less on

the Resistances and using the property of Bipolar, which are low noise devices, to attain the

same Reference voltage.

This concept is also presented in a Thesis by Mr William T Holman (7) on which several

patents have also been filed, for example Sander Gierkink Patent(8).

The output performance of a Bandgap is usually accepted if it performs at an output

of +/‐5% of reference Voltage. This 5% deviation is then adjusted through trimming circuits.

Usually in the topology that has been presented in Bandgap‐3, section 3.3 in Figure 32,

these trimming circuits would be applied to the resistance values so as to enable the taped‐

out chip to have control over output voltage. These resistance values can be adjusted to

finally allow a very high degree of accuracy even in the worst case corner. Also trimming

circuits can be used to regulate the output supply. (10)

These features on top of a low noise bandgap circuit can provide a low noise, highly

accurate, user specific voltage reference.

The Output Resistance of the Current Mirrors at the output stage of the Bandgap,

Chapter 5.3 Figure 56, can be further increased by using Cascode as shown in Chapter 2.2

Figure 19 and Figure 20. That would need a Bias Circuitry to go along with it. Although a

Cascode would mean a headroom problems with minimum VDD. This can be worked around

with low voltage cascades and also because we see a head room of about 0.3 V as shown in

the Chapter 4: Corner Simulations for Bandgap‐2, Figure 39.

During Layout, although Common centroid techniques were used to minimize the

mismatch, Dummy structures were not placed due to time constraint. Considering we need

very high matching in this Bandgap it is advisable to implement the dummy structures.


Section 5.3, Figure 61 and 62, explains some of these concepts but were not implemented in

this design.

These are some of the obvious scopes of improvements which can be implemented to this

circuit.

References1. Sansen, Willy. Bandgap and current reference circuits. [book auth.] Willy M.C. Sansen. Analog Design

Essentials. Catholic University , Leuven Belgium : Springer, 2006.

2. Zenhbroeck, B. Van. Chapter2: Semiconductor Fundamentals. Principles of Semiconductor Devices. s.l. :

Department of Electrical , computer and Energy Engineering, University of Colorado at Boulder, 2011.

3. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Chapter 11 Bandgap References. s.l. : TATA

McGraw‐Hill, 2002.

4. IBM Corporation. BiCMOS‐7WL Model Reference Guide. 2011, Vol. V1.8.1.0, 11.4. Page 183.

5. Redman‐White, Prof. W. Analogue & Mixed Signal CMOS Design. s.l. : Dept. of Electronics and Computer

Science, University of Southampton, 2011.

6. Aylward, Kevin. Low Area, Low Power Startup Circuit. Analogue Design, Kevin Aylward, B.Sc.,. [Online]

October 2006. http://www.kevinaylward.co.uk/ee/zeropowerstartup/zeropowerstartup.html.

7. IBM Corporation. IBM Design Manual. ES#70P3341 BiCMOS7WL Design Manual. 25 January 2011.

8. Holman, William Timothy. A Low Noise CMOS Voltage Reference. Georgia Institute of Technology , USA.

1994. p. 176.

9. Gierkink, Sander. Low Noise Bandgap. US007242240B2 USA, 10 July 2007. United States Patent.

10. IBM Corporation. BiCMOS 7WL Training Manual. 2007, Vol. Revision 6.2, p. 309. Page 52.

11. Martinez Brito, J.P. Bampi, S. Klimach, H. Kimach, A 4‐Bits Trimmed CMOS Bandgap Reference with an

Improved Matching Modeling Design.. June 2007, IEEE International Symposium on Circuits and Systems, 2007

(ISCAS 2007), pp. 1911 ‐ 1914.

design of pvt tolerant bandgap reference circuit for low noise and low current

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