design review: 500 w phase shifted zvt converter 4-1 · a high power density 500 watt phase shifted...

3/25{93

Bill Andreycak

Abstract:

A high power density 500 Watt Phase Shifted

power supply design is presented and reviewed.

This practical 200 kHz full bridge converter oper-

ates from a 385 Volt dc input bus, typical of a

Power Factor Correction circuit, and outputs a

regulated 48 Volt dc bus for distributed power and

Telecommunications applications. Low profile,

planar magnetics are featured with full 3750 Vac

safety isolation. Over 93% efficiency is achieved.

Power density approaching 40 Watts per cubic inch

(2.5 W/c1r?) is featured, suitable for load-shared,

modular power converter applications. Operating

waveforms, printed circuit board layout and mea-

sured efficiency of the actual breadboard are also

presented.

370 to 410 Vdc

48.8 Vdc

2 .10.5 Adc

50 .550 Watts

93% at fullload

100 mV pk-pk

1%

1%

50% -100%

3750 Vac

200kHz

40W/in3 (2.5W/cm3)

4.5. x 2.0. x 1.4.

Design Overview and ConsiderationsThe fixed frequency, phase shifted ZVT conver-

sion technique was implemented using the UnitrodeUC3875 IC for control. Power to this unit includingthe IC bias supply is delivered by a universal Ac(85-265 Vac) input ZVT Power Factor Correctionmodule. The phase shifted converter's outputvoltage feedback path will incorporate an optocoup-ler to maintain the safety isolation voltage. Wherev-er possible, standard, commercially available prod-ucts have been incorporated to simplify develop-ment efforts. A goal to achieve a standard 2.375"

DESIGN SPECIFICATIONS :

Input Voltage Range :Output Voltage :Output Current Range :Output Power Range :

Efficiency:Output Ripple :Line Regulation :Load Regulation :ZVT Power Range :Safety Isolation :

Switching Frequency:Power Density :Physical Dimensions (target) :

4-1Design Review: 500 W Phase Shifted ZVT Converter

by 4.625" footprint, low profile fmal assembly,suitable for modular power applications has beenset. The trend toward half-inch total physical height,while recognized, was not currently possible toachieve for this 500 Watt design.

TopologyA mastery of the basic full bridge topology is

needed before initiating the design of this phaseshifted derivative. This knowledge allows for somefIrst round approximations regarding the activesemiconductor components, passive components andisolation levels required throughout the varioussections of the converter. Only items unique to thephase shifted version of the full bridge converterwill be covered in significant detail. Based uponconservative design practices, the author has takenthe liberty to make a few initial selections whichare outlined in the next section.

SemiconductorsThe MOSFET switches selected for this 500

Watt, 400 Volt application are readily availableIRF840 types. These 500 V devices are conserva-tively derated by twenty-five percent during normaluse. Although the "on" resistance, hence conductionpower losses could be lowered by using heftierdevices as in a conventional design, large switchesare not used in this design. Several factors andtradeoffs have been weighed to arrive at this deci-sion. They are: longer transition times, reducedmaximum duty cycle, higher primary circulatingcurrents and potentially lower efficiency. All factorsfocused on the use of the '840 switches as theoptimal choice which was confIrmed by a computerspreadsheet program and presented elsewhere in this

paper.The output rectifiers selected are 200 Volt, 16

Amp ultrafast recovery devices to keep powerlosses low. A series resistor/capacitor (R/C) snubberis used across the transformer secondary windingsto minimize voltage excursions. While switchingwaveforms on the primary are virtually noiseless,the leakage inductance between the secondarywindings can lead to ringing and the need topassively snub. The snubber circuit used limits theoutput rectifier transient voltage overshoot toapproximately 150 Volts, leaving an adequate safety

margin. The 16 Amp diodes were selected to keepconduction losses reasonable while amply handlingthe rms current. Recovery time is not critical due tothe series ZVT inductance on the primary , but fastrecovery assists in keeping losses low.

A series inductor is used on the primary to makethe Zero Voltage switching Transitions possibleunder various output loads. Energy is stored eachtime power is transferred from the prim'4CY to thesecondary , and circulated in the primary only duringthe freewheeling periods. This stored energy isnecessary only to accomplish the left leg resonanttransitions, and is transparent during the "linear"right leg transition. Additionally, this inductor limitsthe rate of change in primary current, furthersoftening the power transfer edges.

A dc blocking capacitor is used in series with theprimary for this example, primarily because voltagemode operation (duty cycle control) is incorporated.No net voltage was expected to be measured acrossthe capacitor since the applied volt-second productsin consecutive switching cycles should be identical.Experiments with voltage feedforward, currentmode control and average current mode controlwere not conducted.

Overcurrent protection has been incorporated bymeans of a current sense transformer also in serieswith the primary winding. A standard Pulse Engi-neering toroidal transformer, model #PE-64977 wasused with a single turn primary winding and anisolated 20 turn secondary .This part features lowleakage inductance, 1250 VRMS isolation and 20 Apeak current sense capability. A full bridge diodearray reconstructs the signal referenced to theUC3875 controller "ground" return. A small R/Cfilter cleans up the waveform which is input to theIC's current sense pin. Resistor R is selected suchthat a 2.5 V peak signal corresponds to a 15%overload and will trigger the UC3875 current limitprotection circuit

Several low ESR/ESL aluminum electrolytic andceramic monolithic capacitors are paralleled to formthe output filter section. This arrangement yieldsvery low parasitics while providing the correctcapacitance value for filtering.

4-2 UNITRODE CORPORATION

repeatability over manufacturing tolerances for thisparameter. The power supply industry trends tOowards high power density and low profile modulessteered the decision towards a planar transformerdesign concept For the purposes of this presenta-tion, a successful transformer design must beuniversal and adaptable with minimal design effort.Ideally, the design must meet International SafetyAgency isolation requirements and accommodate awide variety of different output voltages and cur-rents. Accommodating all of these design objectivesmight be best achieved by going with an existingsupplier of planar magnetics as opposed to doing it"from scratch".

Multisource Technology Corporation was con-tacted to supply the prototype main transformerwhich was essentially one of their standard prod-ucts. The specific model selected came from theT -500 series which is rated at 1000 Watts of outputpower when operated at 250 kHz and 100°C "Hotspot" core temperature. This design example will

Main Power Stage DesignThe focus of this presentation is the design and

evaluation of the phase shifted ZVT power stage. Aschematic of the main power stage is shown inFigure 2 for clarity. Note that neither externaldiodes nor capacitors are placed in parallel with thefour MOSPET switches. The otherwise parasiticoutput capacitance (Coss) is fully utilized as themain part of the resonating capacitance, and theMOSPET intrinsic body diode are used to clampthe voltage excursions to the input supply rails.These body diodes are later shunted by the MOS-PET on-resistance during the freewheeling portionsof the period, lowering the losses.

The design of each of the major componentsshown in Figure 2 is featured, beginning with thenext section covering the main transformer.

Main Transformer DesignThe design goal of the main transformer was to

minimize leakage inductance while maintaining high

r-PIOT2

I§;

QA11.--

' 'I-'

, R14

VAVB

I~I( ~

C11 C12

R18 R19C16'..rD15

-*-'C14 r

C15

~

PIOT308 QD

I~ --

I~.R15 R17

Fig 2. -Phase Shifted PWM Converter Power and Output Circuit


Transformer SelectionThe Multisource Technology T -500 series was

the most appropriate selection and the specificdetails will now be highlighted.

conservatively operate the transformer at one-halfrated maximum power, allowing ample room for

higher power applications.

Transformer Design ProcedureThe starting point of any transformer design

should be an estimate of an acceptable temperaturerise, and a 25°C total rise is quite typical. Next, thecore Area Product can be calculated using theformulas to approximate the core size for a conven-tional design. However, with planar magnetics, theArea Product (AP) calculation does not equallyapply. This is primarily because of two reasons; thereduced core volume (V e ) of these low profiledevices in comparison to the full height, standardcores, and the reduced winding area (Aw). Thereduced core volume for a given magnetic crosssection allows for higher flux density (B) for thesame temperature rise. Another option is to usefewer turns for a given temperature rise, whichhelps to result in a compact, low profile transformerdesign. For these reasons, it is best to consult andwork closely with the transformer manufacturer to"home in" on the best core selection for a planartransformer application.

Fig 4 -Electrical/ Mechanical Specifications

TOP VIEIJ

~

9

:0

rl1000000'"' -",M

..I (\j MMM

FRONT VIE\I

~ I I Sr-1- o

.040 ,003 DIAH. -Il-l

TIN PLATED PIN

Fig 5. -Mechanical Dimensions

IIo oo oW\11

Io~

/Q

-700 MAX.

, 200 MIN

Fig. 3 -Planar Transformer Characteristics

MTC planar transformers are designed to operate in120VAC!22OVAC environment and to meet UL, CSA, V DE andIEC safety requirements for isolation transformers.

o 4kV Primary-to-Secondary dielectric isolation

o 6-8 mm creepage and clearance distance between primary

and secondary windings

o Three ply isolation

o Typical efficiency 98%, low temperature rise

o Low leakage inductance

o Low height 0.53-0.8° (13.5-20 mm)

o High frequency operation 50-1000Hz

o Excellent repeatability, all windings are pretooled

o PWM or resonant topologies

o One to four secondaries

o Efficient cooling

o Low weight from 0.6 oz. (20 g) per 100W

o 200W-1500W power capacity at -40°C ambient temperature


23002.1501.950l75Cl550l350U50.~50

..750

..550

.350.150O

Temperature RiseA 25°C total core temperature rise will be used

to initiate the transformer design. The allowablepower dissipation can be determined from thetransformer's lO°C/W thermal impedance, RnIETA-hot spot to air.

PXFMR = tRISE/RTHETA = 25/10 = 2.5 W

This power loss is the sum of the core andcopper individual losses. Usually, losses are appor-tioned equally between core and copper, a gooddesign practice which will also be used for this

design.

PCORE = PCOPPER = 12.5/10 = 1.25 Weach

Transformer Operating FrequencySwitching frequencies as high as 300 to 600 kHz

have been tried with acceptable results, and areworth further consideration. However, in thisapplication, 200 kHz has been selected as a reason-able and practical compromise between minimizingcore losses and reduced transformer and outputinductor volume. In the full bridge topology, thecore flux swings at half the switching frequency.Thus, the transformer operating frequency in thisdesign is 100 kHz.

Flux DensityThe operating flux density (B) is determined

from the transformer operating frequency, allowablecore loss (pcore), and the core set volume (Ye).First, the core loss in mW/cm3 is calculated.

Pwss = 1.25W / 24.2cm3 = 52 mW/cm3 axis, a peak flux density of 0.065 Tesla (650Gauss) is obtained. Note that the total peak to peakflux excursion, LlB, is TWICE the peak flux density(which is given in most core manufacturers coreloss curves). Thus, in this application, LlB is 0.13Tesla or 1300 Gauss.

Primary Number of TurnsThe required number of primary turns is calculat-

ed by solving Faraday's Law using the known

parameters.

Next, the manufacturer's "Core Loss vs. FluxDensity" curve for the core material is used todetermine the correct peak flux density. Thisexample uses Magnetics Inc. "P" type materialwhose core loss curves are shown in Figure 6. Notethat this curve is obtained using a much differentcore shape than that of the planar design, so somemeasured verification may be required.

The exact flux density is found where the diago-nal 100 kHz frequency line intersects with52m W /cm3 core loss on the vertical axis. Droppingdown from this point to the horizontal Flux Density

Faraday's Law:

NPRJ = VJN'toN'I(f / (Ae'~B)


In this particular design:

VIN = 385 Vdc(min)

tON = 4Jlsec

fXFMR = 100kHz

Ae = 3.1 cm2

LlB = .13 TesIa

Therefore :

construction technique, designers are faced withsome of the same difficulties with traditionallywound units. Integral numbers of secondary turns(without resorting to complex flux shifting tech-niques) still poses problems with multiple outputs.Tradeoffs and considerations will be highlighted inthe next section.

Planar Construction: Planar transformers areformed by series and/or parallel connections ofindividual planar windings. These windings aregenerally made from etched printed circuit boardmaterial for multiple turns per plane, or from astamped copper "lead frame" for a single, planarturn. Each of these planes is isolated from adjacentplanes by some form of insulation material. Typi-cally, the stamped copper turns are used for thehigher current applications such as low voltageoutputs. The multiple turn PC boards are commonlyconnected in series to form higher voltage andlower current windings like the transformer'sprimary .High voltage, V DE approved isolationbetween primary and secondary is achieved with apatented bobbin[2] structure as shown below.

Final Transformer Details The fmal transform-er design was an iterative process as with almost alltransformer designs. The total number of planarboards able to fit within the structure dictatedseveral details of the design, including turns ratioand number of primary turns. A 6 turn secondary(Ns = 6 T) was selected as optimal for this 48 V

output, and several PC boards were connected inparallel to handle the output current. The "winding"room available for the primary side and a roughestimate of the final primary current determined theexact fmal number of primary turns. A 32 turnprimary (Np = 32) would fit, while amply handling

the current. This resulted in an overall transformerturns ratio, N, of 32:6, or 5.33:1. While this mightbe slightly less than ideal, it will actually be neces-sary once the resonant inductor, needed to facilitateZero Voltage Transitions, is added to the circuit. Aswill be later described, this inductance adds a slightpenalty in the effective maximum duty cycle, thusrequiring the turns ratio to be reduced. Np = 32,Ns = 6, N = 5.33:1.

NPRJ = 385 .4.10-6 .1~ / (3.1Ocm2 ..13T)

NPRI = 38 turns (estimated)

Turns Ratio CalculationThe number of turns for each secondary winding

is calculated knowing the available volt-secondproduct on the primary winding and the desiredoutput voltage. In this application, the outputrectifier voltage is a small percentage of the 48 Voutput level and can be ignored in the turns ratiocalculation.

The exact transformer primary to secondary turnsratio (N) is derived from the following relationshipsused for any Buck derived converter:

VoUT = VIN(MIN)'DMAX / (NPRI/NsEC)

where DMAX is the maximum obtainable duty cycleof the converter which occurs at the minimum inputvoltage, VIN(MIN).

Substituting the turns ratio N = NPRI/NsEC into

the above equation and solving;

N = VIN(MIN)'DMAX / VoUT

N = (385 * 0.80) /48.5(typ) = 6.3 (estimate)

The secondary number of turns is straightfor-

ward:

NSEC = NpRI/N = 38/6.3 = 6.0 (estimate)

Planar Transformer Design

ConsiderationsDesign considerations are much different for

planar magnetics as opposed to conventionallywound transformers due to physical limitations.These are: total number of turns, turns ratio, andcurrent per winding. In all fairness to the planar


TOP "E" CORE

INSULATOR

112 SECONDARY

INSULATOR

INSULATOR

BOBBIN A

1/2 PRIMARY

INSULATOR

112 PRIMARY

BOBBIN B

INSULATOR

INSULATOR

112 SECONDARY

INSULATOR

BOTTOM "E" CORE

Fig 7. -Planar Transformer Construction

Lossless Switching RangeOne goal of this design is to accomplish Zero

Voltage Transitions when the output load is abovefifty percent of the full power rating. When the loaddrops below this amount, then ZVT is no longerobtained for the resonant left leg switch pair A andB. Switches C and D will undergo lossless switch-ing at loads below 50% because they are propelledby the constant output current and energy stored inthe output choke. At some point, however, theseswitches will also encounter switching loss at verylight loads, and this power level is easily calculated.So, while this design features fully lossless switch-ing above =50% of full load, it will have lossesbelow that level. This was a reasonable designcompromise, and the exact switch-over point can beadjusted by changing the resonant inductor value.

Resonant InductorThis design incorporates an inductor in series

with the transfonner primary to facilitate the loss-less transitions within the desired delay times.Further details and tradeoffs of accomplishing thisobjective are available in another topic in thisSeminar Manual[ll. This inductor will also programthe power stage dI/dt which softens the switchingtransitions and noise even further. The influencethis will have on the effective duty cycle must beconsidered since this erodes the full power transferportion of the conversion cycle. Also, a high valueof series inductance could ultimately effect thetransfonner turns ratio. This case could be consid-ered as extreme, but is possible with designs at-tempting to ZVT down to very light loads.

Power loss in the core was a concern in this200kHz inductor design due to the high voltageprimary .The few turns required to get the lowinductance value corresponds to a higher core fluxdensity during each switching transition. Ideally,this suggests the use of low loss, gapped ferritematerial or possibly low penneability magneticmaterial. Low profile is preferred to keep with thedesign guidelines, so total height shouldn't exceedthe main transfonner's 0.62 inch profile.

Transition DetailsA spreadsheet program was developed to analyze

the ZVT transition effects at various output loads,MOSFET choices and resonant inductor values.(See Figure 8.) Effects on both the "linear" rightleg and resonant left leg transitions were tabulatedalong with the critical minimum load currentrequired to facilitate lossless switching within theprogrammed delay time.

It was detennined that a 50 pH series inductancewas needed to achieve the lossless switching objec-tive above half load within the 250 nsec maximumdelay time. Note that this only applies to the leftleg resonant transition and not to the "linear" rightleg, separately programmed for a briefer (15Ons)delay time. The 50 pH inductor in conjunctionwith the IRF840 MOSFET capacitance, transfonnercapacitance, leakage inductance and 5.33:1 turnsratio facilitates ZVT down to 60% of full load, or6.3 Amps of output current. More inductance can


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be added, but this value works out reason- IPHASE S~IFT ZVT crwvF"TF" nF!;,(;N TEST 11 TEST 'I TI;ST .1ably well for the purpose of this designexample. The required energy storage is 156pJ at 2.5 A maximum, indicating a fairlysmall device can be used.

Note that this series inductance limits theprimary di/dt and therefore erodes the effec- ~tive maximum duty cycle. Power transfer ~~~~TS~6!~I;Stakes place during a smaller portion of the ~F~T ~~~UT CAPACITA~F "".. ("F'total switching cycle, which could require I«)SFET "do(",,' n '5 c (" , --

another iteration on the main transformer ~~~~ D~~~~ , ~~~t ~~,' n~~~.-(W\ Iturns ratio. This design procedure com- ~QjETIc-cQRE .LOSsEs -~(;~ .-.Imenced with an initial estimate of 85% and i

the 5.33:1 turns ratio. The spreadsheet re-sults indicate that the realizable maximum 1~~~~A~GN~¥Tz~~00~;,~~~~F (u~,duty cycle is about 86%, and therefore will ~~~~ p~7~~~ c~~~~~~~ ~~~~work fine. Had this not been the case, theeasiest way to resolve the situation would beto lower the switching frequency enough to .

yield the required maximum duty cycle.Another possibility is to take a turn or so offof the primary and recalculate the transitionanalysis. Adding series inductance to facili-

r ~~J~ i*;[I~~!,tate the transitions seems to be the preferredroute with moderate frequency converterdesigns. High frequency applications, those '67above 250 kHz may need to resort to other t=iftj-.i1i-~techniques to accomplish ZVT. ~,~~

-

Transition ComparisonThe spreadsheet analysis contains a Fig 8. -Transition Time Spreadsheet Results

wealth of detailed information about the transitions. ..Comparisons to using larger MOSPETs, different SIX switches requires more primary current toturns ratios, and resonant inductor values can be accomplish the transitions within the allotted transi-made. The three columns on the spreadsheet shown tion times. A larger series resonant inductor can beindicate trial designs using the same basic converter ~dded to stor~ the additional energy, but this willand transformer designs, but different size Impact the pnmary current slew rate. This, in turn,MOSPETs. Reviewing the columns, values are erodes the maximum effective duty cycle which

calculated for an IRF840 type (size 4) PET first,and IRFP450 (size 5) PET next, and finally for anIRFP460 (size 6) MOSPET.

The purpose of these examples is to be able toclearly distinguish the repercussions of using a largePET with this phase shifted technique to reduceconduction losses. The penalties paid for the slightincrease in overall efficiency are numerous. Thelarger output capacitance of the heftier size five and

160

~1-'tUzQ

2!1

1-inz~1-

3511 500 550400 450OUTPUT rowER (Watts)

Fig 9. -Transition Times vs. Load


suggests a lower switching frequency, and possiblyan increase in the transformer turns ratio. There isnothing wrong with taking this tack, provided thatthe overall power density is not impacted. In fact,this may be a better approach for very high powerapplications. The comparison is presented to dem-onstrate the subtle and obvious tradeoffs whichoccur during the design process of the phase shiftedconverter. Numerous other parameters, for exampleswitching frequency, can be quickly evaluated andcompared using the spreadsheet format.

Spreadsheet formulae are given in Appendix II

Gate Drive Circuit DesignThe destiny of "old" bipolar transistor power

supply design was typically determined by the basedrive circuitry. While today's families of powerMOSFETs have greatly simplified this section ofthe design, the challenge of designing an optimalgate drive circuit should not be underestimated.High frequency drives allow no provision forleakage inductance. The gate transitions must besharp, ringing and overshoot must be minimal.

Standard, off-the-shelf PE-64972 "500kHz" gatedrive transformers from Pulse Engineering wereused in the fIrst round of high frequency experi-ments, but not the final prototype. As the convert-er's switching frequency was lowered from 600kHz to the fmal 200 kHz to accommodate corelosses, the gate drive transformer maximum volt-second product was exceeded. Nevertheless, theyperformed very well above 350 kHz and deliveredclean drive signals to the gates. Design details ofthe transformers fabricated for this example areincluded.

Compared to conventional switching techniques,phase shifting offers a few significant benefits andreduces the gate drive complexity .First, all switch-es are continually running at approximately fiftypercent (50%) duty cycle, all of the time. Also, theupper and lower switches within one leg are alwaysdriven out of phase, at the same 50/50 duty cycle.High side switches do not experience the wide volt-second product variations as in conventional PWMdesigns with variable duty cycles. Therefore, theupper switches have greatly simplified transformercoupled gate drives and will not require the back-

to-back zener diodes or complex clamp circuitstypical of a traditional full bridge. The 50/50percent duty cycle drive makes it easy to addanother winding on the core and obtain the lowerswitch gate drive with minimal effort. Adding thiswinding is a small expense, but worth considerationdue to potential power to signal ground loops andvoltage drops commonly found in a high powerconverter.

Another benefit of this phase shifted controltechnique is the lack of "Miller" effects during thezero voltage transitions. The typical gate voltageplateau at around 8 V is gone since the switch isalready positioned with zero voltage across it. drainto source. The associated ringing of the gate voltagewhen confronting the "Miller" effects is likewisegone. Power loss in the switch due to the gateringing is also eliminated. Finally, the IC drivingthe four gates is spared from a good percentage ofthe total gate charge (Qg), so IC power dissipationis even reduced. This is only true for the ZVTportion of operation above 60% of full load, and isnot applicable at light loads when the converter isoperating in a lossier switching mode.

Only the two upper switches of this converterneed high voltage (500 V) isolation from theUC3875 driver outputs. The two lower side PETscan be driven from the IC without galvanic isola-tion. However, the decision to transformer coupleall four gate drive signals was made based onseveral factors. First, ideal magnetic coupling wasneeded to insure that the exact programmed delaytimes were delivered intact across the isolationbarrier. This suggested using three windings on atoriodal core wound tri-filar for best results. Keep-ing these as identical as possible required using thesame insulated wire for all three windings, so eachwas electrically isolated from the core, and eachother. Two transformers are used, each with threetri-filar insulated windings.

The toroid core selected for the gate driveapplication is a Magnetics Incol]JOrated 41206- TC,made using the company's low loss "P" ferritematerial. Physical dimensions are shown in theaccompanying Figure. Insulated, small diameterwire can be used due to the net low dc currentsinvolved. This prototype incol]JOrated standard


~ .475~ L1A.i' I

.t -~ 70:/.210

3 ..t

blocking capacitor accommodates any volt-secondmismatching of the drivers. Eight Schottky clampdiodes are required, two per UC3875 output, toprotect the IC against any voltage excursions belowground or above the collector supply voltage, V c.These diodes MUST be Schottky types in order toeffectively clamp, and a 2 A peak minimum ratingis recommended. Details are shown in Figure 11.

VGS5V/Div

VoUT A

Fig 12. Gate Drive Waveforms

"wire-wrap" wire, A WG#30. KYNAR insulationprovides 1000 V isolation for each winding, morethan adequate for even high input voltage IGBTdesigns. Different color sleeving can be used foreach of the three windings to simplify fabrication.The three wires can be twisted together first, thenwound for possibly better magnetic coupling,although this was not done on the prototype.Twelve turns will be needed for each winding tokeep core losses within reason and voltage droop toa minimum. Later in the development cycle, Coil-craft (see SUPPLIER LIST) was contacted todiscuss making this transformer a standard product.As a result, a similar 10:10:10 turn gate drivetransformer is being made available from Coilcraftas their part number Q3903-A. It features 500 Vrmsisolation (minimum) for each winding and demon-strates better magnetic coupling than the author'shandmade prototypes.

Each gate transformer is driven in a bipolartechnique and is connected between the two appli-cable UC3875 high current outputs. The 12 Vsupply rail and a 10 Ohm series resistor limits thepeak current to approximately 1 Amp. A series dc


Output Filter Section

Output Inductor: The output inductor selectionwas kept as simple as possible by incorporating anstandard, low cost wound toroid. The preregulateddc input supply from the Power Factor Correctioncircuit maintains almost a constant duty cycle nearthe maximum of 85%. Little inductance is needed,even in this 48 V output application due to the briefoff-time incurred with high switching frequency.Slight modulation is required to overcome theincremental conduction (I*R) losses and variationsin input bulk supply voltage.

LoUT = VOUT tOFF / MOUT

LoUT = 48.8 .10-6/ I.I = 44 pH

Once again, an off-the-shelf Pulse Engineeringpart, a high current toroidal inductor model# PE-51511 was used. This is a swinging choke featuringa two-to-one change in inductance, and specified at85.5 pH without a dc load. At its 10 A ratedcurrent. the inductance decays to 43 pH which willdouble the ripple current to about 1.1 A peak topeak. This choke was selected for its full loadparameters and the fact that it swings is a bonus.Use of this part in this 200 kHz, 10.5 A applicationexceeds the manufacturers intended operating rangeby 0.5 A. This shortcut was taken to simplifybreadboarding the entire unit. Designers shouldfurther evaluate this as well as other options.Gapped center leg, low profile, low loss ferrite coregeometries deserve consideration.

Output Capacitance: Maintaining the 100 mVmaximum specification for peak to peak ripplevoltage requires low ESL/ESR capacitors as men-tioned in the Design Overview. With 1.1 A ripplecurrent at 200kHz, the acceptable ripple voltagecomponent will be 25 m V.

high frequency parasitic spikes caused by theswitching b"ansitions and physical layout. All partsare rated at 63 V dc and operated well within theirripple cUITent ratings.

UC3875 Phase Shifted Control CircuitryProgramming of the individual functions of the

UC3875 controller and UCI9432 precision refer-ence and optocoupler driver will be detailed in thissection. The control circuit schematic is shown inFigure 13 for reference, and all IC pinouts refer tothe 20 lead through-hole package.

Control Circuit Programming Outline:

A. Oscillator FrequencyB. RAMP and SLOPE functionsC. Error Amplifier and Soft StartD. Current Limit ProtectionE. Delay SectionF. High Current OutputsG. Supply Connections

A. Typically, the control circuit design beginswith the IC's oscillator section. Frequency isprogrammed at the FREQuency SET pin (pin 16)with a parallel resistor (R9) capacitor (C9) fromthis pin to ground. According to the datasheetcurves, a 43K resistor and 470 pF capacitor areneeded for the chosen switching frequency.

B. The IC will be used in conventional duty cycle(voltage mode) control without feed forward.Potential users of this technique are strongly en-couraged to continue experimention with voltagefeed forward, standard current mode control andaverage current mode control.

To perform the phase shifted modulation, the ICcompares the error amplifier output (pin 2) to theRAMP input (pin 19). To facilitate direct duty cyclecontrol the RAMP input requires a sawtooth wave-form which is obtainable using the constant currentsource of the IC's SLOPE (pin 18) feature. ThecUITent programmed by Resistor R1 from SLOPE toVREF is internally mirrored to the RAMP pin, andonly a capacitor from RAMP to ground (C5) isneeded. These components are selected to give afull amplitude (3.8 V) signal within the oscillator's5 psec total period. A 75K SLOPE resistor and75pF RAMP capacitor are used.

COUT(min) = l(p-p) / (8. !cONV.AVOUT)

COUT(min) = 1.1 / (8.200103..025V) = 25 pF

Two 15 pF low ESR/ESL elecb"olytic capacitorsand two 1 pF ceramic multilayer capacitors are allplaced in parallel to filter the output voltage. Theelecb"olytics handle the bulk of the charge storagerequirements whereas the ceramic units filter the


c. The error amplifi-er CEtA) non-invertingdc input (EtA+) is bestprogrammed near thecenter of its SV com-mon mode input volt-age range, and 3V isused in this design.Two series resistors,R2 (2K) and R3 (3K)divide the SV reference

(Vret) voltage (pin I)to 3V and feed theEtA noninverting inputat pin 4. The referencealso is supplied to the

optocoupler's (02)diode to power thefeedback signal. Thisfeeds two series resis-tors, R4 (lK) and RS(3K) to develop thenominal 3V, closed

~Time Deley A~ A

GND

L

Lj Time Delay B ~ B

0.

~Tlme Delay C~ ::!b-m OUT CI

I I T'-- n-'--- n I k

--,~D~laL~r

..r---~ OUT D

I DELAY

i mSET

C-D

R11VIN

REFERENCE GATEInler~al GENERA TOR

BiasSV 1 VREF

~GND

SOFT- mSTART ~

-(O300JLA-011

OverCurrent

&Soft-Start

Logic

CIS(+) ~

2.5V .--

L

---CJ:=<I;=~

Fig 14. -UC3875 Block Diagram


loop feedback signal. The centerpoint of theseresistors is input to the error amplifier inverting(EIA-) input at pin 3.

Compensation around the El A is a series R/Cnetwork consisting ofR10 (150K) and C10 (O.lpF).These exact values deliberately keep the amplifierlow, as most of the compensation will be done onthe secondary side before the optocoupler. Furtherdetails about optimization are presented in thefeedback section.

D. Two forms of overcurrent protection arepossible with the UC3875 controller; a non-latchingshutdown with a full soft start cycle restart or acompletely latched shutdown. The current senseinput (CIS+, pin 5) is compared to a 2.5 V internalthreshold and triggers a 300 uA current sink on thesoft start (SIS, pin 6) capacitor to ground, holdingthe outputs low. The soft start capacitor voltage isalso monitored to detect which mode of protectionhas been programmed. It must first drop below the300 m V lower threshold before the current sink isreleased. Latched protection is obtained by external-Iy supplying more than 300 uA of pull up currentto the soft start capacitor thus not allowing dis-charge to the lower threshold. Non-latching opera-tion, often called "hiccup" requires no external pullup since the IC contains an internal 9 uA source atthis node. A full soft start time constant expiresbefore operation recommences as the capacitor isused for the timing delay function instead of softstart during this time.

E. The ZVT transition delay is programmed atthe DELAY SET A-B (pin 15) and the DELSYSET C-D (pin 7) inputs. A resistor to ground fromeach of these pins separately programs the CUrfentused to charge internal capacitors used to set thedelay. Note that each leg delay time can be individ-ually programmed which permits higher maximumduty cycles in high frequency converters thanotherwise programming all delays for the worst casemaximum of the right leg. The resistors (R7, R8)programming the DELA Y inputs should be ade-quately bypassed with capacitors (C7, C8) toprevent noise spikes from modulating the delayfunctions.

F. Four 2 Amp high speed totem pole outputswithin the UC3875 insure excellent gate drives tothe full bridge switches. OUT A (pin 14) and OUTB (pin 13) deliver the upper and lower left legdrive signals respectively, whereas OUT C (pin 9)and OUT D (pin 8) are for the respective left leggate drives. Note that all outputs are with respect toIC ground and that the two "high side" switchdrives (OUT A and OUT C) must always betransformer coupled or level shifted. Outputs B andD, the two lower switches of the full bridge do notrequire isolation from the power stage. Schottkydiodes are required to protect each output frombeing forced beyond the supply rails, as describedin the gate drive section of this topic.

G. A 12 V bias is supplied to the VIN (pin 11)and Vc (pin 10) connections from the PFC preregu-lator stage. These IC power connections should bewell bypassed and filtered for best performance,likewise for the 5V reference (pin 1). There are twoseparate returns paths within the IC, a powerground (pWR GND pinl2) for the high currentoutput stages, and a signal ground (GND pin 20)connection for the analog circuitry .Note: Thesetwo grounds must be at the same electrical potentialand work best when tied together directly at the ICpins. This is also where the bypass capacitor con-nections should be made. Separate signal and powerground "planes" are incorporated in this prototypeto keep noise from each localized, but are connect-ed together at the IC ground pins.

Isolated Output Voltage FeedbackNo great efforts were attempted to optimize the

voltage feedback path for this design example. Asimple 5000 V dc isolating optocoupler provides theprimary side UC3875 error amplifier with theoutput voltage feedback information. A precisionreference and optocoupler driver IC, the UnitrodeUC39432 was incorporated for excellent dc outputvoltage stability and regulation. Power for thiscircuitry is derived from the 48 V output for sim-plicity, and a zener diode provides some degree ofregulation. The loop was not optimized for thisapplication as the main goal was to evaluate thephase shifted power stage. Further developmentefforts are needed.


Prototype AssemblyThis 500 Watt converter was built on standard

single sided PC board material using one etchedboard (as shown) primarily for the control andanother "experimenter" type PC board for thepower stage assembly. A base plate was simulatedby using the flat sides of aluminum heat sinkextrusions supplied by AA VID Engineering, model#61875. Each piece has a thermal rating of2.7°C/W for a three inch length using naturalconvection cooling in free air.

Fig 15. -Heat Sink Dimensions Fig 16. -Mechanical Assembly

MOSPETs as this increasing loss is primarilyconduction loss. Be aware that this may also requirelowering the switching frequency or increasing thecirculating current which will reduce the benefits ofswitching to larger PETs in the first place. Thespreadsheet program will help designers fine tunethe tradeoffs involved. Peak efficiency was over93.5% with loads between 325 watts and 450 watts,and just below 93% at full power output (500 W).

Performance EvaluationThe assembled prototype was evaluated over it's

intended operating ranges and various parameterswere compared against the initial specifications. The500 Watt power supply meets a majority of theintended goals including efficiency, power density,output ripple, line and load regulation. The unit didfall slightly short of being able to ZVT down to50% of full load -only about 60% was achieved.This was a tradeoff highlighted in the TransitionAnalysis section. So while some increase in powerloss was experienced near half load and below, thetotal losses decreased due to the lower current.Cooling and heat sinks should still be designed forfull load operation which is the worst case forpower loss.

A graph of the measured converter efficiency isshown in Figure 17 for loads above 300 watts.Efficiency remains above 93% in this operatingregion, but shows a sign of tailing off at the upperend. This could be improved by selecting larger

UNITRODE CORPORATION4-14

with input line variations. Three measurements weremade for this converter at high power and areshown in Figure 19.

93.6J~i~~

~ 93,4'

I

~ 93.2.wuu: 93 .LLW

~ U~i~~

~~~utl = 51~ W92,8'

c---360 370 390 390

INPUT VaL T AGE -VDC

Fig 19. -Efficiency vs. Input Voltage

The results indicate that efficiency is higher withthe lower inputs and reduces with increasing inputvoltage. Highest efficiency is achieved at 360 V dc,coITesponding to the lowest input voltage necessaryto maintain the regulated output voltage. For thisdesign, inputs any lower would cause the outputvoltage to sag since maximum duty cycle has beenreached. It is conceivable to actively adjust the PFCpreregulator output voltage for highest efficiency ofthe phase shifted converter. This is possible for allbut the highest input line conditions, for example,above about 250 Vac in. Should the ac input mainsget above this point, the PFC output voltage can beraised from 360 V nominal to 385 V, or so. A netincrease of around 0.2% efficiency ( 1 Watt ) is allthat is to be gained, and possibly not worth theadditional complexity for this application.

Full load operational primary voltages andcurrent for one complete switching period can beobserved in Figure 20. Note that this photo, andothers, was taken with a 150 MHz gain-bandwidthoscilloscope at 100 Volts per division verticalcalibration. The horizontal time base in Figure 20(679 nanoseconds/division) is different from mostof the others which use 1 microsecond per division,only to fit one complete period on the screen. Thisphoto shows how clear the ZVT waveforms are bythe absence ringing and overshoot. A similar photofor two switching periods is shown in Figure 21.

One of the full cUITent right leg "linear" transi-tions is shown in detail in Figure 22 for clarity. Theexact measured transition time corresponds well to

The effects of lossy, non-ZVT operation areclearly demonstrated by the efficiency measure-ments below 250 watts. Here, the primary circulat-ing current during the freewheeling interval is toolow to discharge the left leg switches output capaci-tance to zero prior to turn-<>n, and switching loss isincurred. At light loads, the same will hold true forthe right (linear) leg switches which become unableto ZVT below about 6 A. Note that this point isgenerally lower than for the left leg's fully resonanttransition, which loses its lossless transitions atabout 6.5 A output current.

Total power loss versus load is shown in Figure18 for reference. This demonstrates that non-ZVToperation is not the worst case for power dissipationin this design, and that full load is still the worstcase. Therefore, operation under this lossy conditionis acceptable from a thermal standpoint since amplecooling has been provided for much more powerloss. Total losses range from about 20W at lightload to 4OW at full load. Heat sinks are selected forworst case power dissipation at full load, and thereis plenty of margin at light loads in spite of thelossy transitions.

fi)1::

[I

InIna-'ttw~

~

During normal operation with Zero Voltageswitching Transitions, efficiency should be some-what immune to changes in line voltage. This istrue to a point, however there are some line depen-dant losses. The duty cycle does have to vary tomaintain regulation. This changes the ratio ofswitch "on" to freewheeling times, and conductionlosses for each mode are different. Additionally, thepeak inverse rectifier voltages change with line onthe transformer's secondary, also. Therefore, oneshould expect some change in overall efficiency


load current continues to conduct until the primaryvoltage is reversed at the beginning of the nextswitching cycle. The output ripple voltage andtransformer secondary waveforms are also shown.There is a slight overshoot in the voltage waveformas conduction begins, and this is due to leakageinductance between the secondary windings. Asimple R/C snubber was used to control the ampli-tude of this, and no elaborate analysis of this is

presented.

VA100V/Div

IPRI

2A/Div

VB100V/Div

Fig 20. -One Switching Period IDoUT10A/Div

VA100V/Div

~VOUT100mV/Div

IPRI

2A/DivVSEC

SOV/Div

Fig 23. -Secondary Side WaveformsNon-Zero Voltage Transition wavefonns are

featured in Figure 24 for the primary voltage andcurrent at a 30 Watt (6%) load. Note that theprimary voltage starts its nonnallinear and resonanttransitions, but is then forced to the mil by thecontrol and drive circuitry .It is also clear thatenough energy was not stored in the tank to makethe transition occur by nonnal means. Note too, thatthe power loss is not as bad as it could have beensince the tank does drop the switch voltage signifi-cantly before turn-on. Spikes on the leading edge ofthe current wavefonn are caused by the outputsnubber circuit.

VB100V/Div

Fig 21. -Two Switching Periods

the spreadsheet value, and any difference is dtJe tothe approximated 8/3 Coss multiplier factor.[!]

The secondary side waveforms are shown inFigure 23. The top trace shows the output rectifiercurrent at 10 Amps per division. Notice how thisdiffers from a conventional full bridge. Due to thefinite voltage drops in the primary during free-wheeling intervals, the primary current does NOTdivide evenly between both diodes. In a phaseshifted converter, the diode which was conducting

Ip100mA/DivVB

SOV/Div

VA100V/Div

Fig 24. -Non-ZVS, "Hard" SwitchingFig 22. -Right Leg Transition


Performance ComparisonThis 500 Watt evaluation unit was compared to

other phase shifted PWM converters presented byvarious authors over the past few years. This is notan "apples-to-apples" comparison due to the differ-ent switching frequencies, input and output voltagesand power levels, but does provide proof of thehigh efficiency conversion. Shown is a brief list ofthe other phase shifted PWM designs and results.

ConclusionsThis design review presented a typical applica-

tion for the fixed frequency, phase shifted ZVTswitchmode technique. All evidence indicates thatthere is no reason in the future to intentionallydesign a conventional, non-phase shifted full bridgecircuit. Efficiency is higher, and noise is significant-ly lower throughout the converter. Even the slightpenalty incurred during non-ZVT operation is lessthat the best of the conventional full bridge. Deviceparasitics are fully incorporated into the design toperform lossless switching as opposed to the contin-ual combat found with traditional switching. Thisdesign example serves as an additional technicalreference in support of the phase shifted PWMtechnique. Also, a working prototype can be madeusing many "off-the-shelf' components, readilyavailable to power supply designers, with minimaldesign effort.

SummaryThis 500 Watt Design Review demon-

sb"ates only one of a vast number of possi-ble applications for this switching tech-nique. It is equally applicable at powerlevels both above and below 1!2 KW,depending on the circumstances and projectgoals. Higher output power and higherfrequency operation need to be furtherexplored, although the results should endup quite similar to this benchmark example.Needless to say, much higher power densi-ties than today's off-line kilowatt unit stan-dards are attainable.

Modular power supplies below 500 wattscan also benefit from the phase shifted

switching technique. Although commonlyruled out at 200 or 300 W, use of this full bridgeconverter should be exploited. Couple the attributesof high efficiency conversion with a very highswitching frequency and an exb"emely dense,modular converter is possible, despite the additionalcomplexity of having four switches. Transformerutilization is optimal, output choke volume isminimal. While first impressions of this techniquemay lean towards higher power applications, de-signers are encouraged to consider it also for powerlevels of a few hundred Watts.

The phase shifted, Zero Voltage Transition PWMtechnique successfully combines the attributes offixed frequency conversion, lossless switchingtransitions and high efficiency operation.

Viva ZVT


AcknowledgementsSpecial thanks to Alex Estrov of Multisource

Technology for his technical assistance and quickturnaround of the prototypes.

Thanks also to Bob Mammano for his encourage-ment to prove that this technique really does workas claimed, and John O'Connor for his support.

Supplier List

AA VID Engineering, 1 KooI Pad1, Box 400,

Laconia , N .H. (USA)

Phone # 1-603-524-4443

Coilcraft, 1102 Silver Lake Road, Cary , ILL. 600 13

(USA)Phone # 1-708-639-6400, FAX # 1-708-639-1469

Multisource Technology Corp., 393 Totten PondRd, Waltham, MASS. 02154 (USA) Phone # 1-617-890-1787, FAX # 1-617-890-8011

Pulse Engineering, P.O. Box 12235, San Diego,CA. 92112 (USA)Phone # 1-619-268-2400, FAX # 1-619-268-2515

Signal Transfonner Co. Inc., 500 Bayview Ave.,Inwood, N.Y. 11696 (USA)Phone # 1-516-239-5777, FAX # 1-516-239-7208

References

[1] Andreycak, W., "Designing a Phase ShiftedZVT Power Converter", Unitrode PowerSupply Design Seminar Manual SEM-900,1993

[2] Estrov, A., "Low-profile Planar Transformerfor Use in Off-line Switching Power Sup-plies", United States Patent # 5 ,010,314, April

23,1991

[3] Steigerwatd et at, "Full-Bridge LosslessSwitching Converter", United States Patent #4,864,479, Sept. 5, 1989

[4] LoCascio, J., Klein, J. and Natbant,M.K., "ANew Phase Modulation/Soft Switching ICController", High Frequency Power Confer-ence, 1991, Toronto

[5] Chen,Q., Lofti,A. and Lee,F.C., "DesignTrade-offs in 5V Output Off-Line ZVS-PWMConverters", Proceedings of the InternationalTelecommunications Energy Conference,Kyoto, Japan, 1991

[6] DalaI, Dhavat B.; " A 500 kHz Multi-output

Converter with Zero Voltage Switching",IEEE 1990

[7] Chen, Kerning and Stuart, T.A., "A 1.5kW,200kHz DC-DC Converter Optimized forIGBTs", High Frequency Power Conference1991, Toronto

[8] Mweene, L., Wright, C. and Schlecht,M., " A

lkW, 500kHz Front-End Converter for aDistributed Power Supply System", IEEE,1989 #CH2719-3/89/0000-0423

[9] Sabate' ).A., Vlatkovic',V., Ridley,R.B.,Lee,F.C. and Cho,B.H.; "Design Considerationfor High-Voltage, High Power, Full Bridge,Zero- Voltage-Switched PWM Converter" ,IEEE APEC, 1990

[10] Henze, C.P., "Full Bridge DC-DC Converterwith Zero Voltage Resonant TransitionSwitching and Immersion Cooling", IEEEAPEC, 1992

UNITRODE CORPORATION4-18

Appendix I --UC3875 Full Bridge Phase Shifted Converter

MA TERIALS LIST

CAPACITORS RESISTORS

All are 1/2 Watt, 1%, Metal Filmunless indicated

All are 20 VDC Ceramic Monolithic orMultilayer unless indicated.

R1 75K

R2 2K

R3 3K

R4 470 Ohm

R5 3K

R6 100 Ohm

R7.8 6.8K

R9 43K

R10 150K

R11.12 10 Ohm

R13 20 Ohm

R14-17 10KR18 3.6K.1 W

R19 36KR20 1K

R21 TBD

R22 TBD

R23 110 Ohms- 5W Carbon

C1 1 uFC2 47 uF -25V ElectrolyticC3 1 uFC4 1 uFC5 75 pF- 16V PolystyreneC6 0.001 uFC7,8 0.01 uFC9 470 pFC10 0.1 uFC11 1 uF -450VDC PolyC12 47uF- 450VDC ElectrolyticC13 1.2uF -450 VDC PolyC14 1uF-100VDCC15,16 220uF- 63VDC ElectroliticC17 TBDC18 1 uFC19 22 uF -25 VDC ElectroliticC20 1 uFC21 2.7 nF-200V Poly-low ESL & ESR

TRANSFORMERS

T1 I Sense

T2,3 Gate Drivers

T4 Main XFMR

DIODES

D1-8 1 N5820 3A-20V SchottkyD9-12 1N4148D13 12V 3W ZenerD14,15 15A-200V Fast Recovery MOSFET TRANSISTORS

QA-D IRF840 NMOSINDUCTORS

L 1 47uH-3A

L2 100uH-15A

INTEGRATED CIRCUITS

U1 UC3875 PWMU2 Opto CouplerU3 UC19432


Appendix II --Excel Spreadsheet Formulae

A

I 1 IPHASE SH I FT ZVT C~VERTER [)!'~ I ~

~~

j !i m;.~~~ ~~~~~ ~ii~cf~~r";~ I!:"" -

~

*


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