design rules for photonic packaging - · pdf filedesign rules for photonic packaging table of...

DESIGN RULES FOR PHOTONIC PACKAGING �1

DESIGN RULES FOR PHOTONIC PACKAGING

01 07/06/2016 First IssueR&D Manager

A. Vannucci

Optical and Packaging Engineer

A. Dedè

02 04/11/2016 Second IssueR&D Manager

A. Vannucci

Optical and Packaging Engineer

A. Alippi

ED DATE CHANGE NOTE APPRAISAL ORIGINATOR


Table of Contents

1. Updates 32. Introduction 4

2.1. Main photonic package capabilities 43. Thermal and thermo-mechanical management 5

3.1. Thermo-mechanical simulations and optimization 54. Linkra’s standard generic package 7

4.1. Chip layout specifications and requirements 74.2. Electrical Connections 84.3. Optical coupling 9

5. Customized standard package 116. Full customized package 117. Front and back-end electronics 12

�2


1. Updates

�3

RELEASE DATE CAUSE OF CHANGE

1 07/06/2016 First isuue

2 04/11/2016

Improvements and new capabilities:

• Quasi-planar vertical grating coupling

• Extension to greater chip dimension

• Update design rule for RF tracks


2. IntroductionThis document describes the features and constrains of the Linkra’s integrated photonic packages and packaging service. Linkra provides 3 types of packages, which will be described individually. The first is a standard generic package designed to be the “reference” in terms of packaging and scalable to production volume. This type of package allows the user to address the main physical environment of a Photonic Integrated Chip (PIC) i.e. optical, electrical, mechanical and thermal. Second series allows for some customization in the optical and electrical inputs/outputs as well as chips sizes at the cost of higher price and longer lead-time for small series. Of course you can also fully customize your package within the constraints of our production machines. For easier designing your PIC, the design rules for our standard (early prototyping) packages are integrated in the PhoeniX Optodesigner Software.

2.1. Main photonic package capabilities

Linkra provides package engineering, packaging process development (can be transferred to the customer for high volume packaging) and low-mid volume production.

For optimal function of the package devices we advise to make use of our mechanical, thermal, thermo-mechanic and electronic optimization, of which you can find more information below in the document.

�4

Optical

The optical alignment process is performed through an automated optical bench equipment able to perform the typical alignment routines such as raster, area and line scans, reading the power distribution and moving the chip and the fiber array to reach the corresponding maximum coupling position.

Mechanical Mechanical design and structural analysis of photonics components and modules (mechanical and thermal stress)

Electrical Analog and Digital design of PCB boards for photonic modules

DC to RF Active/passive design and analysis of components and modules up to 90 GHz

Thermal Thermal analysis and thermal management of packaged photonics modules

Testing Optical and electric up to 70 GHz, DWDM qualification test benches

Table 1: Main photonic package capabilities provided by Linkra.


3. Thermal and thermo-mechanical management Integrated photonic devices change behavior as a function of temperature and mechanical stress. From a more practical point of view, due to the presence of thermal gradients and thermal cross-talks induced by on-chip lasers and other active optical elements, heaters and electronic components (both on chip and nearby), the behavior of the photonic chip may be altered and performances of the overall system compromised. Further, thermal gradients induce also mechanical stresses that can be a critical issue for example thinking of fiber coupling, MZI cavity length,… . In order to limit these unwanted variations all our standard packages come with a thermal management system based on a thermo-electric cooler (TEC) and thermistor for temperature stabilization. In the standard generic package TEC and thermistor are well defined. In the other packages these can be modified or even removed. Based on consideration above, it is therefore mandatory to use tools able to study and manage issues like thermal and thermal-stress in a multi-physical environment.

3.1. Thermo-mechanical simulations and optimization In order to address in the proper way issue like thermal management and mechanical stress (generated by thermal gradients), Linkra has the capabilities to study and optimize these fields through a finite element simulator.

�5

Figure 1: Linkra’s clean room and related machines/devices.


PICs are surrounded by lots of heat sources inside (TIA, TEC, control electronics, ..) and outside the package (power supply, ASIC, laser driver, more TECs, ..). Some heat sources are even on the PIC (SOA, PD, Modulator, laser, ..). These heat sources cause deformations due to the presence of temperature gradients all along the package. These variations turn in mechanical stress and could affect both PIC functionalities and package integrity. Moreover, the optical properties of the PIC will vary with temperature and stress causing a direct worsening of entire assembly performance. In order to optimize the overall performance of your system (including price and dimensions) we offer thermo-mechanical modeling of both PIC, package and other componets. Through these models we can assist in modifying the PIC layout such that heat sources have minimal negative influence to critical components on the PIC. Similar we optimize TEC, Thermistor position(s) and package layout. In demanding cases we can even optimize the layout of the surrounding electronics.

�6

Figure 2: Temperature distribution achieved through thermal simulation.

Figure 3: Displacement distribution achieved through thermal-stress simulation.


4. Linkra’s standard generic package Whilst developing a photonic system, typically first a proof of concept is required. Photonic packaging, using a custom package design, is relatively expensive for small series as all components will have to be designed and produced in small quantities. In order to enable an easy and fast PIC’s testing at lower cost we provide some standard packages. These packages have limited choice in features, i.e. max 25GHz, max amount of electric contacts, limited amount of PIC dimensions will fit, configuration of the PIC has to follow electrical and optical I/O layout rules. This chapter describes these design rules, for more or complete customized packages see following chapters. For PICs packaging, Linkra provides a standard 52 pin package. This package comes standard with:

• A “gold box” (kovar) with dimensions of 50 x 35 x 8.6 mm (L x W x T) is used as housing for all the components

• A TEC of 4.5 Watt • An NTC Thermistor 10KΩ @25°C • RF ports: 0, 2 or 4 (up to 25 GHz) • Two rows of 26 DC pins (of which 2 for TEC and 2 for Thermistor and max

2x24 for the PIC).

4.1. Chip layout specifications and requirementsIn order to be able to fit in the standard package, the PIC needs to be designed according some specific design rules. Optical and Electrical connections are not permitted on the same side of the PIC. Looking from a chip top view (see Figure 5), the right edge of the PIC is reserved for optical connections, the left side for RF connections, instead the upper and lower edges are reserved for DC electrical-connections.

�7

Figure 4: Linkra’s 52 pin standard package.


The package can accommodate chips of different technological platform basically InP, SOI, SiN. The standard chip dimension is 4x6 mm (width x length) for both straight and angled chip orientation (when waveguides are fabricated with slightly angled end-facets to limit back-reflections from the coupling surfaces).

In principle, chips of dimension up to 6.3 mm width and 9.8 mm length can be accomodate in Linkra’s 52 pin standard package, but with some limitations (for angled optical coupling dimensions are less, please contact us). With larger chips, electrical connections have to be properly managed, in particular, RF signaling come not mandatory and depends on the particular chip dimension (position and pitch of between tracks may change from design rule specification). Regarding DC pad, they should be placed starting from right edge of the chip, according to its length the pitch should be 250 µm or if needed a multiplication of it. Deviations from this will be treated as customization and will need to be checked for feasibility by us before finalizing your design. Please contact us before designing the chip to meet our packaging requirements.

4.2. Electrical ConnectionsStandard electrical connections between PIC and alumina carrier interposer are made using wire-bonding. To ensure reproducible and high-quality wire-bonding, the location and pitch of the bond-pads on the PIC must be controlled. • DC connections:

Regarding DC connections, we recommend square bond-pads with a size between 80-100 µm, separated by a pitch of 250 µm (center to center). The resulting bond-pad array should be centered with respect to the PIC and aligned along the upper and lower edges (max 24 pads for each side). Please keep a minimum pad distance of 50 µm from the north, south and west chip facets. Instead, regarding the east side (optical I/O interface), there will

�8

width

length

Figure 5: Example mask layout.


be a possibile coverage with AR coating and so a minimum pad distance of 200 µm from the facet would be better to avoid bad electrical contact. Please check with your foundry for further and reliable information.

• RF connections: As of RF signaling, max 4 RF signal tracks are allowed on the left side. A symmetric geometry is a must specially for higher frequencies, we therefore advice to use (0), 2 or 4 RF ports symmetrically centered with respect to the edge of the chip. At the output facet of the PIC, the pitch between the

center of two adjacent signal tracks depends on the line type configuration, the required values are 350 µm for micro-strip and 500 µm for coplanar. To avoid the crossing of wire-bonds, users must ensure that the “order” of RF bond-pads on the PIC coincides with the order of the RF connectors on the outside of the package, in case there is no ground on the

backside of the PIC, each RF track need to be sided by two ground tracks (one left, one right). Thus, in case of two RF signal tracks: grnd-sign-grnd-grnd-sig-grnd. See picture above for the configuration of each grnd-sig-grnd triplet. Grounds (of different signals) should not overlap and therefor the 500 µm signal pitch is recommended for coplanar waveguides.

4.3. Optical couplingBoth edge-coupling and quasi-planar vertical grating-coupling are feasible technique in Linkra’s 52 pin standard package. Some remarks, specifications and design rules are hereafter summarized. To date passive alignments are not possible as optical losses will be too high. Therefore, an active optical alignment is mandatory. Single waveguides or the outer channels of a fiber array need to be dynamically monitored by external photodiodes (PD) exploiting integrated sources on-chip (laser/SOA), or acquiring the photocurrent generated by integrated PD on-chip. Operating instructions for PDs, lasers and SOAs need to be provided. Alternative, for fiber array only, is shunting the outer waveguide to be aligned. Both standard/lensed (SM) and polarization maintained (PM) fibers are feasible. Three different optical coupling technique are feasible with Linkra’s 52 pin standard package.

• Edge-Coupling with individual fibers:

�9


Standard package allows for both straight and angled waveguide. A maximum of 4 SSM (lensed) fibers can be independently packaged and the required minimum pitch between adjacent waveguide is 500 µm for straight waveguides and 544 µm for angled waveguides (7 degrees).

• Edge-Coupling with fiber array: Packaging with fiber arrays come standard with the following combination of channel/pitch: 4 Ch/both 127 and 250 µm, 8 Ch/both 127 and 250 µm. Fiber array with more than 12 (16 or 64) channels can be packaged as well through minor package modifications, please contact us for further information. The waveguides must end straight at the end of the chip’s facet in order to guarantee the lower coupling loss as possibile (for angled waveguides contact us first to evaluate if this is feasible). In addition, the edge should be polished. Please contact us, before designing the chip, in case this cannot be ensured by the foundry. Fiber array of SSMFs are taken into account as standard component. Regarding SOI, please be sure of design your SiP chip with Mode-adapters/Inverted tapers in order to allow the best coupling as possibile. Solution with lensed fiber array are possible but do not fit in the Linkra’s standard package, so in case of this type of requirement please contact us for one of our other solutions.

• Grating-coupling (quasi-planar) with fiber array: Especially for Si-Photonics, the most common optical-coupling schemes usually involve grating-couplers (GCs) because they offer relaxed alignment tolerances compared to edge-coupling. We recommend the quasi-planar geometry (see Figure 6), because it offers better mechanical stability, and a lower profile packaged PIC. The optical-mode should be incident on the GC at the correct angle-of-incidence (typically 8deg or 10deg). The following design rules should be followed:

• The GC array should be arranged in straight line, parallel to the edge of the PIC-die and placed at least 1mm from its edge

• The first and last channels of the GC array should be connected to form an optical-shunt to be used for optical alignment, or connected to an on-chip integrated source or PD.

When choosing the number of channels needed for their PIC, users should account for the two channels needed for the optical-shunt. A pitch of 127 or 250 µm is allowed for both 4 and 8 channels, as well as edge-coupling, customized fiber arrays configuration can be taken into account (i.e. more fibers), ask for further information. To ensure a stable mechanical- and optical-connection of the epoxy-bond, it is important to have sufficient contact area between fiber array and PIC. As an epoxy flow from the target region onto the main body of the PIC will occur, we demand leaving an “exclusion zone” from 0.5 to 1 mm, around the grating array, in which no bond-pads are located, because it is liable to be covered by the epoxy flow.

�10


Photonic and electrical components within this area (besides GCs) will most probably change behavior due to the (different) refractive index of the glue. It is advised to have only GCs and waveguides in this area.

5. Customized standard packageLimited deviations from the standard PIC configuration are allowed. Strongest criterion is that it needs to still fit within the “gold box” standard, 50 x 35 x 8.6 mm (L x W x T). This allows for more configurations and features at limited extra cost. Think of deviations like: DC pads on the RF side (limit is the total of 48 DC pads), PIC size, multiple PIC’s in a package, pad pitch size and location over the edge, in package electronics (TIA, drivers, control, ..), in package micro optics (i.e. for combining/splitting beams within the package), hermetical sealing. We suggest you to do these modifications in close cooperation with us. This prevents disappointments later on (not possible, higher costs than expected, lower performance).

6. Full customized packageOf course you can also fully customize your package within the constraints of our production machines. As to date, not all combinations and configurations are possible, contact us for exact directions and latest developments, preferably before designing your chip.

�11

Figure 6: Vertical-Coupling technique and specifications.


7. Front and back-end electronicsAs Linkra has a long history in developing and producing (microwave-)electronics, we can design, develop and/or supply complete photonics modules for you i n c l u d i n g b a c k e n d a n d f r on t - e n d electronics, where needed even according to various spec/standards/regulations. Typical front-end in-package electronics are TIAs, modulator drivers, and laser controls.

�12

Platforms SOI, InP, Triplex, Polymer

Chip dimensions starting from 2x2 mm or even smaller

Fiber type

• MM, SM, PM

• lensed, cleaved • single, array • angled, straight

Coupling• Butt-coupling (micro lensed or facet to facet) • Vertical-coupling in pigtail geometry • PD arrays/ light source arrays

Front end electronics TIA’s, filters, controllers

Micro optics Beam combining, splitting, polarization adjustment,…

Thermal cooling passive and active

Hermetically sealing According to various specs/standards

Table 2: Lists of possibile modifications to the Linkra’s standard package.

Figure 7: Example of customized packages assembled by Linkra.

design rules for photonic packaging - · pdf filedesign rules for photonic packaging table of...

Documents