design setup fpr cpf

UNICAD 24 / May 2008

CENTRAL R & D Design Automation and Integrated Systems

CPF DESIGN SETUP

CPF DESIGN SETUP

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FTM-CCDS

Company ConfidentialCPF Design SETUP

May 2008

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TABLE OF CONTENTS0.1 Design Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

0.1.1 seed.cpf reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.1.2 seed.tcl reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80.1.3 seed.cpf example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170.1.4 seed.tcl example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21


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0.1 Design Setup

Design setup needs to be performed by the user to specify the design and library informationrequired for the generation of setup files for all the tools used in the flow. For this purpose, twofiles must be provided by the user in the SETUP directory:

A seed.cpf file in Cadence CPF format is used to define design name, power domains, nominal conditions, power modes, operating corners and analysis-views, and power rules.

A seed.tcl file in Tcl format is used in addition to the seed.cpf format to define power domain libraries and design global variables.

Examples of seed.cpf and seed.tcl are given at the end of this section.

0.1.1 seed.cpf reference

A seed.cpf file in Cadence CPF format is used for design setup. The purpose of this section isto describe the CPF statements and extensions expected in the seed.cpf file, for design setup(figure 1). Please refer to Cadence documentation for more information on CPF.


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Figure 1:CPF Terminology

0.1.1.1 Design Name

The CPF statement set_design is used to specify the current design name:

set_design

Where:

is the name of the current design name.

0.1.1.2 Power Domains

The CPF create_power_domain statement is used to specify the design power domains. At leastone default power domain must be defined.

create_power_domain [-default] -name

Where:


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is the name of the power domain to be specified.-default specifies the default power domain. At least one default powerdomain must be defined.

0.1.1.3 Nominal ConditionsThe CPF create_nominal_condition statement is used to specify the nominal conditions atwhich power domains can operate.

create_nominal_condition -name -voltage

Where:

is the nominal condition to be specified. is the voltage of the nominal condition.

0.1.1.4 Power ModesThe CPF create_power_mode statement is used to specify the design modes. The concept ofdesign mode includes both power and timing modes. Additional properties can be attached todesign modes with the power_mode_properties Tcl variable.

create_power_mode -name -domain_conditions {@ ...}

set power_mode_properties() { ...}

Where:

design mode to be specified.

@ specifies that in mode the condition for power domain is .

is the name of a property to be attached to the design mode.

is the value of the property

0.1.1.5 Operating CornersThe CPF create_operating_corner statement is used to specify operating corners. Additionalproperties can be attached to operating corners with the operating_corner_properties Tclvariable.


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create_operating_corner -name -process -voltage -temperature -librarySet

set operating_corner_properties(corner) {rc [mode ] [voltage2() ] ...}

Where:

is the operating corner to be specified.

-process, -voltage, -temperature are mandatory options to specifyoperating corner process, voltage and temperature.

is the name of a library set. Actual library paths are computedduring script generation, according to design library definitions in seed.tcland library packaging/vc.bbview files. In consequence, library sets MUSTNOT be defined in the seed.cpf.

is a mandatory parasitics corner to be attached to the operatingcorner. Allowed values are RCMIN, RCMAX, RCTYP.

is an optional mode to be attached to the operating corner. Allowedvalues are modes defined with create_power_mode.

name of a library with 2 voltages

value of the second voltage for library

0.1.1.6 Analysis Views

The CPF create_analysis_view statement is used to specify analysis views. Analysis views areused to generate different CAD tool execution runs, refered to as tasks.

create_analysis_view -name -mode \

-domain_corners {@}

Where:

is the name of the analysis view to be specified.

is the design mode corresponding to the analysis view.

@ tells that in analysis view the operatingcorner to be used for power domain is


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The analysis_view_scenarios Tcl variable is used to specify the category of task to beperformed foreach analysis views.

set analysis_view_scenarios() { ... }

Where:

is the name of the category of tasks to be generated. Allowedvalues task categories names are.

,... are the analysis views used for the generation of tasksin the category .

The analysis_view_properties Tcl variable is used to specify mapping of analysis viewsbetween different categories.

The following statement defines the analysis view of category EXTRACTION, to beused in the analysis view of category DELAY_CALCULATION.

set analysis_view_properies() {parasitics }

The following statement defines the analysis view of categoryDELAY_CALCULATION, to be used in the analysis view of categoryTIMING_ANALYSIS.

set analysis_view_properies() {delays }

Analysis View CategoriesIMPLEMENTATIONEXTRACTIONDELAY_CALCULATIONTIMING_ANALYSISPOWER_ANALYSISSTATIC_IRDROP_ANALYSISDYNAMIC_IRDROP_ANALYSISRAMPUP_ANALYSIS

Table 1: Analysis View Category names


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0.1.2 seed.tcl reference

In addition to the seed.cpf, a seed.tcl in Tcl format is used to define power domain libraries anddesign global variables.

The following tables describe the use of all the variables that can be found inside the seed.tclfile:

Design Structure Description:

Variable name ValueG_DESIGNS Current design name.

G_DESIGN_TYPE Defines the type of the current design. top or block.

G_TECHNO Technology name, in lower case

G_LIBRARIES List of library names used by the designs.

G_PHYSICAL_LIBRARIES List of additional libraries to be used for assem-bly of the complete layout.

G_BUMP_LIBRARIES List of bump libraries, for flip-chip designs.

G_BLOCK_REFERENCE_LIBRARIES()

Obsolete

G_POWER_DOMAIN_LIBRARIES()

List of libraries used in power domain .

G_BLOCKINSTANCE() This variable is used to describe the design hier-archy. The hierarchy is described by an array whose index contains the sub-block instance path and whose value contains the sub-block master name.

Table 2: Design structure related variables

Variable name ValueG_FLIP_CHIP Specifies a flip-chip design.

G_MULTISUPPLY Specifies a multisupply design.

Table 3: Design features related variables


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G_MULTISUPPLY_GROUP Non switchable group name. This group must be specified in the power ATTX with a given area.

Variable name ValueG_OPCOND_LIBRARY Library name to be used as reference for operating

condition definitions.

G_OPCOND_NAME() Obsolete

G_LIBRARY_OPCOND_NAME(:)

This variable can be used when an operating condi-tion is not available in library How-ever, it must not be used for final chip sign-off, where all library operating conditions must be available. The index is the name of a library set. Allowed values are the operating condition keys which can be found in library pack-aging/vc.bbview files (typically _V_)

G_PRIMETIME_USE_FULL_OPCOND_NAME

This variable is transparently set by the techno kit. It is true when the operating condition defined in the libraries is of the form wc_1.10V_125C instead of Worst.

Table 4: Operating condition related variables

Variable name ValueG_MODES Obsolete

G_OPCOND_MODES()

Obsolete

G_BLOCK_DESIGN_MODE_MAP()

Specifies the mapping between the top design mode and the block design mode.

Table 5: Mode Related Variables

Variable name Value

Table 3: Design features related variables


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Implementation Flow Variables

Variable name ValueG_NBTI_EXTENSION Specify the NBTI extension to be used for librar-

ies and blocks. Allowed values are _10y, _1ey, _2ey,... The default value is set by the technol-ogy kit.

G_NBTI_MISSING_LIBRARIES

Specifies the libraries for which NBTI data is not available for implementation (only for tech-nologies that use NBTI).

G_NBTI_MISSING_LIBRARY_OPCOND_NAMES()

This variable can be used when a NBTI operating condition is not available in library However, it must not be used for final chip sign-off, where all library NBTI operating conditions must be available. Allowed values are the non NBTI operating condition keys, corresponding to the missing NBTI operating conditions, which can be found in library packaging/vc.bbview files (typically _V_)

G_NBTI_MISSING_LIBRARY_SETS

Lists the names of library sets for which no NBTI views are expected.

G_BLOCK_NONBTI Specifies a list of block masters for which NBTI data is not available.

Table 6: NBTI Related Variables

Variable name ValueG_IMPLEMENTATION_MODE Defines the mode in which the implementation is

going to be performed.

G_IMPLEMENTATION_NBTI Specifies whether the design should be imple-mented using NBTI or not. For RtlKit, AvantiKit and SignOffKit, this variable is automaticaly set to the correct value depending on technology By default this variable is set to the value of G_NBTI.

Table 7: Global implementation variable


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G_IMPLEMENTATION_NBTI_MISSING_LIBRARIES

Specifies the libraries for which NBTI data is not used for implementation (only for technolo-gies that use NBTI). By default this variable is set to the value of G_MISSING_LIBRARIES.

G_IMPLEMENTATION_OPCOND_MODES()

List of modes to be performed for the operating condition , where defined with the G_OPCOND_NAME() variable. By default this variable is set to the value of the G_OPCOND_MODES() variable.

G_BLOCK_PR_MODE() In top-down flow, blocks are located along with design data. This variable should be set to budget. In bottom-up flow, blocks are along with libraries. This variable should be set to library.

G_PSYN_HIGHSPEED_LIBRARIES

Specifies the high speed libraries for mix HS/LL flow

Variable name ValueG_NETLISTOPT_DO_COMPILE Determines if incremental compile is done.

G_NETLISTOPT_TEST_READY Determines scan ready FFs are to be preserved.

G_NETLISTOPT_TEST_INSERTION

Enables basic test insertion.

G_NETLISTOPT_XDBIST_INSERTION

Enables XdBist insertion in a gate 2 gate synthe-sis flow.

G_PRECTS_FIX_HOLD Enables the synthesis flow to fix hold violations before Clock Tree Synthesis.

G_CTEDIT_GTECH Enables the CTEdit flow (Clock Tree + High Fanout Net management at GTECH level).

G_SYNTHESIS_USE_ACS Enables the parallel compilation with Automated Chip Synthesis (Bottom-up synthesis), instead of Top-Down synthesis.

G_SYNTHESIS_USE_SVF Enables the SVF flow (Design Compiler creates information files that help Formality prove the synthesis).

Table 8: Variable specific to SYNTHESIS tasks

Variable name Value

Table 7: Global implementation variable


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G_SYNTHESIS_DO_REFINE Determines if a refinement pass is to be done for optimization

G_SYNTHESIS_TEST_READY Enables the use of flip-flops with dedicated scan connected together (compile -scan).

G_SYNTHESIS_TEST_INSERTION

Enables basic test insertion.

G_SYNTHESIS_CLOCK_GATE Enables the automated clock gating insertion with Power Compiler.

G_SYNTHESIS_USE_XG Enables the use of XG mode in Design Compiler. Available in v.2003.12+.

G_SYNTHESIS_USE_LSF Enables the use of LSF for ACS compilation of par-titions.

G_SYNTHESIS_LSF_COMMAND (optional) Specifies the default LSF command for ACS (G_SYNTHESIS_USE_LSF must be set to true).

G_SYNTHESIS_LSF_COMMAND_LARGE

(optional) Specifies the LSF command to use for large partitions (G_SYNTHESIS_USE_LSF must be set to true).

Variable name ValueG_DEFAULT_DRIVE_LIB library that contains the driving cells to make

the default budget. It is mandatory to use a drive lib to enable the use of the xb template latter on.

G_DEFAULT_DRIVE this is the default driving cell to use for all outputs or inouts of the sub-blocks.

G_DEFAULT_MAX_LOAD this is the default expected maximum loading for the drive cell specified with G_DEFAULT_DRIVE

G_DEFAULT_PORT_LOAD this is the default port load for all ports of the sub-block.

G_DEFAULT_DRIVE_INPUT_TRANSITION

this value is used by the .lib generator to extract from the driving cell specified a table that depends only on loading.

Table 9: Variable specific to BUDGETING tasks

Variable name Value

Table 8: Variable specific to SYNTHESIS tasks


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SignOff Flow Variables:

Variable name ValueG_ICPACK_CLASS class of pads to be used for IO libraries.

G_ICPACK_VERSION()

IO libraries versions. This variables also defines the list of IO libraries.

Table 10: Variable specific to ICPACK tasks

Variable name ValueG_SIMPLE_FLOW Specifies a reduced set of netlist checks, for a

implementation flow able to keep all verilog names.

Table 11: Variable specific to CHECKS tasks

Variable name ValueG_EXTRACTION_TOOL Specifies the extraction tool to be used: starrcxt

or arcadia. Default is computed from the technol-ogy name.

G_EXTRACTION_MODE Specifies the extraction mode: best_worst or typic. Default is best_worst.

Table 12: Variable specific to EXTRACTION tasks

Variable name ValueG_HOST_ARCH Defines the host architecture, for script genera-

tion. This variable is used by the VERIFICATION variable, for calibre invocation.Default value is 64.

G_PR_FLOW Defines the implementation flow being used. This variable is used by the VERIFICATION task, for cdl netlist generation.

G_NETLIST2CDL_READ_DEF Let netlist2cdl read the routed def and to include the physical cells into the output cdl.

Table 13: Variable specific to VERIFICATION tasks


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G_SIGNOFF_DRC_CALIBRE_OPTIONS

Specifies options for drc calibre

G_SIGNOFF_LVS_CALIBRE_OPTIONS

Specifies options for lvs calibre

G_POWER_AUTO_CONNECT When true (the default for 90nm and previous tech-nologies), netlist2cdl will automatically con-nect power ports with same name eventhough they are not defined in the power.attx. When false (the default for 65nm and bellow), netlist2cdl will connect power port only if they are defined in the power.attx. All remaining ports will be left unconnected.

Variable name ValueG_PAD_OPENING_LAYER Normally automatically set by SignOffTechnoKit.

Available to override in case it is needed for a workaround. Defines the layer:datatype to use to identify pad openings.

G_PROBE_TEXT_LAYER Normally automatically set by SignOffTechnoKit. Available to override in case it is needed for a workaround. Defines the layer:datatype to use to identify so called probe text which defines where to place probes inside the pad opening.

Table 14: Variable specific to EWS tasks

Variable name ValueG_BLOCK_TA_MODE() Describes how a hierarchical cell is to be used in

PrimeTime flow. In spef mode, the verilog and spef are loaded flat this mode is required for SignOff. Other modes are dspf, etm, ilm, "budget".

Table 15: Variables specific to DELAY_CALC and TIMING_ANALYSIS tasks

Variable name Value

Table 13: Variable specific to VERIFICATION tasks


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G_DELAY_CALC_MAX_CAP Max capacitance to be checked during DELAY_CALC. Typically, this variable is used to take an addi-tional margin to the checks specified in librar-ies, in consequence, the value specified should be lower than the values specified in libraries. When this variable is set to the value XXX, the set_max_capacitance command is commented in the DELAY_CALC.OPCOND.pt scripts, and the default max_capacitance of each cell is used.

G_DELAY_CALC_MAX_TRAN Max transition to be checked during DELAY_CALC. Typically, this variable is used to take an addi-tional margin to the checks specified in librar-ies, in consequence, the value specified should be lower than the values specified in libraries. When this variable is set to the value XXX, the set_max_transition command is commented in the DELAY_CALC.OPCOND.pt scripts, and the default max_transition of the library is used.

G_DELAY_CALC_LIBRARY_STAMP_MODELS()

Specifies the library STAMP models to be used for each library during DELAY_CALC. This variable is an array whose index contains the library name and value contains the list of stamp names.

G_DELAY_CALC_ANNOTATE_SIMULATOR

Simulator to be used to check SDF annotation. Allowed values are verilogxl, ncverilog, modelsim and vcs. Default simulator is ncverilog.

G_DELAY_CALC_CHECK_CLOCK_DRC

Enables the sourcing of the clock drc script gen-erated by ctEdit, during delay-calculation.

G_PRIMETIME_TIMING_EXCEPTIONS

Enables the management of exceptions as a separate PrimeTime constraint file. Must be true.

G_DELAY_CALC_CHECK_CLOCK_DRC

Specifies that primetime should check and export clocks transition in DELAY_CALC or dspf mode TIMING_ANALYSIS.

G_TA_REPORT_LEVEL none, short, medium or full, default is full. Defines the verbosity of reports in DELAY_CALC and TIMING_ANALYSIS tasks. See task description for full details.

Variable name Value

Table 15: Variables specific to DELAY_CALC and TIMING_ANALYSIS tasks


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Variable name ValueG_TA_REPORT_TIMING Enable the generation of a full range of

report_timing commands in timing analysis if true. Useful for debugging, but costly in run-time. If not set, default value is true.

G_TA_REPORT_CLOCK_TIMING

Enables the generation of report_clock_timing script to analyse the clock trees of the design if true. If not set, default value is false.

G_TA_QUIT If false, no quit will be present at the end of the timing analysis primetime shell scripts. If not set, default value is true.

G_TA_SAVE_SESSION When set to true, the primetime session is savedbefore exiting. The session can then be restoredusing restore_session command.

G_TA_CRPR_MODES Obsolete

G_CRPR_HOLD_ONLY Specify if CRPR is performed only for hold. A default value is specified in the techno kit.

G_CRPR_DERATE Clock delay derating factor for the CRPR timing analysis flow. Used in sign-off timing analysis when CRPR flow is activated.

G_HOLD_UNCERTAINTY Minimum hold uncertainty for the CRPR timing anal-ysis flow. Used in sign-off timing analysis when CRPR flow is activated.Default is 20ps.

G_TA_MAX_FIX_CELL Maximum number of cells to be fixed when generat-ing the fix hold report for the CRPR timing anal-ysis flow in worst mode. Used in sign-off timing analysis when CRPR flow is activated

G_TA_FIX_HOLD_ARRAY(Worst)

Specifies the buffers to be used when generating the fix hold report for the CRPR timing analysis flow in worst corner. Used in sign-off timing analysis when CRPR flow is activated.

G_TA_FIX_HOLD_ARRAY(Best)

Specifies the buffers to be used when generating the fix hold report for the CRPR timing analysis flow in best corner. Used in sign-off timing anal-ysis when CRPR flow is activated.

Table 16: Variables specific to TIMING_ANALYSIS task


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0.1.3 seed.cpf example

An example of seed.cpf is as follows:set_design

create_power_domain -default -name TOP

create_nominal_condition -name 1.10V -voltage 1.10

create_power_mode -name functional -domain_conditions {[email protected]}create_power_mode -name test -domain_conditions {[email protected]}

###################### operating corners ######################

Variable name ValueG_POWER_OPCONDS Obsolete.

G_POWER_ANALYSIS_PIPE_MODE

Set to true if the output of the simulator is piped directly in PrimePower. Set to false if a .vcd.gz is read.

G_POWER_VCD_STRIP_PATH()G_POWER_VCD_STRIP_PATH

G_POWER_VCD_STRIP_PATH specifies the path of the design in the vcd simulation file.In case this path is mode dependent, the G_POWER_VCD_STRIP_PATH() must be used.These two syntaxes are exclusive.

Table 17: Variables specific to POWER_ANALYSIS

Variable name ValueG_PACKAGE_LIBRARY_NAME Library name of the package. Set to the design

name by default

Table 18: Variable specific to PACKAGING , TIMING_ETM_MODEL and TIMING_FALT_MODEL tasks


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create_operating_corner -name nom_1.10V_25C_RCTYP -process 1.0 -voltage 1.10 -temperature 25 -library_set Nomcreate_operating_corner -name bc_1.20V_m40C_RCMIN -process 0.8 -voltage 1.20 -temperature -40 -library_set Bestcreate_operating_corner -name bc_1.20V_m40C_RCMAX -process 0.8 -voltage 1.20 -temperature -40 -library_set Bestcreate_operating_corner -name bc_1.20V_125C_RCMIN -process 0.8 -voltage 1.20 -temperature 125 -library_set bc_1.20V_125Ccreate_operating_corner -name bc_1.20V_125C_RCMAX -process 0.8 -voltage 1.20 -temperature 125 -library_set bc_1.20V_125Ccreate_operating_corner -name wc_1.05V_125C_RCMIN -process 1.2 -voltage 1.05 -temperature 125 -library_set Worstcreate_operating_corner -name wc_1.05V_125C_RCMAX -process 1.2 -voltage 1.05 -temperature 125 -library_set Worstcreate_operating_corner -name wc_1.05V_m40C_RCMIN -process 1.2 -voltage 1.05 -temperature -40 -library_set wc_1.05V_m40Ccreate_operating_corner -name wc_1.05V_m40C_RCMAX -process 1.2 -voltage 1.05 -temperature -40 -library_set wc_1.05V_m40C

set operating_corner_properties(nom_1.10V_25C_RCTYP) {rc RCTYP}set operating_corner_properties(bc_1.20V_m40C_RCMIN) {rc RCMIN}set operating_corner_properties(bc_1.20V_m40C_RCMAX) {rc RCMAX}set operating_corner_properties(bc_1.20V_125C_RCMIN) {rc RCMIN}set operating_corner_properties(bc_1.20V_125C_RCMAX) {rc RCMAX}set operating_corner_properties(wc_1.05V_125C_RCMIN) {rc RCMIN}set operating_corner_properties(wc_1.05V_125C_RCMAX) {rc RCMAX}set operating_corner_properties(wc_1.05V_m40C_RCMIN) {rc RCMIN}set operating_corner_properties(wc_1.05V_m40C_RCMAX) {rc RCMAX}

################ Extractions ################

create_analysis_view -name Best -mode functional {TOP@bc_1.20V_m40C_RCMIN

}create_analysis_view -name Best_125C -mode functional {

TOP@bc_1.20V_125C_RCMIN}create_analysis_view -name Worst -mode functional {

TOP@wc_1.05V_125C_RCMAX}create_analysis_view -name Worst_m40C -mode functional {

TOP@wc_1.05V_m40C_RCMAX


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}create_analysis_view -name Nom -mode functional {

TOP@nom_1.10V_25C_RCTYP}

######################## functional analysis ########################

create_analysis_view -name functional_Best -mode functional {TOP@bc_1.20V_m40C_RCMIN

}create_analysis_view -name functional_Best_RCMAX -mode functional {

TOP@bc_1.20V_m40C_RCMAX}create_analysis_view -name functional_bc_1.20V_125C -mode functional {

TOP@bc_1.20V_125C_RCMIN}create_analysis_view -name functional_bc_1.20V_125C_RCMAX -mode functional {

TOP@bc_1.20V_125C_RCMAX}create_analysis_view -name functional_wc_1.05V_m40C_RCMIN -mode functional {

TOP@wc_1.05V_m40C_RCMIN}create_analysis_view -name functional_wc_1.05V_m40C -mode functional {

TOP@wc_1.05V_m40C_RCMAX}create_analysis_view -name functional_Worst_RCMIN -mode functional {

TOP@wc_1.05V_125C_RCMIN}create_analysis_view -name functional_Worst -mode functional {

TOP@wc_1.05V_125C_RCMAX}

set analysis_view_properties(Best) {parasitics Best}set analysis_view_properties(Best_RCMAX) {parasitics Best}set analysis_view_properties(bc_1.20V_125C) {parasitics Best_125C}set analysis_view_properties(bc_1.20V_125C_RCMAX) {parasitics Best_125C}set analysis_view_properties(wc_1.05V_m40C_RCMIN) {parasitics Worst_m40C}set analysis_view_properties(wc_1.05V_m40C) {parasitics Worst_m40C}set analysis_view_properties(Worst_RCMIN) {parasitics Worst}set analysis_view_properties(Worst) {parasitics Worst}


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################## test analysis ##################

create_analysis_view -name test_Best -mode test {TOP@bc_1.20V_m40C_RCMIN

}create_analysis_view -name test_Best_RCMAX -mode test {

TOP@bc_1.20V_m40C_RCMAX}create_analysis_view -name test_bc_1.20V_125C -mode test {

TOP@bc_1.20V_125C_RCMIN}create_analysis_view -name test_bc_1.20V_125C_RCMAX -mode test {

TOP@bc_1.20V_125C_RCMAX}create_analysis_view -name test_wc_1.05V_m40C_RCMIN -mode test {

TOP@wc_1.05V_m40C_RCMIN}create_analysis_view -name test_wc_1.05V_m40C -mode test {

TOP@wc_1.05V_m40C_RCMAX}create_analysis_view -name test_Worst_RCMIN -mode test {

TOP@wc_1.05V_125C_RCMIN}create_analysis_view -name test_Worst -mode test {

TOP@wc_1.05V_125C_RCMAX}

set xtscenarios { Best

Best_125C

Worst

Worst_m40C Nom

}

set tascenarios { functional_Best functional_Best_RCMAX functional_Worst_RCMIN


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functional_Worst test_Best

test_Best_RCMAX

test_Worst_RCMIN

test_Worst

functional_bc_1.20V_125C functional_bc_1.20V_125C_RCMAX functional_wc_1.05V_m40C_RCMIN functional_wc_1.05V_m40C test_bc_1.20V_125C test_bc_1.20V_125C_RCMAX test_wc_1.05V_m40C_RCMIN test_wc_1.05V_m40C}

set analysis_view_scenarios(IMPLEMENTATION) $tascenariosset analysis_view_scenarios(EXTRACTION) $xtscenariosset analysis_view_scenarios(DELAY_CALCULATION) $tascenariosset analysis_view_scenarios(TIMING_ANALYSIS) $tascenariosset analysis_view_scenarios(POWER_ANALYSIS) $tascenariosset analysis_view_scenarios(STATIC_IRDROP_ANALYSIS) $tascenariosset analysis_view_scenarios(DYNAMIC_IRDROP_ANALYSIS) $tascenariosset analysis_view_scenarios(RAMPUP_ANALYSIS) $tascenarios

0.1.4 seed.tcl example

An example of seed.tcl file is as follows:#============================================================================# DEFINE DESIGN NAME, DESIGN RULE CHECKS#============================================================================

set G_DESIGNS " "set G_DESIGN_TYPE "top|block"set G_TECHNO "cmos045lp_7m4x0y2z"

#============================================================================# DEFINE LIBRARY AND HIERARCHICAL SUB-BLOCKS#============================================================================

set G_LIBRARIES { }


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# To specify specific libraries for block master# set G_BLOCK_REFERENCE_LIBRARIES() { }

# To specify the cell name and instance path of hierarchical# sub-blocks, which are implemented separately. Please uncomment and# duplicate the following statement as needed.

# set G_BLOCKINSTANCE() # set G_BLOCK_PR_MODE() {budget|library}

#============================================================================# FLIP CHIP PARAMETERS#============================================================================

# To generate Flip Chip tasks, set the following variable to true : # Signoff RDL extraction (block or top) etc...set G_FLIP_CHIP false

#============================================================================# DEFINE DESIGN LIBRARY OPERATING_CONDITIONS# define operating conditions persent in libraries#============================================================================

set G_OPCOND_LIBRARY ""

# set G_PHYSICAL_LIBRARIES { .....}

set G_NBTI_MISSING_LIBRARIES {}set G_NBTI_MISSING_LIBRARY_SETS {bc_1.20V_125C}

#============================================================================# Flow definition variables#============================================================================

set G_HOST_ARCH 64set G_SIMPLE_FLOW true

#============================================================================# DELAY_CALC TASK PARAMETERS#============================================================================


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set G_DELAY_CALC_MAX_CAP "XXX"

set G_DELAY_CALC_MAX_TRAN "XXX"

# To use library STAMP models, the list of STAMP model names to be# used for each library need to be specified. Please duplicate the# following statement as needed.

set G_DELAY_CALC_LIBRARY_STAMP_MODELS() { }

# To Specify the timing model to be used for each hierarchical# sub-block. Please uncomment and duplicate the following statement# as needed. Allowed values are dspf, ilm, etm. Default value is# dspf.

#set G_BLOCK_TA_MODE() dspf

# in case the model has been generated only with fresh libraries#set G_BLOCK_NONBTI { }

# Available simulators are ncverilog verilogxl modelsim

set G_DELAY_CALC_ANNOTATE_SIMULATOR {ncverilog}

#============================================================================# TIMING ANALYSIS PARAMETERS#============================================================================

set G_TA_NBTI_MISSING_LIBRARIES {}set G_TA_CROSS_CORNERS true

set G_BLOCK_DESIGN_MODE_MAP() { ...}

set G_TA_QUIT trueset G_TA_SAVE_SESSION true

## G_TA_REPORT_LEVEL, G_TA_REPORT_TIMING, G_TA_REPORT_CLOCK_TIMING: ## these variables can be modified after script generation## by modifying the variables.pt in DELAY_CALC or TIMING_ANALYSIS tasks

## G_TA_REPORT_TIMING possible values are none, short, medium, full## MANDATORY for SIGNOFF: full## DELAY_CALC: 4_case_analysis_log_file & 6_report_disable_timing only in full


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## TIMING_ANALYSIS:## none : minimum set of reports : report_constraints & check_timing## short : add report_max_delay_violator & report_qor## medium : add report_*_violator & report_clock, port, hierarhy, reference, cell## full : add 4_case_analysis_log_file, 6_report_disable_timing, ## report_ignored_exceptions, analysis_coverage*, min_pulse_widthset G_TA_REPORT_LEVEL full

## G_TA_REPORT_TIMING possible values are true and false## when true, timing/*.rpt reports are generatedset G_TA_REPORT_TIMING true

## G_TA_REPORT_CLOCK_TIMING possible values are true and false## when true, report_clock_timing.rpt report is generatedset G_TA_REPORT_CLOCK_TIMING true

set G_CRPR_DERATE 0.1set G_SETUP_UNCERTAINTY 0.1set G_HOLD_UNCERTAINTY 0.02set G_TA_MAX_FIX_CELL 7

# Variable available to customise defaults buffer list for hold fixing loop#set G_TA_FIX_HOLD_ARRAY(Best) " { }EXAMPLE_BUF {0.1 0.15}"#set G_TA_FIX_HOLD_ARRAY(Worst) " { } EXAMPLE_BUF {0.3 0.45}"

#============================================================================# POWER ANALYSIS PARAMETERS#============================================================================

set G_POWER_ANALYSIS_PIPE_MODE false

#set G_POWER_VCD_STRIP_PATH() XXX/YYY

#============================================================================# VERIFICATION PARAMETERS#============================================================================

# Disk-space saving option to GZIP MASK GDSII, only if CALIBRE support it# i.e. from CALIBRE 2002.9 (v9.1_9) on : To activate option, uncomment line.#set G_CALIBRE_ZIP "true"

design setup fpr cpf

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