design techniques for cmos broadband amplifiers papers/cmoset_2009_cmos... · s1 c g v out transfer...

1-25High-Speed Devices and Integrated Circuits Group, NTHU

Design Techniques for CMOS Broadband Amplifiers

Shawn S. H. Hsu and Allen J. D. JinHigh-speed Devices and Integrated Circuits Group

Electrical Engineering and Institute of Electronics EngineeringNational Tsing Hua University, Hsin Chu, Taiwan

02/19/2009


Outline• Introduction

− Application of broadband amplifiers− CMOS design considerations and challenges− Different wideband techniques

• π-type inductor peaking (PIP)− Transfer function analysis− A 40-Gb/s TIA using 0.18-μm CMOS technology

• Asymmetric transformer peaking− Transfer function analysis− A miniaturized 70-GHz amplifier using 0.13-μm CMOS technology

• Summary and conclusion


Broadband Amplifiers for communications

• Wireless communication system

RT

I/QDemodulator

PLL

I/QModulator

Filter

PA

MixerLNA

LO

Multiplier

Antenna

Filter

Filter

Switch


Broadband Amplifiers for communications (cont.)

• Optical communication system

Digital Logic

FiberPD

TIA LA CDR DMUX

FiberLD

MUXTx

Rx

DriverDigital Logic

• To meet requirement of high-speed and low-noise, III-V or SiGetechnology is preferred

Still a challenge if using CMOS to design


Optical interconnect

[Ref.]: Photonics research group, INTEC

• Intra-chip optical interconnecta miniaturized optical communication system on chipOne of the bottlenecks: high-speed, small-size,and low power broadband amplifiers in CMOS

[Ref.]: R. G. Beausoleil, IEEE LEOS, 2007, HP laboratories

[Ref.]: W. Bogaerts, Photonics and Nanostructures, IMEC


How far can we push the RF circuit performance using CMOS?

Circuit configuration (simpler solution is always a better solution) Inductive components (effective way to enhance Gain-BW)Layout (the key to success)

• In addition to continuous scaling of CMOS, what else can we do?

• Major considerations when designing a CMOS broadband amplifier

Chip area (cost) Gain-Bandwidth productPower consumptionGroup delay, noise, linearity, ..


Scaling of CMOS and Limitation for High-speed Operation

Gain= Rd

BW= 1/Rd(Cd+Cg)

GBW= 1/(Cd+Cg)

Gain= Rg

BW= 1/Rg(Cpd+Cg)

GBW= 1/(Cpd+Cg)

RdCd Cg

gmvgs voutipd

CgCpd Rg

• C↓ GBW↑ Speed↑

0

50

100

150

200

250

fT a

nd f m

ax (G

Hz)

0.25 μm

0.18 μm

0.13 μm

90 nm

65 nm

0.35 μm

fmaxfT

• For transimpedance gain consideration


• Feedback amplifier− simple to design and small chip area− not easy to achieve high gain if a large

bandwidth is required

• Inductive peaking amplifier− No additional DC power − high gain can be obtained by cascade

amplification (gain multiplied fromeach stage)

− Inductors consume a large chip area

Broadband Techniques for Amplifiers

• Distributed amplifier− form virtual transmission line to achieve

a large BW− large DC power consumption and chip

area (parallel amplification; gain added from each stage)

☺☺

☺☺

☺☺

☺☺

Rf

RLCd

gmvgs

vgs

—

+Cg

Cd

gmvgs Ld

CL

Rd

Cg

—

+vgs

Cd

gmvgs Ld

CL

Rd

Cg

—

+vgs


Inductive Peaking Technique

zs ω+

zω

p

z

ss

ωω

++

zp ωω , ω

ps ω+1

pω ω ω

• Inductor can introduce a zero in the transfer function to enhance BW

• Inductor can also introduce complex conjugate poles to enhance BW if the damping factor ζ is smaller than 0.707

200

2 21 )(

ωζω ++∝

sssH

)1(- 201 −+= ζζωP

)1(- 202 −−= ζζωP


Shunt Inductor Peaking

• A zero is introduced by Ld to extend BW • Bandwidth enhancement ratio (BWER) is 1.85

[Ref.] S. S. Mohan, M. del M. Hershenson, S. P. Boyd, and T. H. Lee, “Bandwidth extension in CMOS with optimized on-chipinductors,” IEEE J. of Solid-State Circuits, vol. 35, pp. 346-355, Mar. 2000.

0.0 0.5 1.0 1.5 2.0 2.5-6

-3

0

3

6

9

Nor

mal

ized

gai

n (d

B)

Normalized frequency (rad/s)

a: without any peaking techniques b: inductor peaking

Vdd

Rd

Cd Cg

gmvgs

Ld

vout


Shunt-Series Peaking

[Ref.] S. Galal and B. Razavi, “40-Gb/s amplifier and ESD protection circuit in 0.18 µm CMOS technology,”IEEE J. of Solid-State Circuits, vol. 39, pp. 2389-2396, Dec. 2004.

Vdd

Rd

Cd Cg

gmvgs

Ld

voutLs

• A zero and a pair of complex conjugate poles are introduced to extend BW, and the BWER is 1.83 (Cg/Cd= 3)

0.0 0.5 1.0 1.5 2.0 2.5-6

-3

0

3

6

9

Nor

mal

ized

gai

n (d

B)


a: without any peaking techniques b: inductor peaking c: shunt-series peakking


T-coil Peaking

[Ref.] S. Galal and B. Razavi, “Broadband ESD protection circuits in CMOS technology,” IEEE J. of Solid-State Circuits, vol. 38, pp. 2334-2340, Dec. 2003.

Vdd

Rd

Cd Cg

gmvgs vout

CcLd

k

Ld

• A zero and two pairs of complex conjugate poles areintroduced to extend BW, and the BWER is 2.40

0.0 0.5 1.0 1.5 2.0 2.5-6

-3

0

3

6

9

Nor

mal

ized

gai

n (d

B)


a: without any peaking techniques b: inductor peaking c: shunt-series peakking d: T-coil peaking


Proposed π-type Inductor Peaking (PIP)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0-6

-3

0

3

6

9

Nor

mal

ized

gai

n (d

B)


e: without any inductors f : Ld2

g: Ld2 + Ls1

h: Ld2 + Ls1 + Ld1

Vdd

Rd1

Cd

gmvgs

Rd2

Ld1 Ld2Ls1

voutCg

• Introduce two zeros and two pairs of complex poles • The BWER is 3.31 with a gain flatness within 2 dB


( )5

54

43

32

210

2

2

1

12

2

2

1

1

21

1

DsDsDsDssDDRL

RLs

RL

RLs

RRsH d

d

d

d

d

d

d

d

ddPIP +++++

+⎟⎟⎠

⎞⎜⎜⎝

⎛++

=

( )( )( )

( ) ( )( )

Ldsdd

ddddLds

LdsddsdLdsddd

LsddsdddddLd

Ldddsdd

dd

CCLLLDLRLRCCLD

CCLRRLLCLLLCLDCLRCLRLRLRCCD

CCRRLLLDRRD

1215

122114

1211121213

121112212

211211

210

=+=

++++=++++=

++++=+=

where

ddd

dds

ddd

CRL

CRL

CRL

××=

××=

××=

211

211

212

80.0

86.0

50.1

Vdd

Rd1

Cd

gmvgs

Rd2

Ld1 Ld2Ls1

voutCg

Transfer Function of PIP Topology

Two pairs of complex conjugate poles

Two zeros


Zero, Pole, and Complex poles

• Both damping factors ζLd1, p1 and ζLd1, p4 are < 0.707, BW enhancement

Ld2 + Ls1 + Ld1

─

Ld2 + Ls1

─

Ld2

─

─

─

without PIP

Damping factor

Complex pole

Pole

Zero

Ld2 + Ls1 + Ld1

─

Ld2 + Ls1

─

Ld2

─

─

─

without PIP

Damping factor

Complex pole

Pole

Zero

00.11 =pω

33.11 =zω

37.2

21.1

4,13,1

2,11,1

=

==

=

pLspLs

pLspLs

ωω

ωω

50.233.1

2

1

==

z

z

ωω

14.0

63.0

4,1

1,1

=

=

pLd

pLd

ξ

ξ

16.12,21,2

=

= pLdpLd ωω

79.01,2 =pLdξ

33.11 =zω

28.0

82.0

3,1

1,1

=

=

pLs

pLs

ξ

ξ01.3

28.1

5,14,1

2,11,1

=

==

=

pLdpLd

pLdpLd

ωω

ωω

39.13,1 =pLdω

79.0 1,2 =pLdζ 82.0 1,1 =pLsζ28.0 3,1 =pLsζ

63.0 1,1 =pLdζ14.0 4,1 =pLdζ

Ld2 + Ls1 + Ld1

─

Ld2 + Ls1

─

Ld2

─

─

─

without PIP

Damping factor

Complex pole

Pole

Zero

Ld2 + Ls1 + Ld1

─

Ld2 + Ls1

─

Ld2

─

─

─

without PIP

Damping factor

Complex pole

Pole

Zero

00.11 =pω

33.11 =zω

37.2

21.1

4,13,1

2,11,1

=

==

=

pLspLs

pLspLs

ωω

ωω

50.233.1

2

1

==

z

z

ωω

14.0

63.0

4,1

1,1

=

=

pLd

pLd

ξ

ξ

16.12,21,2

=

= pLdpLd ωω

79.01,2 =pLdξ

33.11 =zω

28.0

82.0

3,1

1,1

=

=

pLs

pLs

ξ

ξ01.3

28.1

5,14,1

2,11,1

=

==

=

pLdpLd

pLdpLd

ωω

ωω

39.13,1 =pLdω

79.0 1,2 =pLdζ 82.0 1,1 =pLsζ28.0 3,1 =pLsζ

63.0 1,1 =pLdζ14.0 4,1 =pLdζ


Circuit Topology of 40 Gb/s TIA

• 4 CS stages in cascadelow power and high gain

• π-type inductor peaking (PIP)wide BW

• The circuit BW is enhanced 11x by PIP

Vdd

RD RD

L4 L5

L6

RD RD

L4 L5

L6

RD RD

L4 L5

L6

RM RM

L7 L8

L9

M1 M2 M3 M4

Out

In

RM RM

L1 L2

L3

0 5 10 15 20 25 30 35 4025

30

35

40

45

50

55

Z T (dBΩ)

Frequency (GHz)

TIA without PIP TIA with PIP


Layout Considerations

• Full-custom designed inductors to reduce chip area

• Use GCPW (grounded coplanar wave guide) structure

improve shielding for lossy Sisubstrate and reduce crosstalkremove guard-ring of inductor to further reduce the size

1.17 x 0.46 mm2

Vdd Gnd Vdd

Gnd

In

Gnd

Gnd

Out

Gnd1.17 x 0.46 mm2

Vdd Gnd Vdd

Gnd

In

Gnd

Gnd

Out

Gnd

6.5μm

3μmM6M5M4M3M2M1

Ground Signal Ground

Si Substrate

5μm


0 5 10 15 20 25 30 35 400

10

20

30

40

50

60

0

50

100

150

200

250

300

Z T (dBΩ)

Frequency (GHz)

Z IN (Ω

)

Measured ZT and Eye Diagram

• Gain: 51 dBΩ

• BW: 30.5 GHz ( ~ 0.5 fT)

Iin: 740 μApp

231-1 PRBS

40-Gb/s

263 mVpp

10 ps

40-Gb/s

263 mVpp

10 ps


Comparison with Prior Art

[Ref.] J. Jin and S. Hsu, “A 40-Gb/s transimpedance amplifier in 0.18-µm CMOS technology,” IEEE J. Solid-State Circuits,vol. 43, no. 6, pp. 1449-1457, June, 2008.


Asymmetric Transformer Peaking

• Unequaled LP and LS

suitable for unequaled Cd and Cg

707.0707.0

2

1

<<

ξξ

( ) ( )( ) ( ) ( ) ( )kCCLLsCCRLsCLLksCLCLCLsCCsR

RLLkLsRsZ

gdSPgdPdSPgSdSdPgd

SPST −++−++++++

−+=

121/1

4322

Introduce one zero and two pairs of complex conjugate poles k-related terms are negative ⇒ frequencies of zero and complex poles↑Achieve a BWER up to 5

1

2

3

4

5

10 20 30 40 50 60

Frequency (GHz)

Cg/

Cd

RD

M1

LP

LS

k

LP≠LS

VDD

RD

M1

LP

LS

k

LP≠LS

VDD


Amplifier Configuration

• 5 cascaded CS stages: high gain• RM and RD: matching/biasing resistors• Gain: 10.3 dB• BW: 80.6 GHz (only 7.0 GHz

w/o inductive network)

VDD

RD

M1 OutIn

RD

LS

M1

RD

LS

M1

RD

LS

M1

RD

LS

M1

RMInductive network

Inductive network

Inductive network

Inductive network

Inductive network

Inductive network

0 20 40 60 80 10005

1015202530

S21

(dB

)

Frequency (GHz)

A : Without any peaking technique B : Shunt peaking C : Shunt-series peaking D : Symmetric transformer peaking E : Asymmetric T-coil peaking F : Asymmetric transformer peaking


Transformer Layout and Chip Micrograph

In Out

VDD GND VDD

Chip area: 0.39 mm2

Core area: 0.05 mm2

660 μm

core area

590 μm

In Out

VDD GND VDD

Chip area: 0.39 mm2

Core area: 0.05 mm2

660 μm

660 μm

core area

590 μm590 μm

• Layout of the asymmetric transformer(optimized for chip area and k)

0 10 20 30 40 50 60 70 80 90 1000.0

0.1

0.2

0.3

0.4

0.5

0.6

0

2

4

6

8

10

12

LS

QS

L P and

LS (n

H),

k

Frequency (GHz)

k

QP

LP

QP a

nd Q

S


Measurement Results

• Good agreement between measured and simulated results

• BW: 70.6 GHz • Gain-bandwidth product GBW: 231 GHz


Comparison with Prior Art

[Ref.] J. Jin and S. Hsu, “A miniaturized 70-GHz broadband amplifier in 0.13-µm CMOS technology," IEEE Trans. Microwave Theory Tech., vol. 56, no. 12, pp. 3086-3092, Dec. 2008.


Summary and Conclusion• A 40 Gb/s transimpedance amplifier (TIA) was achieved

using the proposed π-type Inductor Peaking (PIP)technique by 0.18-μm CMOS technology

• A 70-GHz miniaturized (core area only 0.05 mm2)broadband amplifier was achieved using the proposedasymmetric transformer peaking technique by 0.13-μm CMOS technology

Acknowledgement We would like to thank National Chip Implementation Center (CIC)and TSMC for the chip fabrication, and National Nano Device Laboratories (NDL) for chip measurements.

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