design with on-chip interconnect inductance (invited)design with on-chip interconnect inductance...
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Design with On-Chip Interconnect Inductance (Invited)
S. Simon Wong, C. Patrick Yue1, Richard Chang2, Frank O’Mahony3
Center for Integrated Systems, Stanford University, Stanford CA 1Carnegie Mellon University, PA 2Atheros Communications, CA 3Intel Corporation, OR
Abstract The detrimental effects of interconnect inductance on signal propagation have been widely discussed. This papers describes innovative design concepts that utilize the interconnect inductance to benefit the design of high-speed circuits. Specific examples are illustrated. I. Introduction As the operational frequency of an integrated circuit increases beyond GHz, the inductive impedance associate with an on-chip wire becomes comparable or dominant over the resistive component. This could result in additional signal distortion, propagation delay, and cross-talk noise [1, 2]. Hence, the general belief is that inductance, L, is detrimental to interconnect performance, and should be minimized. Although the extraction of L associated with a wire randomly placed in a chip is complicated by many factors [3]. L can be controlled if there is a dedicated current return path as in co-planar strip line, or micro-strip line. In such an environment, the wire L can actually provide a new design dimension. This paper describes specific examples of applying wire L in high-speed circuits. II. Near Speed-of-Light Propagation of Electrical Signal As a digital signal propagates down a long wire, the quality of the signal is degraded resulting in excessive delay or inter-symbol interference. To understand the reasons, the power spectral density of a 500 ps digital pulse is compared with the intrinsic frequency characteristics of a minimum-sized wire in Fig. 1. The digital signal is broadband in nature, while the wire characteristic changes dramatically over this frequency band. At lower frequencies, the wire behaves as a distributed R-C network. In this regime, signals travel very slowly by diffusion and undergo frequency dispersion. As the frequency increases, L begins to dominate over R, and the wire behaves more as a L-C waveguide. The high-frequency L-C regime allows for propagation of an electromagnetic wave; consequently,
the peak velocity is the speed-of-light in the dielectric surrounding the wire.
ox
Amplitude
Velocity
Figure 1 – Spectral power density of a typical digital pulse, and the signal propagation velocity versus frequency along a minimum-sized wire. Fig. 1 suggests that a high-speed system can be built by taking advantage of the wave nature of wire [4]. Firstly, it is necessary to eliminate the low-frequency portion of the signal that lags behind. This can be achieved by modulating the digital data with a sufficiently high-frequency carrier, and as a result, concentrating all the signal power in the L-C regime. Secondly, the crossover frequency between the R-C and L-C regimes can be shifted into the single GHz range by explicitly emphasizing L and reducing R. In this frequency range, simple RF circuits can be designed to transmit and receive these modulated signals. Fig. 2 illustrates the impact of using modulated signaling in combination with an optimized low-loss wire to support high-speed transmission. The signal spectral components now lie predominantly in the high-speed L-C regime. This system has been demonstrated in a TSMC 0.18-µm CMOS technology with six levels of Al/Cu wiring and SiO2 dielectric. The transmitter, receiver, and all other components are integrated on-chip. Fig. 3 shows as-measured input and output waveforms propagating over a distance of 2 cm. Excluding the delay needed for driving signals on and off the chip for testing and measurement., an average delay of 283ps is obtained, which corresponds to an effective signal propagation speed of nearly one-half the speed of light in SiO2.
Single SWO
Virtual grounds
Prototyped clock gridSimulated clock grid
Cross-coupled pair
Clock buffer
Injection-locked cross-coupled pair
14µm
4µm 3.5µm
1.8mm0.6mm
Clkinj
ox
Velocity
Amplitude
Figure 2 – Spectral power density of a modulated digital pulse, and the signal propagation characteristic of an optimized low-loss wire.
Figure 3 – Measured input and output waveforms of the modulated signal transmission system. III. 10 GHz Standing Wave Clock Global clock distribution has become increasingly difficult for multi-GHz microprocessors. Timing uncertainty must reduce with clock period, but skew and jitter for conventional H-trees are proportional to latency, which does not scale with clock period [5]. The global clock network in Fig. 4 distributes a 10 GHz clock through a grid of coupled standing-wave oscillators (SWOs) [6]. The SWO, as shown in Fig. 5, is analogous to a differential L-C oscillator where the gain and tank are distributed. These SWOs are coupled together and sustain synchronous, sinusoidal standing waves across the chip. A single clock source coupled into one SWO injection-locks the entire grid. Clock buffers recover a digital clock and drive the local circuits. This coupled SWO clock network has been prototyped in a TSMC 0.18-µm CMOS technology. The test chip integrates eight coupled SWOs. The grid injection locks to an external clock from 9.8 GHz to 10.5 GHz (6.4% locking range). The clock skew and jitter are measured to be less than 1ps.
Figure 4 – 10GHz global clock network with coupled standing wave oscillators.
Standing-waveoscillator (SWO)
Tank
λ/2
Gain
Output
Reference Signal(Input)
Figure 5 – Schematic of a standing wave oscillator. 5. Conclusions In high frequency operations, wire inductance is not necessary undesirable, but can be exploited for novel design concepts. Other design examples that exploit the distributive behavior of a wire at high frequencies include a 23 GHz distributed amplifier and a 16 GHz distributed oscillator [7]. Acknowledgments The work presented in this paper was partially supported by the MARCO Interconnect Focus Center. References [1] Restle, et al, IEEE JSSC, Apr 1998. [2] Deutsch, et al., Proc. IEEE, Apr 2001. [3] Kim, PhD thesis, Stanford University, 2004. [4] Chang, et al, Sym VLSI Circuits, June 2002. [5] Restle, et al, IEEE JSSC, May 2001. [6] O’Mahony, et al, ISSCC, 2003. [7] Kleveland, et al, IEEE JSSC, Oct 2001.
Design withOn-Chip Interconnect Inductance
S. Simon Wong, C. Patrick Yue1,Richard Chang2, Frank O’Mahony3
Electrical Engineering Department, Stanford University1 Intel Corp., 2 Carnegie-Mellon University, 3 Atheros Communication
Outline
• Detrimental Effects of Interconnect Inductance
• Taking Advantage of Inductance• Conclusions
Motivation
2t2LCtLG)(RCRG2x
2 VVVV
w s
l
H
w = 2 m, s = 2 m, l = 1 mm
Low Frequency
High Frequency
Crossover Frequency
Line Impedance vs Frequency
Commercial Design
30 , 0.2rt psUser Input
( ) ( ) 6d dt RLC t RC psScreeningCriteria
ScreeningOutput
98 nets
Inductance Screening Example
1.0E+00
1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Length (mm)
Num
ber o
f Net
s
All the Netstr = 20pstr = 30pstr = 40ps
= 0.2
Inductance Screening Result
Outline
• Detrimental Effects of Interconnect Inductance
• Taking Advantage of Inductance– Near Speed of Light Propagation of Electrical
Signal
• Conclusions
Inductance is a property of a closed current loop
1
11 1 1
S
B ds
1111
1
LI
I1 S1
c1
I2 S2
c2
1212
1
MI
2
12 1 2
S
B ds
Signal
Return
S
On-chip environment
?
Inductance Definition
Coplanar Configuration Microstrip Configuration
• Multiple Metal Levels• Shielding from Substrate/UnderlyingWires
• Resistance Scales with Width atHigh Frequencies
• Only Single Metal Level• Coupling to Substrate/Underlying Wires• Slow-wave Effects• Resistance is Independent ofWidth at High Frequencies
Coplanar versus Microstrip
1M 10M 100M 1G 10G0.85
0.9
0.95
1
Frequency [Hz]
Nor
mal
ized
Am
plitu
de
0.01
0.1
1
Nor
mal
ized
Vel
ocity
Velocity
Amplitude
Digital Signal over Global Wires
2t2LCtRC2x
2 VVV
R L C
Low Frequencies (R>> L).
R L C
High Frequencies (R<< L).
2t2LCtRC2x
2 VVV
Frequency analysis of digital pulse over interconnect.
1M 10M 100M 1G 10G−80
−60
−40
−20
0
20
Powe
r Spe
ctral
Dens
ityof
Trap
ezoid
al Pu
lse
1M 10M 100M 1G 10G0.85
0.9
0.95
1
Frequency [Hz]
Nor
mal
ized
Am
plitu
de
0.01
0.1
1
Nor
mal
ized
Vel
ocity
Velocity
Amplitude
Digital signals are broadband.• Most power of the digital
pulse is concentrated in slower, low-frequency regime.
Length of line = 1 mm
Digital Signal over Global Wires
Digital signals are broadband.• Most power of the digital
pulse is concentrated in slower, low-frequency regime.
• But, portion of signal that contributes to sharp rise time is in the higher frequency regime.
Frequency analysis of digital pulse over interconnect.
1M 10M 100M 1G 10G−80
−60
−40
−20
0
20
Powe
r Spe
ctral
Dens
ityof
Trap
ezoid
al Pu
lse
1M 10M 100M 1G 10G0.85
0.9
0.95
1
Frequency [Hz]
Nor
mal
ized
Am
plitu
de
0.01
0.1
1
Nor
mal
ized
Vel
ocity
Velocity
Amplitude
Length of line = 1 mm
Digital Signal over Global Wires
Modulate digital signals with a high-frequency carrier to
push signal spectrum into LC-regime.
Normal Digital Pulse. Modulated Digital Pulse.
Signaling in the LC Regime
INPUT:Digital Data
RF Carrier
Interconnect
SenseAmplifier
OUTPUT:Digital Data
RF Carrier
tdiel
tmetal
w
Cross-section:tmetal = 2 m
frequency = 10 GHzComposition: Al, SiO2
Need to minimize loss over interconnect, while using reasonable dimensions.
Contours of loss [dB/mm]
2 4 6 8
2
4
6
8
10
12
14
16
tdiel
(Dielectric Thickness) [µm]
w (
Sig
nal W
ire W
idth
) [µ
m] 0.20.3
0.3
0.4
0.4
0.5
0.5
0.6
0.6
0.7
0.70.80.9
1
Optimization of Low Loss Wires
1M 10M 100M 1G 10G 100G−30
−20
−10
0
Frequency [Hz]
Nor
mal
ized
Pow
er S
pect
rum
[dB
]
0.001
0.01
0.1
1
Nor
mal
ized
Vel
ocity
w.r
.t. c ox
1M 10M 100M 1G 10G 100G−30
−20
−10
0
Frequency [Hz]
Nor
mal
ized
Pow
er S
pect
rum
[dB
]
0.001
0.01
0.1
1
Nor
mal
ized
Vel
ocity
w.r
.t. c ox
Conventional Approach --Signal power is distributed over slowRC regime.
Modulated Approach --Signal power is concentratedin fast LC regime with the help ofbetter wires.
oxox
Amplitude
Velocity
Velocity
Amplitude
Modulated Signal over Global Wire
0 0.5 1 1.5 2 2.5 30
0.5
1
1.5
2
[V]
Time [ns]
Output
Reference Signal(Input)
• Taken with HP54750A digital sub-sampling oscilloscope
20 mm Delay: 283 ps (including modulator and demodulator delays,excluding buffer delay ) 1/2 Speed of Light
Measured Waveforms
Outline
• Detrimental Effects of Interconnect Inductance
• Taking Advantage of Inductance– Near Speed of Light Propagation of Electrical
Signal– 10 GHz Standing Wave Clock
• Conclusions
Travelling Waves
Zo
Incident wave
Travelling Waves
Zo
Incident wave
Travelling Waves
Zo
– Wave characteristics• Phase varies linearly with position• Amplitude is constant with position
– Used in most conventional clock distributions
Incident wave
Standing Waves
ZL = 0( L = -1)
Standing Waves
Reflected wave
Standing Waves
Reflected wave
Standing Waves
Reflected wave
Standing Waves
Standing wave
Standing Waves
Standing wave
Standing Waves
Standing wave
Standing Waves
Standing wave
Standing Waves
Standing wave
Standing Waves
Standing wave
Standing Waves
Standing wave
Standing Waves
– Wave characteristics• Phase is constant with position (with 180º discontinuities)• Amplitude varies sinusoidally with position
Standing wave
Standing Waves on Lossy Wires
+
Residualtravelling waveStanding wave
• Wire loss causes skew• Design using low-loss, inductive wires
Incident wave Attenuatedreflected wave
=
Standing-Wave Oscillator (SWO)
Tank
Gain/2
LC oscillator
)(2
1and
)(
dclk
dd
CCLfl
L
CCR
n
lgConditions for
oscillation at fclk
Standing-waveoscillator
SWO Coupling
ccp
ccp
ccp
ccp
ccp
ccp
ccp
ccp
ccp
ccp
Icouple
• Couple by directly connecting the wires• Low-Q oscillators have wide locking range
SWO Clock Grid
SWO Clock Grid SWO Clock Grid
SWO Clock Grid SWO Clock Grid
Clkinj
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (0/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (1/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (2/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (3/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (4/12)Tclk
SWO Clock Grid WaveformV
olt
age
(arb
itra
ry u
nit
s)
Y (wavelengths) X (wavelengths)
t = (5/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (6/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (7/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (8/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (9/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (10/12)Tclk
SWO Clock Grid WaveformV
olt
age
(arb
itra
ry u
nit
s)
Y (wavelengths) X (wavelengths)
t = (11/12)Tclk
SWO Clock Grid Waveform
Vo
ltag
e(a
rbit
rary
un
its)
Y (wavelengths) X (wavelengths)
t = (12/12)Tclk
Die Micrograph
Locking range 9.8 GHz – 10.5 GHz (6.4% range)Skew 0.6psJitter (added toexternal source)
<0.5ps rms(1.4ps rms external source)
Power 430mW
MUX and mixer
Cross-coupledpair
Differentialtransmission line
Accumulation-modeMOS varactor
Open-drainbuffer
3.0mm
Skew Measurements
• Tuned grid– 0.6ps global skew
SWOclock grid
1.4ps-rms
1.5ps-rms
t ps ps ps rmsjit grid, ( . ) ( . ) .15 14 052 2
Jitter Measurement
CLKref
Outline
• Detrimental Effects of Interconnect Inductance
• Taking Advantage of Inductance– Near Speed of Light Propagation of Electrical
Signal– 10 GHz Standing Wave Clock– Other Distributed Designs
• Conclusions
Distributed Amplifier
Out
RtermIn
Rterm
Amplifier S-parameters
Frequency (GHz)
S-p
aram
eter
s (d
B)
S11Vds = 1.5V Vgs = 1.3V Ids = 60mA
S12
S22
S21Unity Gain Bandwidth
0 10 20 30-20
-10
0
10
-14 dB
Distributed OscillatorFeedback
Z0 Out
In
W3
W3
W3
Z0+ Z0+ Z0+
Z0+ Z0+ Z0+ Vout_osc
Output wrapped around to the input
Phase Noise Comparison
Frequency (GHz)
Nor
mal
ized
Pha
se N
oise
(dB
c/H
z)
Razavi,
Wagemans,
Ali,
Craninckx,
Ahrens,
This Work
P=1mW, fm/f0
ISSCC 97
ISSCC 98
ISSCC 96
ISSCC 95
Lo-Pow Symp, 98
0 5 10 15 20-190
-180
-170
-160
-150
Hajimiri,
(std. CMOS)
(Glass substrate)
(bipolar)
(Bondwires)
(Bondwires)(std. CMOS)
(std. CMOS)PhD Thesis, 98
16.6
Conclusions
• At high frequencies, interconnect inductance can no longer be ignored
• Extraction of inductance in a typical IC environment is extremely difficult
• Only a small number of interconnects exhibit inductive behavior
• With dedicated return path, interconnect inductance can be controlled & optimized
• Incorporating inductance into distributed designs offer new opportunities