IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 3, MARCH 2018 1211

Designing 0.5 V 5-nm HP and 0.23 V 5-nm LPNC-FinFETs With Improved IOFF Sensitivity in

Presence of Parasitic CapacitanceHarshit Agarwal , Member, IEEE, Pragya Kushwaha , Member, IEEE,

Juan Pablo Duarte , Student Member, IEEE, Yen-Kai Lin , Student Member, IEEE,Angada B. Sachid, Member, IEEE, Huan-Lin Chang, Member, IEEE,

Sayeef Salahuddin, Senior Member, IEEE, and Chenming Hu, Life Fellow, IEEE

Abstract— Negative capacitance field effect transis-tor (NCFET) is designed in 5-nm FinFET node, whichsimultaneously meets the low-power and high-performancetargets of ION and IOFF at Vdd = 0.5 V and Vdd = 0.23 V,respectively, while the international roadmap for devicesand systems (ITRS 2.0) projected Vdd is 0.65 V for both. Theimpact of power supply and parasitic capacitance on theperformance of NCFET is studied. It is demonstrated thatNCFET can be designed for fluid subthreshold swing (SS)behavior such that SS is degraded around Vgs = 0, Vds =Vdd, and is improved in the subthreshold region. This helpsin combating OFF-current variation due to the thresholdvoltage fluctuations. A compact model to determine suchdesign conditions is presented. Parasitic capacitance andthe ferroelectric material parameters should be cooptimizedfor the target Vdd.

Index Terms— FinFET, low power (LP), NCFET, sub-60 mV/decade.

I. INTRODUCTION

SUB-60-mV/DECADE subthreshold swing (SS) can beachieved in NCFETs by the virtue of negative capacitance

property of the ferroelectric (FE) material [1]–[6]. There areseveral factors which play an important role in determiningoverall performance of the NCFETs. Parasitic capacitance isone of them [7]. Higher the parasitic capacitance is, better isthe capacitance matching across gate voltage (Vgs) leading tothe improvement in SS [8], [9]. Along with parasitic capaci-tance, in this paper, we study the impact of supply voltage onthe NCFET performance. They both are crucial in determiningthe operating region of the top FE-layer in the OFF-state,and may even cause it to bias at positive capacitance (PC)region at Vgs = 0 V and Vds = Vdd (Vds represents drain tosource voltage). This can leads to differential gain Av < 1[Av = (dVint/dVg)] in deep subthreshold region, and hence

Manuscript received October 4, 2017; revised January 2, 2018;accepted January 3, 2018. Date of publication January 23, 2018; date ofcurrent version February 22, 2018. The review of this paper was arrangedby Editor H. Wong. (Corresponding author: Harshit Agarwal.)

The authors are with the Department of Electrical Engineering andComputer Science, University of California at Berkeley, Berkeley, CA94720 USA (e-mail: harshit@berkeley.edu).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2018.2790349

degrades SS with respect to baseline FinFET. We believe thatlarge SS around Vgs = 0 V is desirable as it makes theOFF-current (IOFF) less sensitive to threshold voltage (Vth)variations, which is good for SRAM and variation sensitivecircuits. In subthreshold region, Av > 1 and SS improves,giving rise to gate voltage-dependent fluid swing behavior.Both the qualitative and quantitative analysis of fluid swingis presented. We define unity gain capacitance CUG such thatif the parasitic capacitance of the baseline device, Cp = CUGthen differential gain becomes unity at Vgs = 0 V andVds = Vdd. Cp > CUG will leads to Av < 1. CUG dependsnot only on the FE material properties but also on the supplyvoltage at which the device intends to be operated. Behavior ofCUG is studied with the help of newly derived compact model,which shows excellent agreement with the simulation results.As an example, hysteresis free NCFET is designed in 5-nmhigh performance (HP) FinFET process [10], which has fluidswing behavior with large SS around Vgs = 0 V, much lowerSS than baseline device in the subthreshold region, high ION

and lower IOFF at lower Vdd than specified by the ITRS 2.0.Interestingly, single designed NCFET simultaneously meetsthe ON and OFF current targets of high performance and lowpower (LP) technology, simply by lowering Vdd from 0.5 Vto 0.23 V.

This paper is organized as follows. Modeling and simulationframework is described in Section II. Fluid swing behav-ior of the NCFET is discussed in Section III, followed byNCFET design example in Section IV. Conclusion is drawn inSection V.

II. MODELING AND SIMULATION FRAMEWORK

The NCFET structure with internal metal gate is studiedfor the simplicity of modeling and easy understanding of theresults. Fig. 1(a) shows the equivalent circuit representationof the device. Dynamics of the FE-FinFET system is modeledby self-consistently solving the BSIM-CMG model [11] (forFinFET) and Landau-Khalatnikov (LK) equation (for FE) [12],as shown in Fig. 1(b) [8], [9], [13]. BSIM-CMG model isfirst calibrated to achieve 5-nm HP FinFET characteristics,as projected by ITRS 2.0 [10]. Table I shows the deviceparameters of the baseline FinFET [10]. Following analysis is

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1212 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 3, MARCH 2018

Fig. 1. (a) Equivalent circuit representation of NCFET structure. Parasiticcapacitance between the internal gate and source/drain are explicitlyshown. (b) Compact modeling using BSIM-CMG and L-K models.

Fig. 2. (a) Vint versus Vgs for different cases of parasitic capacitances atVds = Vdd = 0.65 V. (b) S-curve with markers for operation at Vgs = 0 Vand Vds = 0.65 V. As parasitics increases from zero, the operating pointmoves from a to e in the s-curve.

done for the case of coercive field Ec = 0.96 MV/cm, remnantpolarization Pr = 4 μC/cm2, and FE thickness Tfe = 1.8 nm.The impact of FE parameters will be discussed in Section IV.Total charge on the internal metal gate (QG ) can be expressedas

QG = QGI + Cps · Vint,s + Cpd · Vint,d (1)

Vfe = Vg − Vint = αQG + β Q3G (2)

TABLE IITRS 2.0 PREDICTION FOR HP AND LP TECHNOLOGIES AT 5-nm

NODE. THE BASELINE DEVICE IN THIS PAPER IS

CALIBRATED TO HP DESIGN

Fig. 3. Differential gain versus Vgs. Since the points d and e lies beyondE = Ec, Av is smaller than 1 for the Cp = 0.57 fF/μm and 0.7 fF/μm.This implies degraded SS as compared with the baseline device.

Fig. 4. (a) ION and IOFF as a function of parasitic capacitance Cp at Vdd =0.65 V. They both are nonmonotonic function of parasitic capacitance.IOFF depends more strongly on Cp. (b) Vint at Vgs = � as a functionof Cp. For Ec = −0.96 MV/cm, Vfec = Ec × Tfe = −0.178 V, which isattained at lower Cp when Vdd is large.

here QG I is the intrinsic gate charge and Cps (Cpd) representsparasitic capacitance between internal gate and source (drain)terminal (Cp = Cps + Cpd). α and β are the FE materialparameters. The operating point in the s-curve is determinedby the solution of (1) and (2).

III. NCFET: FLUID SWING BEHAVIOR

Fig. 2(a) plot voltage at the internal gate node, Vint versusVgs at Vds = Vdd = 0.65 V for five cases of total parasiticcapacitances: Cp = 0, 0.33, 0.46, 0.57, and 0.7 fF/μm.Nominal Cp is 0.57 fF/μm for 5-nm node [10]. Fig. 2(b)shows the operating condition at Vgs = 0 V in the s-curve.

AGARWAL et al.: DESIGNING 0.5 V 5-nm HP AND 0.23 V 5-nm LP NC-FinFETs WITH IMPROVED IOFF SENSITIVITY 1213

Fig. 5. (a) Av versus Vgs for a different Vdd. By reducing Vdd, NCFET starts its operation in NC state at Vg = � and hence differential gain isachieved. (b) SS versus drain current for a different Vdd. Reducing Vdd improves SS for this case. (c) Variation in off-current as a function of variationin threshold voltage. At high Vds, SS near Vgs = 0 V is larger, and therefore, IOFF is less sensitive to ΔVth.

In deep subthreshold region, the contribution of QGI to QG

is negligible (QGI ≈ 0), and the dynamics is governed by theparasitic capacitances.

For Cps = Cpd = 0 case, it is easy to follow from (1) and (2)that Vfe = 0 V is the stable operating point, which is indicatedby the point "a" in Fig. 2(b). For Cp �= 0, the operatingpoint at Vgs = 0 V and Vds = Vdd moves in the s-curvedepending on the level of Cps and Cpd. For Cp = 0.33 fF/μm,the operating point "b" lies in the negative capacitance zone.For Cp = 0.46 fF/μm, the operating point is "c," which isclose to (Ec, Pc). On increasing Cp to 0.57 fF/μm, it shiftsto the point "d" in the s-curve. Note that it is beyond the(Ec, Pc) point. In this case, the FE operates in the PC regionbecause d P/d E > 0. In Fig. 3, differential gain is shownas a function of gate voltage for all the cases of parasiticcapacitance at Vds = Vdd = 0.65 V. Note that for operatingpoints a–c in Fig. 2(b), Av ≥ 1, which means that NCFETwill have improved SS as compared with the baseline FinFET.However, for operating points "d" and "e," Av < 1 andhence SS would be degraded in the deep subthreshold region,before Vgs induces sufficient polarization to push the FE in thenegative capacitance (NC) state. This gate bias dependence ofAv makes SS of NCFET a strong function of gate voltage,and hence the fluid swing behavior. Vgs required to achieveunity differential gain is larger for larger parasitic, as shownin Fig. 3. This obviously makes Cps and Cpd an additionaldesign variable for designing NCFET. Note that while largerCp biases the FE in the zone of Av < 1, however, once intothe NC regime, it offers high gain due to improved capacitancematching. This is also evident from Fig. 3.

Apart from fluid swing behavior, ON and OFF currents arealso greatly affected by the region of operation in the s-curve. Fig. 4(a) shows IOFF and ION as a function of parasiticcapacitance. As Cp increases from 0, IOFF monotonicallydecreases up to certain Cp level and increases beyond thispoint. This behavior follows the s-curve trend in Fig. 2(b),which is traversed along a–e direction as Cp increases. To fur-ther understand this behavior, consider the internal voltagebehavior at Vgs = 0 and Vds = Vdd with Vdd varyingfrom 0.65 V to 0.45 V in Fig. 4(b). As Cp increases, Vintreduces until it reaches a minimum point, beyond which it

again increases with Cp . This minimum point is governed byVfe,c = Ec × Tfe = −0.178 V, which would be different fordifferent cases of Ec and Tfe. Once this point is achieved,OFF-current starts to increase with Cp in Fig. 4(a). ION, too,shows nonmonotonic trend. Initially, it increases since parasiticincreases the voltage gain. However, high gain reduces theamount of Vgs needed to arrive at (−Ec, Pc) point in the s-curve. Once the −Ec point is reached, ION starts to decreaseswith parasitic capacitance.

A. Impact of Supply Voltage and Unity Gain Capacitance

Like parasitic capacitance, supply voltage Vdd also play keyrole in NCFET operation. Fig. 5(a) shows Av for nominalCp = 0.57 fF/μm at various Vdd. At Vgs = 0 V, note that Av

reduces for high Vdd, qualitatively similar to Fig. 3. Av < 1for Vdd = 0.65 V, and >1 for 0.35 V. To understand this,consider the baseline device with no FE at the top. The drainand the source nodes are coupled to the gate node throughthe capacitors Cps and Cpd [14]–[16]. Assume Vs = 0 V forsimplicity and Vg = 0 V for OFF-state discussion. Charge atthe gate node is simply given as Q = Cpd×(Vg −Vd) = −Vd ·Cpd. When FE is connected to the gate, it has to support thischarge. Higher the drain voltage, higher the charge at the gatenode, and as a result it can be NC or PC state depending onthe charge magnitude. Lowering Vdd simply eases the chargerequirement, similar to lowering parasitic. Fig. 5(b) shows SSversus Ids at various Vdd. In deep subthreshold region, it ishigher than that of baseline device for high Vdd. This, in fact,is desirable as it makes IOFF relatively less sensitive to variationin the threshold voltage, as shown in Fig. 5(c), where fractionalchange in OFF-current δ IOFF is plotted as a function of �Vth.

In order to understand the supply voltage and Cp depen-dence of differential gain in OFF-condition, we developed asimple model to determine unity gain capacitance (CUG) suchthat if Cp > CUG, Av < 1 at Vgs = 0 V and Vds = Vdd.Starting from (1), setting QGI = 0 (as Vgs = 0 V) andassuming Cps = Cpd

Vint = 1

Cps + Cpd(QG + Vs · Cps + Vd · Cpd) = QG

Cp+ Vdd

2(3)

1214 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 3, MARCH 2018

Fig. 6. Unity gain capacitance versus Vdd. Av > 1 is achieved at Vgs =0 V and Vds = Vdd if Cp < CUG. For Vdd = 0.65 V, if the underlyingdevice has Cp = 0.48 fF/μm, it will show Av < 1 for Vdd > 0.65 V, andbelow this it will give Av > 1. Note that in Fig. 4(a), IOFF starts to increaseafter Cp = 0.48 fF/μm, which is consistent with the model prediction.

using Cp = Cps + Cpd and Vfe = Vgs − Vint

αQG + β Q3G = − QG

Cp− Vdd

2. (4)

Defining CUG as the total parasitic capacitance for whichQG becomes equal to polarization at E = Ec, i.e., =−[(−α/3β)]1/2 [17]

CUG =[

Vdd

2

√3β

−α− α · 2

3

]−1

(5)

CUG is a function of FE material properties (α and β) andsupply voltage, and does not depend on the underlying FinFET.To validate the model, Vdd needed to achieve Av > 1 isdetermined from SPICE simulations for different Cp levels.Fig. 6 compares SPICE results with the developed compactmodel. From this figure, CUG ≈ 0.48 fF/μm for Vdd = 0.65 V(point A), which means that for Cp = 0.48 fF/μm, devicewould be biased at (Ec, Pc) point. This is also consistentwith the OFF-current results in 4(a). Further note that as Vddreduces, CUG increases which is intuitively expected since forlower Vdd, larger parasitic capacitance is needed to bias theNCFET at (Ec, Pc) point. This is also consistent with the SSbehavior in Fig. 5(b).

IV. DESIGN EXAMPLE

In Fig. 7, Ids − Vgs is plotted for various Vdd and Cp =0.57 fF/μm. For every Vdd, Vgs is swept from 0 to Vdd. Thetarget ION as per ITRS 2.0 prediction of 1.5 mA/μm forHP 5-nm technology is achieved at Vdd = 0.5 V, along withIOFF = 0.2 nA/μm for Cp = 0.57 fF/μm. The OFF-currentis much lower than the ITRS 2.0 target of 100 nA/μm. Alsonote that the HP targets are met at Vdd = 0.5 V against 0.65 Vspecified by ITRS 2.0. If we want to reduce IOFF, say to meetthe LP target of 100 pA/μm, what should be our options?

The baseline device has IOFF = 100 nA/μm and SS ≈65 mV/dec [10]. For IOFF to reduce from 100 nA/μm to100 pA/μm, i.e., by three orders, internal gate voltage atVgs = 0 V should be at least −3×SS = −65×3 = −195 mV.Maximum Vint that can be obtained by optimizing Cp or Vddis Vfe,c = Ec × Tfe = −173.8 mV, as shown from Fig. 4(b).

Fig. 7. Drain current versus Vgs for Vdd from 0.65 V to 0.35 V. For everyVdd, Vgs is swept from � to Vdd. Target ION = 1.5 mA/μm is achieved atVdd = 0.5 V.

Fig. 8. Material engineering for lower OFF-current (a) IOFF as a functionof TCfe and Ec. IOFF reduces with increasing Tfe or Ec. (b) Hysteresisbegin to show up as Tfe increases, therefore it should be carefully chosenfor hysterics free operation.

Therefore, changing Cp or Vdd will not help, Vfe,c should beincreased either by increasing Tfe or Ec. Fig. 8(a) shows IOFF

for a different Tfe and Ec, and as expected it decreases withincreasing Tfe and Ec. However, one has to be careful sincethis can lead to hysteresis [18] as FE capacitance also changeswith Tfe and Ec. An example simulation is shown in Fig. 8(b),where drain current is plotted for a different Tfe and hysteresisis observed for thicker Tfe. In present case, Ec = 1.15 MV/cmfor Tfe = 1.8 nm (Vfe,c = −207 mV) gives desired IOFF

AGARWAL et al.: DESIGNING 0.5 V 5-nm HP AND 0.23 V 5-nm LP NC-FinFETs WITH IMPROVED IOFF SENSITIVITY 1215

Fig. 9. (a) Ids − −Vgs of both the designed NC-FinFET in forward andreverse sweep. Devices do not show hysteresis. (b) Fluid swing behavior:SS is higher than that of baseline device in the deep subthreshold regionand much lower than 60 mv/decade in the subthreshold region. Thismakes IOFF less sensitive to the threshold voltage variation.

Fig. 10. One single designed NC-FinFET achieves the IRDS 5-nm HPand LP ION targets at Vdd 0.5 V and 0.23 V, much lower than the 0.65 Vtarget while both achieve <100 nA/μm IOFF.

for LP technology. For both the designs (Ec = 0.96 and1.15 MV/cm), hysteresis free operation is achieved, as shownin Fig. 9(a). Furthermore, when Vdd is scaled to 0.23 V,

target LP ION = 629 μA/μm is achieved. While the firstdesign (Ec = 0.966 MV/cm) misses the OFF-current target,the second design achieves it. Thus, the same NCFET whenoperated at Vdd = 0.5 V meets the HP targets (in fact, it beatsthe OFF-current target) and when Vdd is scaled to 0.23 V,meets the LP ION and IOFF. Additionally, the designed NCFETevince fluid SS behavior in Fig. 9(b), as SS is higher than thatof baseline device in the deep subthreshold region while itis below 60 mv/decade in the subthreshold region. Fig. 10summarizes that the NC-FinFET can meet the 5-nm targets atmuch lower Vdd than 0.65 V.

V. CONCLUSION

NCFET provides not only internal gate voltage amplifica-tion but also other opportunities to optimize the transistors.We showed how to reduce the sensitivity of IOFF to Vthvariation while obtaining large ION. Using 5-nm HP devicesusing Vdd = 0.5 V and LP device using Vdd = 0.23 V (whileIRDS projection is 0.65 V for both devices), we showed howto achieve device target by choosing parasitic capacitancesand FE Ec. These examples illustrate that NCFET excelsin the future very LP and high-performance applications.We demonstrated that fluid swing with larger SS at Vg = 0may be the best design.

ACKNOWLEDGMENT

This paper was partially supported by members of theBerkeley Center for Negative Capacitance Technology and theBerkeley Device Modeling Center.

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Harshit Agarwal (M’17) received the Ph.D.degree from IIT Kanpur, Kanpur, India.

He is currently a Post-DoctoralResearcher/Manager with the Berkeley DeviceModeling Center, BSIM Group, University ofCalifornia at Berkeley, Berkeley, CA, USA.His current research interests include themodeling and characterization of advancedsteep subthreshold-slope devices, logic andhigh-voltage devices, FinFETs, and GAA FETs.

Pragya Kushwaha (M’17) received the Ph.D.degree from the Department of Electrical Engi-neering, IIT Kanpur, Kanpur, India.

She is currently a Post-Doctoral Researcherwith the BSIM Group, University of Californiaat Berkeley, Berkeley, CA, USA. Her currentresearch interests include the modeling, sim-ulation, and characterization of semiconductordevices, such as nanowire, NCFET, PD/FDSOI,FinFET, tunnel FET, high-voltage FET, and bulkMOSFET.

Juan Pablo Duarte (S’12) received the B.S. andM.S. degrees in electrical engineering from theKorea Advanced Institute of Science and Tech-nology, Daejeon, South Korea, in 2010 and 2012,respectively, and the Ph.D. degree in electricalengineering from the University of California atBerkeley, Berkeley, CA, USA, in 2017.

Yen-Kai Lin (S’15) received the B.S. degreein physics and the M.S. degree in electronicsengineering from National Taiwan University,Taipei, Taiwan, in 2013 and 2014, respectively.He is currently pursuing the Ph.D. degree inelectrical engineering with the University ofCalifornia at Berkeley, Berkeley, CA, USA.

Since 2015, he has been with the BSIM Group,University of California at Berkeley. His currentresearch interests include semiconductordevices physics, compact modeling, andsimulation.

Angada B. Sachid (M’17) received the Ph.D.degree in electrical engineering from IIT Bombay,Mumbai, India, in 2010.

He is currently a Post-Doctoral Researcher withthe Department of Electrical Engineering andComputer Sciences, University of California atBerkeley, Berkeley, CA, USA.

Huan-Lin Chang (M’11) received the Ph.D.degree in electronics engineering from NationalTaiwan University, Taipei, Taiwan, in 2011.

He was with the SPICE Team, Taiwan Semi-conductor Manufacturing Company, Hsinchu,Taiwan, from 2011 to 2015. He was a Post-Doctoral Researcher with the BSIM Group, Uni-versity of California at Berkeley, Berkeley, CA,USA. His current research interests include com-pact modeling of the semiconductor devices.

Sayeef Salahuddin (SM’14) received the B.Sc.degree in electrical and electronic engineeringfrom the Bangladesh University of Engineeringand Technology, Dhaka, Bangladesh, in 2003,and the Ph.D. degree in electrical andcomputer engineering from Purdue University,West Lafayette, IN, USA, in 2007.

He joined the Faculty of Electrical Engineeringand Computer Science, University of Californiaat Berkeley, Berkeley, CA, USA, in 2008.

Chenming Hu (LF’16) is currently a Distin-guished Professor Emeritus with the Universityof California at Berkeley, Berkeley, CA, USA.He is also a Board Director of SanDisk Inc.,San Jose, CA, USA, and the Friends of Childrenwith Special Needs, Fremont, CA, USA.