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Microelectronics Journal 41 (2010) 430–439

Contents lists available at ScienceDirect

Microelectronics Journal

0026-26

doi:10.1

n Corr

E-m

journal homepage: www.elsevier.com/locate/mejo

Designing a compact soft-start scheme for voltage-modeDC–DC switching converters

Sizhen Li n, Xuecheng Zou, Xiaofei Chen, Quan Gan

Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China

a r t i c l e i n f o

Article history:

Received 15 August 2009

Received in revised form

23 April 2010

Accepted 3 May 2010

Keywords:

DC–DC switching converter

Soft-start scheme

Inrush current

Digital-controlled current limitation

DAC

92/$ - see front matter & 2010 Elsevier Ltd. A

016/j.mejo.2010.05.001

esponding author. Tel.: +86 13545119211.

ail address: lisizhen@gmail.com (S.Z. Li).

a b s t r a c t

In this paper, a compact soft-start scheme is proposed and successfully applied to typical voltage-mode

DC–DC switching converters. The adaptive current limitation implemented through DAC control will

largely reduce the overshoot voltage under a wide range of output current. Proven experimentally by a

buck converter implemented in a 0.5 mm CMOS technology, the post-simulation results show that when

the converter starts up, the maximum overshoot (2.7% at ILOAD¼0 A) by the proposed soft-start scheme

is less than that with the conventional scheme by 5% under the same condition. The start-up time can

be adaptively adjustable depending on load current and the maximum start-up time is around 760 ms

with 22 mF output capacitor. The circuits which realize the soft-start scheme can also be fully integrated

into the control chip of DC–DC switching converter resulting in low cost.

& 2010 Elsevier Ltd. All rights reserved.

1. Introduction

DC–DC switching converters are widely used in portableelectronic device for high efficiency and low power consumption[1]. In the DC–DC switching converter, during start-up, the largeinrush current and the overshoot of the output voltage willdamage the inductor and induce stability problem. As a result,soft-start scheme is normally adopted to eliminate the inrushcurrent and reduce the overshoot voltage [2–4].

There are two types of soft-start implementation, one isthrough voltage-mode method; the other is by current-modemethod. At present, voltage-mode method has been widely usedin industrial catalog products for its simplicity [5,6]. However,most voltage-mode soft-start circuits need an external capacitorto regulate the soft-start time and the inrush current cannot belimited directly. It leads to cost increase and potential damage-risk in external components. The current trend of integratingnumerous LDOs and switched-mode regulators and controllers onthe same system-on-chip PMIC, each with its own start-up andpower-up sequencing requirements, necessitates the design of acompact fully integrated soft-start circuit with higher safetyrequirements for low cost considerations [7]. As a result, thecurrent-mode soft-start method will be more competent becauseit can directly limit the inrush current and can be fully integratedin the controller chip [8,9]. However, both approaches in [8,9] are

ll rights reserved.

applied in current-mode switching converter and may not beappropriate for the voltage-mode switching converter as there isonly one voltage feedback loop in the voltage-mode DC–DCconverter.

Fig. 1 describes the conventional current-mode soft-startscheme applied to a voltage-mode buck converter [10]. Whenstarts up, the divided voltage of the output is much lower than thevoltage reference Vref, the error amplifier is under unbalancedstate. The output voltage of the error amplifier is at high voltagelevel. If there is not any limitation, the converter works under the100% duty ratio; thus, large inrush current will flow into theoutput capacitor to generate output voltage overshoot.

Current-mode soft-start method senses the current passingthrough the inductor L1 and limits the inductor peak current(ILpeak) through the current comparator to reduce the inrushcurrent. It will generate potential overshoot of the output voltageunder different loads because the current reference is usually setinvariably higher than the typical output current. The outputvoltage Vo and inductor current IL of the converter under the soft-start scheme are shown in Fig. 2.

It can be obtained that the larger overshoot will be generatedat the lighter load and the maximum overshoot occurs at the no-load condition. Moreover, the approach of employing the current-mode soft-start scheme suffers from a dissatisfactory operatingefficiency because of the power dissipated in the current sensor.Besides, the stability problem may also occur if the currentlimitation cannot be controlled fast. So far, there are very fewpapers published relating to the overshoot reduction technologyof current-mode soft-start scheme for voltage-mode switching

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Fig. 1. Conventional current-mode soft-start scheme applied to a voltage-mode buck converter.

Fig. 2. Waveforms of conventional soft-start scheme using constant inductor peak

current (ILpeak) control under: (a) full load; (b) no load.

S.Z. Li et al. / Microelectronics Journal 41 (2010) 430–439 431

converter, especially current-mode soft-start scheme withreduced current-sense power consumption and improved stability.

In this paper, an improved current-mode soft-start schemethat offers overshoot reduction is proposed. Thanks to the digital-controlled current-limitation, the overshoot is largely reducedunder a wide range of load currents. An innovative digital-controlled current sensor, which features with simplicity isproposed to reduce the power dissipation. Besides, fast compara-tor with clamping function and the driver with dedicated controlcontribute to the high stability.

The proposed scheme is realized using transistor level. Thesoft-start circuit is fully integrated and applied to a voltage-modebuck converter in our design. It should also be noted that

the proposed scheme is not limited to buck converter butcan be extended to voltage-mode DC–DC converter ingeneral. In Section 2, the principle of the scheme and the designof the circuits are presented in detail. The experimental resultsare discussed in Section 3. Finally, the conclusion is given inSection 4.

2. Proposed soft-start scheme

2.1. Structure and operational principle

Based on the principle of the conventional current-mode soft-start scheme, an improved soft-start scheme using DAC techniqueis proposed and applied to a voltage-mode buck converter asdescribed in Fig. 3. The signal NPWM is generated from PWM

comparator as shown in Fig. 1. The current reference (IREF) isconverted to voltage V1. Different from constant ILpeak controlgiven in Fig. 1, the principle of the proposed soft-start scheme isto have the current reference IREF rise step by step as shown inFig. 4, and thus the inductor peak current (ILpeak) can be limited bystages. The purpose is to reduce the overshoot voltage underdifferent loads to a great extent.

During start-up, the output signal Nsoft of the currentcomparator and the oscillator output signal CLK are used to liftthe output voltage. The upper edge of the signal CLK turns thepower transistor M1 on and the upper edge of the signal Nsoft turnsM1 off. During normal state, the output signal NPWM of the PWM

comparator and the signal CLK are used to realize feedback controlto regulate the output voltage. Fig. 4 describes the soft-start keywaveforms under full load and no load.

EN is the enable signal of the counter. When EN is set to logichigh, the soft-start function starts working. The switchingfrequency of power transistors is fs (fs¼1/Ts), which is the sameas that of oscillator. The nc-bit counter calculates the switchingcycles of power transistors. The high bits of the counter(Qnc�2Qnc�1) are used to generate the output codes D0D1D2, whichare the inputs of the DAC.

As shown in Fig. 4a, it can be obtained that

T1 ¼ ð2nc�2�1ÞTs, ð1Þ

T2 ¼ T3 ¼ 2nc�2Ts, ð2Þ

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Fig. 3. Simplified schematic of the synchronous voltage-mode buck converter with the proposed soft-start scheme.

S.Z. Li et al. / Microelectronics Journal 41 (2010) 430–439432

and the maximum counting period is

TCOUNT ¼ T1þT2þT3 ¼ ð3� 2nc�2�1ÞTs: ð3Þ

When codes D0D1D2 are ‘000’, ‘001’, ‘011’, ‘111’ in turn, thecurrent passing through the resistor R1 (IREF) rises in steps of 4Ia,8Ia, 12Ia, 16Ia.Thus, the output V1 is described as

V1 ¼ Vin�IREFR1: ð4Þ

The power transistor M1 works in the deep linear region, theresistance is defined as RON. In our design, the inductor current issampled through sensing the voltage Vsw, which will be discussedlater. Suppose that during sampling, the current passing throughthe inductor is IL, the output V2 is given by

V2 ¼ Vin�ILRON : ð5Þ

Set V1¼V2; from Eqs. (4) and (5), it can be derived that

ILpeak ¼IREFR1

RON

¼ ILpeak1 ¼4IaR1

RON, 0otot1,

¼ ILpeak2 ¼8IaR1

RON, t1otot2,

¼ ILpeak3 ¼12IaR1

RON, t2otot3,

¼ ILpeak4 ¼16IaR1

RON, t4t3

ð6Þ

From the above discussion, when the sensed inductor currentIL reaches the value of ILpeak, the signal Nsoft changes the state fromlogic low to logic high such that the power transistor M1 turns off.That is, the inductor peak current is limited step by step duringsoft-start stage.

Moreover, we propose the circuit which senses the outputvoltage Vo. As Vo climbs higher than the typical value Vtyp, thecontrol signal LD goes logic high to set code D0D1D2 to ‘111’ to endthe soft-start.

As shown in Fig. 4, the start-up time mainly depends on theload current. The lighter the load is, the more charge will transferto the output capacitor during start-up and Vo will reach to thetypical value Vtyp faster. Thus, with the decrease in load currentsoft-start time is reduced. On the other hand, during soft-startperiod, the average inductor current higher than the load currentis used to enhance the output voltage, and in normal state, theaverage inductor current equals to the output current. In thatcase, when transition happens from soft-start phase to normalphase, the extra current will flow to the capacitor to charge and

result in voltage overshoot. The overshoot can be estimated by

DV ¼Q L�Q R

Cð7Þ

where C is the value of the output capacitor, Q L the charge storedin the inductor, QR the charge transferred to the load. In Eq. (7), Q L

is proportional to the predetermined value of ILpeak. In conven-tional current-mode soft-start scheme, ILpeak is set constant andhigher than the full current. Thus, the overshoot will approxi-mately linearly increase as the load current decreases. In ourproposed scheme, the ILpeak is set constant at different valuesunder different load current ranges. Therefore, the differencebetween QL and QR is reduced and the overshoot has been largelyreduced. Theoretically, the more the current step is, the less theovershoot will be obtained. However, solution with too manysteps will make the circuit implementation complicated andincrease the manufacture cost. Thus, the ILpeak is designed in stepsof typically ILpeak4/4, ILpeak4/2, 3/4ILpeak4 and then the typicalcurrent limit ILpeak4 is 1.6 A in our experiment under which thefull-load current is 1.3 A. At 1.25 MHz switching frequency, a10-bit counter is adopted to ensure the a smooth soft-start [11].For different applications, the value of ILpeak can be tuned intoother value.

2.2. Current sensor

Among many current sensing techniques, we propose thedigital-controlled current sensor which features with simplicity[12,13]. The circuit is given in Fig. 5. The current-sense function isrealized through sensing the voltage Vsw and is controlled by thesignal N2 generated from the driver shown in Fig. 3. The voltagesignal V2 is the output of the current-sense circuit and thecapacitor is used to stabilize the output voltage as illustrated inFig. 5a. Vsw is controlled by the gate driving signals Vp and Vn,which are the outputs of the driver. The voltage Vsw has largetransient change, which may induce large burr in V2. To removethe burr, delays between Vsw and N2 are introduced in our designas described in Fig. 6. In addition, to eliminate the noise of thesignal Nsoft, which is the output of the current comparator asdescribed in Fig. 3, feedback is used to control the output voltageV2 of the current-sense circuit. When NsoftN2 is ‘11’ that denotesover-current is detected and current-sense is disabled, thetransistor MP4 turns on and quickly steps up the voltage V2 tomake the signal Nsoft return to ‘0’. When Nsoft returns to ‘‘0’’, NsoftN2

is ‘01’, MP5 turns on to boost the voltage V2 to Vin waiting for thenext sensing time. The simple and delicate design eliminatesthe potential large burr in V2 and the noise of the signal Nsoft.

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Fig. 4. Soft-start key waveforms under: (a) full load and (b) no load.

S.Z. Li et al. / Microelectronics Journal 41 (2010) 430–439 433

It ensures the effectiveness of the current sensor withapproximate zero DC power consumption. Simulation results asgiven in Fig. 7 show that the sampling delay td2 is around 10 nsand td1 is around 7 ns, which are adequate to remove the largeburr appearing in V2.

2.3. Current comparator

The comparator is used to generate the over-current signal.Fast response is needed to increase the control speed of the soft-start stage. This comparator, shown in Fig. 8, is implemented by a

differential input stage, a folded cascode stage and a clampingstage [14]. The gain of the differential input stage is given by

gmðM1,2Þ R1,2==1

gdsðM1,2Þ

!, ð8Þ

and the gain of the cascode stage is

gmðM5,6Þ

1

gdsðM11Þ

==1

gdsðM9Þ

ðgmðM9Þ þgmbðM9ÞÞ

1

gdsðM6Þ

==R4

� �� �� �: ð9Þ

In Eqs. (8) and (9), gm and gds denote transconductance andoutput conductance of a transistor, respectively. The accuracy of

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Fig. 5. Current-sense circuit (a) the schematic (b) the logic.

Fig. 6. The timing of Nsoft, N2 and Vsw.

Fig. 7. The simulated results of Nsoft, N2, Vsw and V2.

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the comparator is improved through high-gain amplificationstage. It will further increase the accuracy of the current sensor.The clamping circuit is adopted to increase the speed of thecomparator. When the drain voltage of the transistor M9 increasesto the level that can turn on the transistor M16, M16 turns on andthe voltage V1 is limited to V2þVSGðM16Þ

. When the drain voltage ofthe transistor M9 decreases to the level that can turn on thetransistor M15, M15 turns on and the voltage V1 is clamped to

V3�VGSðM15Þ. The output stage is used to increase the response of

the comparator output signal.The simulation results are shown in Fig. 9. The 3.6 V direct

current voltage is put on the input in+. The rectangle pulse with500 ns width is connected with the input in� . For the case withoutclamping, the voltage V1 varies between 0 and 3.6 V. When theclamping circuit is added, the range of V1 is from 0.7 to 2.7 V.

The simulation results show that the delay time has beenreduced by 22% when the clamping stage is added.

2.4. Driver

In our design, a driver with delicate control is necessary toprovide buffer and dead-time control. Buffer and dead-timecontrol are needed to avoid shoot-through current loss, which isone kind of power losses in the switch mode converter [15].Fig. 10 shows the driver applied in our design. When Q is high, Vn

is set to zero, power transistor M2 turns off. Through the feedbacksignals at Vn and A1, Vp is forced to zero, power transistor M1 turnson. Similarly, when Q is low, Vp is set to increase; power transistorM1 turns off. Through the feedback signals at Vp and A2, Vn isforced to increase; power transistor M2 turns on. The basicprinciple is to use the feedback signals to control the gate drivingsignals such that the power transistors M1 and M2 do not turn onsimultaneously. The feedback signals at A3, A4, A5, A6 are used todecrease the time needed for the gate voltage of M1 and M2 to riseand fall and to avoid the case that M3, M4 and M5, M6 turn onsimultaneously. The simulation results show that the rise and falltimes of Vp are only about 5 and 5 ns, respectively, while those ofVn are only about 10 and 20 ns, respectively, and the dead-time isabout 30 ns in this design. Moreover, the driver generates thesignal N2 to control the current sensor. From the schematic inFig. 10, delay time exists between N2 and gate driving signals Vp

and Vn, which control the voltage Vsw. It results in that td1 and td2

can be observed as shown in Fig. 7. In addition, a signal MNoff isalso introduced to turn off M2 at light load to improve efficiency,which will be discussed later.

2.5. System implementation

Fig. 11 shows the overall system. The proposed soft-startcircuit and power transistors have been integrated in the controlchip of a DC–DC voltage-mode buck converter to reduce the cost.During start-up, the controller uses the output signal Nsoft of thesoft-start circuit and oscillator output signal CLK to lift the outputvoltage. As Vo reaches the typical value, soft-start function stopsworking. During normal state, the signal NPWM and CLK are used torealize feedback control. The divided voltage of Vo (Vfb) is sensedby Error amplifier (EA). The output voltage of EA (Ver_out) iscompared with saw tooth generator’s output signal Vramp to

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Fig. 8. Current comparator.

Fig. 9. Waveforms of the comparator (a) without clamping and (b) with clamping.

S.Z. Li et al. / Microelectronics Journal 41 (2010) 430–439 435

generate NPWM. The upper edge of the signal CLK turns M1 on andas soon as Vramp exceeds Ver_out, M1 is turned off. Under thecontrol, the output voltage is regulated at a stable value. Thebandgap reference and bias circuits are included to generatevoltage and current references of the controller chip. Moreover,zero current detector (ZCD) is introduced to prevent inductorcurrent from going negative at the boundary of continuousconduction mode (CCM) and discontinuous conduction mode(DCM). This ZCD function can prevent the output capacitordischarge, which will reduce the efficiency of converter. Thefunction of ZCD is to generate the signal MNoff to turn off M2 (M1 isclosed already) when IL reaches zero [16].

3. Results and discussions

The proposed soft-start circuit has been applied in a synchro-nous DC–DC voltage-mode buck converter with a standard 0.5 mm

CMOS process. Fig. 12 shows the layout of the proposedcontroller. Its effective die area is 1.38 mm�0.90 mm, includingpads and ESD structures. Table 1 summarizes the post-simulationresults for the main specifications of the proposed converter.All these features show that it is suitable for portable electronicdevices, which are powered by battery. The proposed soft-startcircuit occupies 0.06 mm2 on silicon, which corresponds toabout one twentieth of the total area of controller. Although thesoft-start circuit introduces 53.5 mA quiescent current, it addscurrent-limiting function, which increases the reliability of thesystem.

In order to verify the proposed soft-start technique, experimentshave been performed to check the overshoot voltage. Theinput voltage of the converter is set to nominal value, which is3.6 V.

Fig. 13 shows the post-simulated key waveforms with theproposed soft-start scheme under no load and full load. Signal LD

is the internal signal of the soft-start circuit described in Fig. 3.

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Fig. 10. Schematic of the driver.

Fig. 11. Block diagram of overall system.

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The results show that during soft-start, the inductor peak currentis limited step by step. The clock signal CLK and the output signalNsoft of the soft-start circuit control the switching of the powertransistors to transfer energy to the output. As soon as the outputvoltage climbs to Vtyp, which is 1.8 V in our design, LD will changefrom logical low to high to end the soft-start process, and whenthe converter enters in the normal state, CLK and the output signalNPWM of the PWM comparator control the switching of the powertransistors. The results show that the start-up time can beintelligently adjustable by load current. The switch current is

designed in steps of typically ILpeak4/4, ILpeak4/2, 3/4ILpeak4 and thenthe typical current limit ILpeak4 is 1.6 A. The lighter the load is, theless the start-up time is. The maximum start-up time of theconverter is around 760 ms with 22 mF output capacitor under1.3 A load current. The HSPICE simulation results show that theoutput voltage can stably start-up until the output voltage sets up.

A comparison of start-up process is made using two soft-startmethods. Fig. 14 shows the post-simulated output voltage andinductor current of the same voltage-mode buck converter underconventional current-mode soft-start method described in Fig. 1.

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Fig. 12. The layout of the proposed converter.

Table 1Overall chip performance.

Parameters Results

Input voltage range (Vin) 2.6–5.5 V

Output voltage 1.8 V

Maximum output current 1.3 A

Efficiency 92% (max at Vin¼3.6 V, Vo¼1.8 V, ILOAD¼300 mA)

External inductance L1 4.7 mH

External capacitance C1 22 mF

External divided resistors 470 KO for R1; 180 KO for R2

Switching frequency 1.25 MHz

Ripple voltage 30 mv (PWM)

MOSFET model BSIM3V3 model (Normal Voltage)

MOSFET sizing 0.60 mm�0.80 mm

Rds (PMOS) 0.3 O (at VGS¼3.6 V)

Rds (NMOS) 0.2 O (at VGS¼3.6 V)

Input DC bias current 350 mA

DC bias current of soft-start circuit 53.5 mA (16 mA of DAC-controlled current reference; 37.5 mA of current comparator)

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As a remark, the typical current limit ILpeak is also set to 1.6 A, whichis realized through fixing the high bits of the counter (Qnc�2Qnc�1)‘11’ during the whole soft-start process in our design. The resultsshow that the output voltage can stably start-up under full load.However, when the load current decreases, especially when the loadcurrent is zero, output voltage overshoot becomes large.

To further verify the improvement in the proposed soft-starttechnique. A comparison of overshoot is made using twosoft-start methods mentioned above. Fig. 15 shows thesimulated overshoot of the output voltage as a function of theoutput current. The overshoot curve ‘‘a’’ is obtained based onthe proposed soft-start scheme. The overshoot curve ‘‘b’’ isobtained when the conventional current-mode method isapplied. The maximum overshoot (2.7% at ILOAD¼0 A) by thenovel soft-start scheme is less than that with the conventionalscheme by 5%. The results show that the overshoot voltage hasbeen largely reduced in a wide range of load currents.

Therefore, experiments are in good agreement with the theoreticalanalysis that introducing DAC-controlled soft-start circuit caneffectively reduce the output voltage overshoot of the converter andensure smooth output voltage when the converter starts up.

4. Conclusion

This paper presents a compact soft-start scheme applied tovoltage-mode DC–DC converters. Compared to conventionalconstant ILpeak control, DAC-controlled ILpeak control is adoptedto largely reduce the overshoot voltage. The soft-start circuitincluding low-power current sensor, fast current comparator anddriver with delicate control has been designed and fullyintegrated. The proposed soft-start scheme has been successfullyimplemented and verified with a buck converter in a 0.5 mmCMOS technology.

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Fig. 13. Post-simulated key waveforms with the proposed soft-start scheme with 22 mF output capacitor: (a) ILOAD¼1.3 A and (b) ILOAD¼0 A.

Fig. 14. Post-simulated Vo and IL with the conventional soft-start scheme with

22 mF output capacitor: (a) ILOAD¼0 A and (b) ILOAD¼1.3 A.

Fig. 15. The overshoot of the output voltage by the two soft-start schemes under

different output currents.

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