Designing of a D Flip-Designing of a D Flip-FlopFlop

Final ProjectFinal ProjectECE 491ECE 491

ObjectivesObjectives

To familiarize with the function of the D flip- flop and it's operation.

To Draw the schematic and the layout with clocked input

Perform DRC check and generate LVS To do the simulation and observed the

output waveforms To Vary the output load(1pf to 5pf) and observed

outputs

D Flip Flop (Specification)D Flip Flop (Specification)

A signal input and a clock signal is used AMI-0.6micron process is usedWp=7.5 u, Wn= 3.0 u, Ln=Lp=0.6uPre and Post-layout simulations using

spectraRise time, Fall time and propagation delay

increase for the loading effects

Why DFFWhy DFF

Preferred type for integrated circuit applications (DFF)

S-R flip flop has indeterminate state when both inputs are high

The JKFF simplifies the RSFF truth table but keeps two inputs.

Symbol Symbol

CLK

D

Q

QB

DFF

LayoutLayout

InverterAnd Nor And Nor

Q

QB

SchematicsSchematics

ANDNOR

NAND

INVERTER

ResultsResults

DelayDelay

Without loadWithout load

Loading EffectLoading Effect

Negative Edged TriggerNegative Edged Trigger