designing traction inverters with the ucc5870-q1 · 2020. 6. 26. · powertrain | three-phase...
TRANSCRIPT
Presented by: Audrey Dearien
Texas Instruments
Designing traction inverters with the
UCC5870-Q1
Agenda
• HEV/EV system architectures
• Traction inverter overview and failure modes
• UCC5870-Q1 integrated features and protection mechanisms
• Summary
2
Agenda
• HEV/EV system architectures
• Traction inverter overview and failure modes
• UCC5870-Q1 integrated features and protection mechanisms
• Summary
3
HEV/EV systems | hybrid vehicles
4
Transmission
Electric Motor
3-phase inverter /
rectifier
Battery
Fuel
ICE
Generator
Transmission
Electric Motor
3-phase inverter /
rectifier
Battery
Fuel
Mechanical Coupling
ICE
Transmission
Electric Motor
3-phase inverter /
rectifier
Battery
Fuel
Generator
Mechanical Coupling
ICE
(a) (b) (c)
HEV/EV systems | electric vehicles
5
Battery
EM EM
EM
Differential
Battery
EM EM
EM EM
Battery
EM
Differential
EM
Differential
(a) (b) (c)
HEV/EV systems | EV block diagram
6
Electric
Motor /
Generator
Traction
Inverter
HV Li-ion
Battery
DC/DC
Converter
12-V Board
Rail
LV 12-V
Battery
AC/DC
Converter
(PFC+PLC)
Battery
Monitoring/
Management Infra
stru
ctu
re / C
ha
rgin
g S
pot
Controllers
(MCU, PMIC, etc.)
On-BoardCharger
DC/DC
Converter
Agenda
• HEV/EV system architectures
• Traction inverter overview and failure modes
• UCC5870-Q1 integrated features and protection mechanisms
• Summary
7
EV powertrain | traction inverter block diagram
8
M
Pos.
Position
Sensing
Temperature
Sensing
DC Bus
Voltage
Sensing
HS DriverHS DriverIsolated HS
Driver
HS DriverHS DriverIsolated LS
Driver
MCU
PMICIsolated Bias
Supply(s)
Signal
Isolation
Temperature
SensingTemperature
Sensing
Isolation Barrier
Current
Sensing
Shoot-
through
protection
and RESET
control
HV Battery
Voltage
Sensing
CAN Bus
IGBT
Modules
VCE
Monitoring
Short-Circuit
Monitoring/
Protection
Signal
Isolation
DC-link
Capacitor
Controllers
Isolation
Power conversion transistors
Protection and monitoring
Critical control feedback and
motor monitoring
Powertrain | three-phase traction inverter
9
VDC+
S1
S2
S3
S4
S5
S6
A
B
C C
B
A
Driver Driver Driver
VDC-
MCU
Driver Driver DriverVoltage / current /
position
MCDC
VGE,S1
VGE,S6
VGE,S3
VGE,S4
VGE,S5
VGE,S2
Traction inverter | failure modes and prevention
10
Agenda
• HEV/EV System Architectures
• Traction Inverter Overview and Failure Modes
• UCC5870-Q1 Integrated Features and Protection Mechanisms
• Summary
11
UCC5870-Q1 | protection and diagnostic features
12
System Impact Associated driver and/or
inverter failures
Potential failure
location(s) UCC5870-Q1 integrated features
Torque
disturbance
Over or under voltage of driver
power supply F1 UVLO, OLVO and interrupt
Unintended
commutation Gate driver pulse width skew F2 or F3 Low-delay capacitive isolation barrier, clock data transmission monitoring
Unintended motor
shutdown / Torque
disturbance
Power switch short circuit F2 or F4 DESAT/OC detection and interrupt, DESAT/OC self-test
Gate shorted to ground or VDD F2 or F3 VGE monitoring and compare to PWM with interrupt
Unintended motor
shutdown
Power switch shoot-through
due to false gate signal or
dv/dt-induced current
F2 Anti-shoot-through logic and Miller clamp (internal or external)
Torque
disturbance
Power switch over-voltage F4 Two-level turn-off and/or soft turn-off, VCE/VDS monitoring using ADC,
VCE clamp
Power switch over-temperature F1, F2, or F4 Integrated ADC with biasing current
Power switch gate oxide
breakdown F2 or F4 Short circuit clamp
Power switch false turn-on
when input power is floating F1 or F2 Active pulldown
Torque
disturbance /
Unintentended
motor shutdown
Power system DC bus
over/under voltage F1 or F4 Integrated ADC
UCC5870-Q1 | protection and diagnostic features
13
System Impact Associated driver and/or
inverter failures
Potential failure
location(s) UCC5870-Q1 integrated features
Torque
disturbance
Over or under voltage of driver
power supply F1 UVLO, OLVO and interrupt
Unintended
commutation Gate driver pulse width skew F2 or F3 Low-delay capacitive isolation barrier, clock data transmission monitoring
Unintended motor
shutdown / Torque
disturbance
Power switch short circuit F2 or F4 DESAT/OC detection and interrupt, DESAT/OC self-test
Gate shorted to ground or VDD F2 or F3 VGE monitoring and compare to PWM with interrupt
Unintended motor
shutdown
Power switch shoot-through
due to false gate signal or
dv/dt-induced current
F2 Anti-shoot-through logic and Miller clamp (internal or external)
Torque
disturbance
Power switch over-voltage F4 Two-level turn-off and/or soft turn-off, VCE/VDS monitoring using ADC,
VCE clamp
Power switch over-temperature F1, F2, or F4 Integrated ADC with biasing current
Power switch gate oxide
breakdown F2 or F4 Short circuit clamp
Power switch false turn-on
when input power is floating F1 or F2 Active pulldown
Torque
disturbance /
Unintentended
motor shutdown
Power system DC bus
over/under voltage F1 or F4 Integrated ADC
VCC2
VREG2
VEE2
Monitor
ADC Core
I/O
Shoot through
protection
VCC / VREG
Monitor
DESAT
OC/SC
PWM+
Isolation
Barrier
M
Pos.
MCU
PMIC
12V Battery
Sensors
PWM-
nFLTx
HV Battery
DC-link
Capacitor
Isolated Bias
Supply
UCC5870-Q1
V_IO
ASC Override
Digital Core
Die to Die Comm
V_Core
PWM
External
Interrupt and
GPIO
xF1
xF3
xF2
xF4
Driver Output
Miller Clamp
Gate Voltage
Monitor
ASC
ASC
Digital CoreSDO
SDI, CLK, nCS
HV Controller
Die to Die Comm
DESAT
OC/SC
ASC_IN
Vx
VCC2 / VEE2
UCC5870-Q1 | inverter block diagram
14
NC
SDO
SDI
nCS
CLK
IN-
ASC_EN
IN+
nFLT1
AI5
VREF
OUTL
GND2
VBST
CLAMP
OUTH
DESAT
VREG2
VCC2
AI4
AI2
AI3
AI1
AI6
VEE2
VCC1
NC
GND1
NC
VEE2
ASC
GND1
nFLT2/DOUT
NC
VREG1
VCECLP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PWM-
PWM+
Shoot-
through
protection
VCC2
VREG2
VEE2
Monitor
Legend
ProtectionDiagnosticsDriver
FunctionSelf-Test
Output
Stage
OC/SC
2-Level /
Soft Turn-off
Miller
clamp
control
Gate
monitor
Digital Core
Digital Core
VCE
Clamp
UCC5870-Q1
ASC
Logic
Diagnostics
TEST
DESAT
VREG2
Isolated Bias
Supply
Isolation
Barrier
MCU
PMIC
CAN Bus
nCS
SDO
12V Battery
V_IOV_Core
To VCC1
SDI
CLK
PWM+
PWM-
nCS
SDO
SDI
CLK
From
PMIC
From
PMIC
ASC
ASC_ENFrom
PMIC
To MCU
To MCU
nFLT1
nFLT2 / DOUT
Miller
Clamp
3 x Power
Stage
To high-side driver
M
Pos.
Motor
position
VDC
Sensing
Phase
Voltage
Sensing
Current
Sensing
To AI2,
4, or 6
HV
Battery
DC-link
Capacitor
Thru ISO
to MCU
To secondary side driver supply inputs
To AI1,
3, or 5
From isolated supply
From isolated supply
From shunt
resistor or other
From temp
sensor or other
From shunt
resistor or other
From temp
sensor or other
HV Safety
Controller
To AI* redundant
VDC meas
Secondary ASC
or other
Secondary ASC
or other
ASC_EN
ASC
From HV
Battery
AI1,3,5
AI2,4,6
AI5,6
Diagnostics
TEST
I/O
Die to Die
Comm
Die to Die
Comm
Die to Die
Comm
Die to Die
Comm
ADC Core
VCC / VREG1 Monitor
VREG1
UCC5870-Q1 | inverter block diagram
15
NC
SDO
SDI
nCS
CLK
IN-
ASC_EN
IN+
nFLT1
AI5
VREF
OUTL
GND2
VBST
CLAMP
OUTH
DESAT
VREG2
VCC2
AI4
AI2
AI3
AI1
AI6
VEE2
VCC1
NC
GND1
NC
VEE2
ASC
GND1
nFLT2/DOUT
NC
VREG1
VCECLP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PWM-
PWM+
Shoot-
through
protection
VCC2
VREG2
VEE2
Monitor
Legend
ProtectionDiagnosticsDriver
FunctionSelf-Test
Output
Stage
OC/SC
2-Level /
Soft Turn-off
Miller
clamp
control
Gate
monitor
Digital Core
Digital Core
VCE
Clamp
UCC5870-Q1
ASC
Logic
Diagnostics
TEST
DESAT
VREG2
Isolated Bias
Supply
Isolation
Barrier
MCU
PMIC
CAN Bus
nCS
SDO
12V Battery
V_IOV_Core
To VCC1
SDI
CLK
PWM+
PWM-
nCS
SDO
SDI
CLK
From
PMIC
From
PMIC
ASC
ASC_ENFrom
PMIC
To MCU
To MCU
nFLT1
nFLT2 / DOUT
Miller
Clamp
3 x Power
Stage
To high-side driver
M
Pos.
Motor
position
VDC
Sensing
Phase
Voltage
Sensing
Current
Sensing
To AI2,
4, or 6
HV
Battery
DC-link
Capacitor
Thru ISO
to MCU
To secondary side driver supply inputs
To AI1,
3, or 5
From isolated supply
From isolated supply
From shunt
resistor or other
From temp
sensor or other
From shunt
resistor or other
From temp
sensor or other
HV Safety
Controller
To AI* redundant
VDC meas
Secondary ASC
or other
Secondary ASC
or other
ASC_EN
ASC
From HV
Battery
AI1,3,5
AI2,4,6
AI5,6
Diagnostics
TEST
I/O
Die to Die
Comm
Die to Die
Comm
Die to Die
Comm
Die to Die
Comm
ADC Core
VCC / VREG1 Monitor
VREG2
NC
SDO
SDI
nCS
CLK
IN-
ASC_EN
IN+
nFLT1
AI5
VREF
OUTL
GND2
VBST
CLAMP
OUTH
DESAT
VREG2
VCC2
AI4
AI2
AI3
AI1
AI6
VEE2
VCC1
NC
GND1
NC
VEE2
ASC
GND1
nFLT2/DOUT
NC
VREG1
VCECLP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PWM-
PWM+
Shoot-
through
protection
VCC2
VREG2
VEE2
Monitor
Legend
ProtectionDiagnosticsDriver
FunctionSelf-Test
Output
Stage
OC/SC
2-Level /
Soft Turn-off
Miller
clamp
control
Gate
monitor
Digital Core
Digital Core
VCE
Clamp
UCC5870-Q1
ASC
Logic
Diagnostics
TEST
DESAT
VREG2
Isolated Bias
Supply
Isolation
Barrier
MCU
PMIC
CAN Bus
nCS
SDO
12V Battery
V_IOV_Core
To VCC1
SDI
CLK
PWM+
PWM-
nCS
SDO
SDI
CLK
From
PMIC
From
PMIC
ASC
ASC_ENFrom
PMIC
To MCU
To MCU
nFLT1
nFLT2 / DOUT
Miller
Clamp
3 x Power
Stage
To high-side driver
M
Pos.
Motor
position
VDC
Sensing
Phase
Voltage
Sensing
Current
Sensing
To AI2,
4, or 6
HV
Battery
DC-link
Capacitor
Thru ISO
to MCU
To secondary side driver supply inputs
To AI1,
3, or 5
From isolated supply
From isolated supply
From shunt
resistor or other
From temp
sensor or other
From shunt
resistor or other
From temp
sensor or other
HV Safety
Controller
To AI* redundant
VDC meas
Secondary ASC
or other
Secondary ASC
or other
ASC_EN
ASC
From HV
Battery
AI1,3,5
AI2,4,6
AI5,6
Diagnostics
TEST
I/O
Die to Die
Comm
Die to Die
Comm
Die to Die
Comm
Die to Die
Comm
ADC Core
VCC / VREG1 Monitor
VREG1
UCC5870-Q1 | inverter block diagram
16
NC
SDO
SDI
nCS
CLK
IN-
ASC_EN
IN+
nFLT1
AI5
VREF
OUTL
GND2
VBST
CLAMP
OUTH
DESAT
VREG2
VCC2
AI4
AI2
AI3
AI1
AI6
VEE2
VCC1
NC
GND1
NC
VEE2
ASC
GND1
nFLT2/DOUT
NC
VREG1
VCECLP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PWM-
PWM+
Shoot-
through
protection
VCC2
VREG2
VEE2
Monitor
Legend
ProtectionDiagnosticsDriver
FunctionSelf-Test
Output
Stage
OC/SC
2-Level /
Soft Turn-off
Miller
clamp
control
Gate
monitor
Digital Core
Digital Core
VCE
Clamp
UCC5870-Q1
ASC
Logic
Diagnostics
TEST
DESAT
VREG2
Isolated Bias
Supply
Isolation
Barrier
MCU
PMIC
CAN Bus
nCS
SDO
12V Battery
V_IOV_Core
To VCC1
SDI
CLK
PWM+
PWM-
nCS
SDO
SDI
CLK
From
PMIC
From
PMIC
ASC
ASC_ENFrom
PMIC
To MCU
To MCU
nFLT1
nFLT2 / DOUT
Miller
Clamp
3 x Power
Stage
To high-side driver
M
Pos.
Motor
position
VDC
Sensing
Phase
Voltage
Sensing
Current
Sensing
To AI2,
4, or 6
HV
Battery
DC-link
Capacitor
Thru ISO
to MCU
To secondary side driver supply inputs
To AI1,
3, or 5
From isolated supply
From isolated supply
From shunt
resistor or other
From temp
sensor or other
From shunt
resistor or other
From temp
sensor or other
HV Safety
Controller
To AI* redundant
VDC meas
Secondary ASC
or other
Secondary ASC
or other
ASC_EN
ASC
From HV
Battery
AI1,3,5
AI2,4,6
AI5,6
Diagnostics
TEST
I/O
Die to Die
Comm
Die to Die
Comm
Die to Die
Comm
Die to Die
Comm
ADC Core
VCC / VREG1 Monitor
VREG1
Agenda
• HEV/EV system architectures
• Traction inverter overview and failure modes
• UCC5870-Q1 integrated features and protection mechanisms
• Summary
17
Summary
18
Full Traction Inverter Design Guide
TI Solutions for Inverter & motor control
UCC5870-Q1 Product Folder on ti.com
Additional Resources Key Points
There are various mechanisms for
failures in a HEV/EV traction inverter
These can be a result of incorrect control
or other mechanical failures
The UCC5870-Q1 can help to detect and
protect against common inverter failure
modes and provides flexibility by way of
SPI configurable parameters