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Presenter NameTitle or job function
Navraj NandraDirector of Marketing Mixed Signal IPTitle or job functionDirector of Marketing, Mixed-Signal IP
Place Company Logo HereDesignWare IP: Industry’s Broadest PortfolioDesignWare IP: Industry s Broadest Portfolio
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$97.8M in IP Revenue2 d L t IP S liUSBUSB PCI PHYPCI PHY DDR3/2DDR3/2 SATASATA XAUIXAUI
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USBUSB PCI PHYPCI PHY DDR3/2DDR3/2 SATASATA XAUIXAUI • 2nd Largest IP Supplier
USBUSB
USB PHYUSB PHY
PCIePCIe
PCIe PHYPCIe PHY
DDR3/2DDR3/2
DDR3/2PHY
DDR3/2PHY
SATASATA
SATA PHYSATA PHY
10G Ethernet
10G Ethernet
XAUI PHYXAUI PHY
10/100/1GEthernet
10/100/1GEthernetUSBUSB
USB PHYUSB PHY
PCIePCIe
PCIe PHYPCIe PHY
DDR3/2DDR3/2
DDR3/2PHY
DDR3/2PHY
SATASATA
SATA PHYSATA PHY
10G Ethernet
10G Ethernet
XAUI PHYXAUI PHY
10/100/1GEthernet
10/100/1GEthernet
AXI or AHB BusAXI or AHB BusArbitration+ Decode+ Control
Arbitration+ Decode+ Control
#1 PCIe, USB Ethernet, & Building Block SolutionsAXI or AHB BusAXI or AHB Bus
Arbitration+ Decode+ Control
Arbitration+ Decode+ Control
Over 500 IP Engineers Total;SRAM-1TSRAM-1T SRAMSRAM ROMROM AXI/AHB
BridgeAXI/AHB Bridge
Micro-Processor
Micro-Processor
WiUSBWiUSBSRAM-1TSRAM-1T SRAMSRAM ROMROM AXI/AHB Bridge
AXI/AHB Bridge
Micro-Processor
Micro-Processor
WiUSBWiUSBOver 500 IP Engineers Total; 250 Mixed-Signal engineersDSPDSP
AXI or AHB BusAXI or AHB Bus
DSPDSP
AXI or AHB BusAXI or AHB Bus
I2CI2C UARTUART GPIOGPIO RTCRTC InterruptControllerInterrupt
Controller
inSilicon, Accelerant, Cascade, TriCn, Virtio, Mosaid
DDRI2CI2C UARTUART GPIOGPIO RTCRTC Interrupt
ControllerInterrupt
Controller
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DDR
Place Company Logo HerePCI E IP C l t S l tiPCI Express IP Complete Solution
Complete PCI ExpressIP Solution
#1 i PCI E IP*• Endpoint• Root port• Endpoint• Root portDigitalDigital
• #1 in PCI Express IP*
• On PCI-SIG integrators list more times than all th IP d bi d
p• Switch/Bridge• Dual Mode
p• Switch/Bridge• Dual Mode
ControllersControllers other IP vendors combined
• First to certification for 130nm, 90nm, 65 nm
• 1.1 (2.5 Gbps)• 2.0 (5.0 Gbps)• 1.1 (2.5 Gbps)• 2.0 (5.0 Gbps)PHYPHY
• Over 70 PHY (PCIe 1.1) design starts to date from 130 nm to 65 nm across multiple foundries2.0 (5.0 Gbps)2.0 (5.0 Gbps)
M tM t
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• More than 250 customers, in over400 products
PCI E 1 1 d 2 0** IP hi i i• Master• Slave• Monitor
• Master• Slave• Monitor
Verification IPVerification IP• PCI Express 1.1 and 2.0** IP shipping in volume production
*Dataquest 2007**Controller
Place Company Logo HereD i W PCI E 2 0 PHY IPDesignWare PCI Express 2.0 PHY IP
• Doubles transfer speed to 5.0 Gb/sBackwards compatible with PCIe 1 1 -10% +10%Nom Supplies– Backwards compatible with PCIe 1.1
– Exceeds electrical specs in areas of SS
pp
margin and receive sensitivity for robust design TT
5Gb/s
robust design• Packaging: flip-chip or wire-bond
FF
• Availability: 65 nm, roadmap 40 nm• Ease of integration Eye diagrams showing robust design over• Ease of integration
– Verilog, LEF, .LIB, GDSII, test vectors
Eye diagrams showing robust design over process, voltage & temperature
g• Built-in diagnostics & ATE
Place Company Logo HereD i W PCI E LEDesignWare PCI Express LE
• Easy upgrade path to PCI ExpressSi l l ( 1) d i t f i l t ti i t ASIC d• Single lane (x1), endpoint for implementation into ASIC and FPGA designs– Examples: existing PCI/PCI-X designs, Express Cards, Ethernet
controllers & wireless hubs• Simplified, easy to use feature set enables 20% area reduction
– Automatic connection of digital controller and PHYAutomatic connection of digital controller and PHY– Reference design included
• Maintains interface compatibility with full featured DesignWare• Maintains interface compatibility with full-featured DesignWare PCIe IP solutionSili d li t• Silicon proven and compliant
Place Company Logo HereD i W USB IP C l t S l tiDesignWare USB IP Complete Solution
Complete USB IP Solution• #1 in USB IP for six years in a row*
• Host, Device• OTG• Host, Device• OTGDigitalDigital
#1 in USB IP for six years in a row• Most Certified
• 300x by customers• LPM, HSIC• Wireless• LPM, HSIC• Wireless
ControllersControllers300x by customers
• 100x by SNPSSili P
NEW!
• nanoPHY• LPM, HSIC• nanoPHY• LPM, HSICPHYPHY
• Silicon-Proven• Over 500M cores shipped
NEW!LPM, HSICLPM, HSIC
M tM t
• Every two days, a chip tapes out w/ DesignWare USB IP
NEW!
• Master• Slave• Monitor
• Master• Slave• Monitor
Verification IPVerification IPg
• First certified USB 2.0 PHYs in 130 to 45 nm130 to 45 nm
* Dataquest 2007 Dataquest 2007
Place Company Logo HereDesignWare USB 2.0 nanoPHY
First to Certification in TSMC 45LP
S ISynopsys, Inc.DWC TSMC 45nm LP HS USB PHYHS USB nanoPHYUSB2.0 High-Speed ComplianceNTSNational Technical SystemsC l er Cit CACulver City, CA
NATIONAL TECHNICAL SYSTEMS
Silicon Out to Certification in 2 Weeks!
Place Company Logo HereDDR PHY: In Any FlavorDDR PHY: In Any Flavor
DDR2/DDRDDR2 performance up to 800 Mbps
DDR2/DDRDDR2 performance up to 800 MbpsDDR2 performance up to 800 MbpsPreferred IP for 512Mb or smaller DRAMsDDR2 performance up to 800 MbpsPreferred IP for 512Mb or smaller DRAMs
DDR2/3-“Lite”DDR2/3-“Lite”Area & feature optimized PHY for up to 1066 MbpsInsurance policy for DDR3Area & feature optimized PHY for up to 1066 MbpsInsurance policy for DDR3p yp y
DDR3/2DDR3/2PHY & controller for up to 1600MbpsComplete in-system calibration capabilityPHY & controller for up to 1600MbpsComplete in-system calibration capabilityComplete in-system calibration capabilityComplete in-system calibration capability
Place Company Logo HereSynopsys Enters Embedded Breakthrough Embedded Memoryy p y
Memory IP Market with NovelicsBreakthrough Embedded Memory
• DesignWare coolSRAM-1T– Up to 3x more dense than SRAM-6T– For chips containing over 50% of embedded memory, it saves up to 20% in p g y, p
die area– Bulk logic CMOS processg p
• Requires no additional manufacturing steps• Reduces wafer manufacturing costs by up to 15% compared to other educes a e a u ac u g cos s by up o 5% co pa ed o o e
SRAM-1T products
• DesignWare coolSRAM– Reduces dynamic power consumption by up to 50% compared to SRAM-6Ty p p y p p– High performance -- Operates at speeds over 1.2GHz on 65nm low power
process on 32Kb cachep
Place Company Logo HereDesignWare® PortfolioDesignWare Portfolio
DesignWareCores
DesignWareSystem-Level
Lib
DesignWareLibrary
VCSVerification
LibCores
Embedded MemoryPCI Express™
AMBA® 3 AXIAMBA 2 0
LibraryLibrary
SystemC™ Transaction-L l M d l
LibraryVerification Suites
AMBA 3 AXIPCI ExpressPCI Express PHYUSB 2.0 OTG, PHYUSB LPM-HSIC
AMBA 2.0DatapathData IntegrityMemory
Level ModelsProcessors: ARM7, ARM9, ARM 11DesignWare Cores:
AMBA 3 AXIAMBA 2 AHBPCI ExpressPCI/PCI-X
SATA Host, PHYEthernet DDR3/DDR2/DDRWi l USB
MemoryBuilding Blocks8051, 6811 uCFoundry Libraries
DesignWare Cores: USB, PCIe, Gigabit Ethernet AMBA bus IP
USB OTGEthernetSATA M M d lWireless USB
Nios II processorXAUIMobile Storage
yVerification IPPowerPCCoolFlux DSPM
PeripheralsPre-Assembled Platforms
Memory ModelsOCPI2CSerial I/OMobile Storage
More…More… Serial I/O
More…
Industry’s Broadest Portfolio From a Single Supplier
Place Company Logo HereThank oThank you
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