detectors & mechanisms controllers (dec/mec)

PACS DEC/MEC 1

PACS IBDR 27/28 February 2002

Detectors & Mechanisms Controllers(DEC/MEC)

J.-M. GillisCentre Spatial de Liège (B)

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Content

• models• design status• interface status• test results• expected performances, budgets• procurement, manufacturing & AIV plan• schedule milestones• product assurance• problems areas & critical items

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Models

SW

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Interconnecting Backplane

DEC1MEC1 DEC2 MEC2

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et Ctrl M

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FM

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Design Status - Hardware• DEC

– CRE I/F updated following modified CRE spec & cryoharness

– SPICE model DEC/CRE I/F, simulated power ON/OFF, noise

– boards design nearing completion ( EM level )– 1355 FPGA operational ( non redundant version )

• link reliability test : > 400000 disconnect/reconnect

– DEC FPGA operational, integrated in DEC SIM for AVM– next tasks :

• testing of DEC SIM in AVM, 100% validation of DEC/MEC I/F• manufacturing of EM boards ( 2 “base” + 4 “dec” )• interface validation ( 13 CRE cluster = 1 supply group @

4K )• FPGA final versions ( with sync and redundancy logic )• integration with OBS, 100% testing of HK & TC

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DEC - FPGA statusIIDR ( 3 CRE proto ) => IBDR ( 13 CRE + 1355 FPGA )

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Design Status - Hardware• MEC : MIM ( Mechanisms Interface Module )

– HK• HK board prototype running, to be updated for T°

sensors, in use for developing low level software

– Grating• grating drive validated on separate test system,

prototype board for EM in design, to be updated for actual DC/DC

– Chopper• chopper drive prototype HW in manufacturing

– Filter wheel• filter wheel drive prototype HW in manufacturing

– Calibration sources• calibration sources drive prototype HW in manufacturing

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Design Status - Hardware• MEC : DSP

– MOSAIC board integrated in AVM, operational– EM prototype hardware running– EM board in fabrication at CRISA– electrical and mechanical interfaces frozen– timing FPGA ( CSL ) validated ( MOSAIC version ) - to be

updated for CRISA board + possible merging with MIM

• DC/DC– architecture designed (1 filter + 1 MEC + 2 relays + 2

DEC)– EM specification done– compliant offer received– manufacturer selected

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Design Status - On Board Software• “High level” layer

– DPU interface tested with simulators ( ongoing )– SPU interface tested with simulators ( ongoing )– BOLC interface not tested– DEC interface tested with software hardware simulator– interface with low level specified– 1355 code to be adapted for CRISA board

• “Low level” layer– Interrupt handler triggered by timing FPGA, jitter spec

OK– readout of HK board validated– motor control, synchronization, black body interface : in

development– code for AVM : representative timing & CPU load

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Development Status - On Board Software

• “High level” size ( in text lines ) – Total lines : 9582

– Non-comment lines : 4965

– C files lines : 3010

– real code lines : 2000

• “Low level” size ( in assembler instructions )– typical application ( grating cryoprototype ) : 240 lines– housekeeping data acquisition ( on Mosaic ) : 20– ISR overhead ( context switch etc... ) : 6– total asm code : 100 instr X 5 cycles X 8192/sec = 23% load

• not included : libraries ( Virtuoso services + 1355 )• current executable size : PM = 20 Kw, DM = 16 Kw

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Development Status - On Board Software• detailed design / prototype coding status

– Sequencer : 100%– DPU communication : 100%– SPU communication : 100% – housekeeping : 100%– DEC communication : 40%

• ready to start integration and test with DEC SIM hardware

– BOLC communication : 40%– Mechanisms control : 30%

• prototype developed outside OBS structure• High/low layers interface specification under review

• coding status– simulator and on board software use same source

code– code configuration control implemented

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Design Status - Mechanical Layout

• SVM accomodation : one box ( similar to BOLC )

• dimensions : (L x W x H) ~ 585 x 320 x 320• connector allocation from cryoharness

specification• preliminary front panel design• preliminary box drawing• board list and updated mass estimate

available• iteration needed with prime

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Interface Status - Overview

DPU

SPU1

SPU2

1355 (LWL)

1355 (SWL)

SPU HK

1355 1355

S/C 1553

DEC2

1355 (LWL) + Sync

DEC1

1355

(SW

L) +

Syn

c

BOLC

1355 + Sync

LWL Ge:GaArray

SWL Ge:GaArray

BolometerArrays

&

Cooler

BOLA

MEC1

MEC2

Cryo-Mechanisms

&

Sensors

PACS FPU

1355

SVM28V

SVMOBT

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Interface Status - ICDs

With... Ref. ICD Status remark S/C - Part A ESA PT-IID-A-04624 100% complete S/C - Part B ESA PT-PACS-02126 50% complete SVM accom. DPU PACS-CL-ID-003 100% complete SPU PACS-CL-ID-004 100% complete BOLC Sap-PACS-CCa-0046-01 95% complete T° control Ge:Ga Det. PACS-MA-ID-002 see CRE Cryoharness PACS-MA-SP-001 100% complete CREs PACS-IM-ID-001 100% complete Grating PACS-CL-ID-002 80% complete Launch lock Chopper PACS-MA-ID-001 100% complete Filter Wheels PACS-KT-ID-006 80% complete algorithm Cal. Srces. PACS-KT-ID-007 80% complete algorithm Temp. Sens. PACS-ME-ID-003 100% complete

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Results achieved / current tests• CRE interface

– measurements done with real CRE @ 4K with DEC proto ( IMEC report available )

– manufacturing cryo test bench ( 13 CRE @ 4K + DEC EM )

• BOLC interface– Spacewire communication design from CEA validated by

CSL– Interface test with BOLC simulator planned 03/2002 (TBC)

• DPU & SPU interfaces– Ongoing : integration testing with software simulators

• Mechanisms– prototype boards ready, low level software in development– tests planned : Grating : done, Chopper TBD, Filter wheel

03/2002, Calibration source 05/2002, Temp sensors TBD

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Performance & Budgets• Data handling : CPU workload 50 % TBC w/AVM

– estimation down, measured some real code, within budget

• Measurement quality : within noise spec in lab– first results with 1 CRE, coming tests with full supply

group

• Mass & dimensions : iteration required w/prime• Power : will probably not decrease

– current estimates : 20 to 67 W depending on mode

Mode Typical power comment

Power on 21W DSP and housekeeping ON, mechanisms and detector arrays OFF

Photometry 22W DSP, housekeeping and chopper ON

( not counting BOLC )

Spectrometry 66W DSP, HK, chopper and grating + Ge:Ga detector arrays

Maximum 67W DSP, HK, chopper, grating and one filter wheel moving + arrays

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Procurement & Manufacturing

Sub-unit Procurement/ Manufacture StatusAVM manufacturing completedDSP Board EM board under fabrication at CRISA (E)

QM/FM boards : ordering soon to startDEC/MEC Boards DEC EM boards : final design / fabrication at CSL

MEC EM boards : prototype boards under testQM & FM boards : ITT planned Spring 2002

Structure (preliminary drawing)Components Active components : ATP to CPPA

Passive components : list not finalizedConnectors ATP to CPPA

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Schedule Milestones

ID Task Name Start Finish

1 Onboard software 04/09/01 15/04/02

2 AVM (digital simulator) 03/09/01 15/04/02

8 EM (1 MEC + 2 DECs - not form-fit) 01/10/01 30/08/02

9 Ext. Procurements 01/10/01 31/05/02

12 Other circuits (CSL) 05/11/01 07/06/02

21 AIV 10/06/02 30/08/02

22 EM delivery to MPE 30/08/02 30/08/02

23 QM (1 MEC + 1/2 DEC - form-fit) 01/10/01 01/08/03

24 Ext. Procurements 01/10/01 23/05/03

25 DC/DC converters QM (Alcatel) 02/09/02 28/03/03

26 DSP Module QM (CRISA) 15/07/02 23/05/03

27 QM part procurement @ CPPA 01/10/01 31/10/02

28 Subcontract 08/03/02 26/05/03

47 CSL AIV 26/05/03 01/08/03

50 FM (2 MEC + 2 DEC) 01/11/02 08/01/04

30/08

S O N D J F M A M J J A S O N D J F M A M J J A S O N D J2002 2003 2004

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Problem Areas / Critical Items• Mass / volume / SVM accomodation

– current estimates above initial IID-B figures - iteration req’d

• Grating encoder readout– CPPA problems ( rad. tolerance ) [ > keep & shield ]

• Cryoharness– not confirmed to spec, awaiting evaluation samples

• mechanism simulators availability

detectors & mechanisms controllers (dec/mec)

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