determination of the trapped charge distribution in scaled silicon nitride monos nonvolatile memory...

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Solid-State Electronics Vol. 34, No. 10, pp. 1083-1089, 1991 0038-1101/91 $3.00 + 0.00 Printed in Great Britain. All rights reserved Copyright © 1991 Pergamon Press plc DETERMINATION OF THE TRAPPED CHARGE DISTRIBUTION IN SCALED SILICON NITRIDE MONOS NONVOLATILE MEMORY DEVICES BY TUNNELING SPECTROSCOPY ANIRBAN ROV'~ and MARVINH. WHITE Sherman Fairchild Center No. 161, Lehigh University, Bethlehem, PA 18015, U.S.A. (Received 29 November 1990; in revised form 7 March 1991) Abstract In this paper an analytical model for extraction of the spatial trapped charge density in silicon nitride has been formulated with amphoteric trap statistics. The model includes the energy distribution of traps in nitride and the time-dispersive tunneling transitions from these nitride traps. We have examined charge loss from sub-100 A nitride films with MONOS memory devices at 110 K at different gate bias conditions. We conclude that by maintaining depletion/weak-inversion at the Si surface, the primary charge loss mechanism is back-tunneling of charge from the nitride traps into the Si bands. The actual charge distribution in the nitride is a function of charge injection and trapping. We have demonstrated that modified Fowler-Nordheim tunneling of electrons into the nitride generates a non-uniform spatial distribution of trapped charge for a spatially uniform trap density in the nitride. I. INTRODUCTION The detrimental aspect of electrically active traps is manifested as device performance degradation of different solid-state device structures. The leakage currents accruing from bulk and semiconductor inter- face traps limit charge retention of dynamic RAM cells, dynamic range, signal/noise ratio and charge transfer efficiency of charge coupled device arrays. Traps in the gate dielectric of MOS transistors lead to logic threshold instabilities of CMOS circuits. Bulk traps in the polysilicon reduces mobility of charge carriers in polysilicon thin-film transistors. In other instances, traps have advantages, e.g. gold has been used as a lifetime "killer" in Si for fast-recovery power rectifiers and oxygen is used for intrinsic gettering of other undesirable impurities in Si. In addition, the efficient charge trapping characteristics of silicon nitride films have resulted in MNOS non- volatile memory devices. One memory state corre- sponds to excess electrons in the silicon nitride, and the other memory state corresponds to excess holes in the silicon nitride. Since traps in silicon nitride are responsible for memory action and charge transport, the microscopic nature of these traps is relevant to a physically consistent description of device behavior. The evi- dence of the nitride film being charged negatively (positively) under charge injection of electrons (holes) from the Si substrate leads to two possibilities: (a) Non-interacting, close-compensating donor and acceptor traps which are present to densities of more tPresent affiliation: WaferScale Integration, 47280 Kato Road, Fremont, CA 94538, U.S.A. than 10mcm 3. A donor trap has two charge states (D~, D °) and an acceptor trap has two charge states (D A , D°). The traps interact with electrons (e-) and holes (h +) independent of each other (see Fig. la). (b) Amphoteric traps which have three charge states D +, D D, D - ) and two transition energies (ErD, ETA). An amphoteric trap interacts with electrons and holes as shown in Fig. lb. From theoretical calculations of Robertson and Powell[l] and the electron spin reson- ance and injection experiments of Fujita and Sasaki[2] and Krick et al.[3], the amphoteric traps in silicon nitride are postulated to arise from a trivalent Si center which offers a single atomistic origin for the nitride traps. In this paper we will present our formulism of the capture and emission processes via amphoteric traps. We will present a new approach to determine the trapped charge distribution in the nitride and apply this method to the memory reten- tion data on a scaled MONOS transistor. The four capture processes and four emission pro- cesses involving the three charge states of an ampho- teric trap can be expressed with two coupled first-order rate equations for the occupancy functions f+ (D + state), f- (D- state) and f0 (D O state): dff+ 0 ~ 0 dt = apvthpvf - e;f + - a+~ Vthncf + +e~f °, (1) d f- = a°vthncP -- e:f- -- a; vthp~f- + e°pf °, (2) dt where Uth is the thermal velocity of the carriers in the o a;,a~- and nitride. For the capture cross-sections ap, a,+ and emission coefficients e 7, e °, e ° and e~, the superscript denotes the charge state and the subscript 1083

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Page 1: Determination of the trapped charge distribution in scaled silicon nitride MONOS nonvolatile memory devices by tunneling spectroscopy

Solid-State Electronics Vol. 34, No. 10, pp. 1083-1089, 1991 0038-1101/91 $3.00 + 0.00 Printed in Great Britain. All rights reserved Copyright © 1991 Pergamon Press plc

D E T E R M I N A T I O N OF THE TRAPPED CHARGE DISTRIBUTION IN SCALED SILICON NITRIDE MONOS

NONVOLATILE M E M O R Y DEVICES BY T U N N E L I N G SPECTROSCOPY

ANIRBAN ROV'~ and MARVIN H. WHITE

Sherman Fairchild Center No. 161, Lehigh University, Bethlehem, PA 18015, U.S.A.

(Received 29 November 1990; in revised form 7 March 1991)

Abstract In this paper an analytical model for extraction of the spatial trapped charge density in silicon nitride has been formulated with amphoteric trap statistics. The model includes the energy distribution of traps in nitride and the time-dispersive tunneling transitions from these nitride traps. We have examined charge loss from sub-100 A nitride films with MONOS memory devices at 110 K at different gate bias conditions. We conclude that by maintaining depletion/weak-inversion at the Si surface, the primary charge loss mechanism is back-tunneling of charge from the nitride traps into the Si bands. The actual charge distribution in the nitride is a function of charge injection and trapping. We have demonstrated that modified Fowler-Nordheim tunneling of electrons into the nitride generates a non-uniform spatial distribution of trapped charge for a spatially uniform trap density in the nitride.

I. INTRODUCTION

The detrimental aspect of electrically active traps is manifested as device performance degradation of different solid-state device structures. The leakage currents accruing from bulk and semiconductor inter- face traps limit charge retention of dynamic RAM cells, dynamic range, signal/noise ratio and charge transfer efficiency of charge coupled device arrays. Traps in the gate dielectric of MOS transistors lead to logic threshold instabilities of CMOS circuits. Bulk traps in the polysilicon reduces mobility of charge carriers in polysilicon thin-film transistors. In other instances, traps have advantages, e.g. gold has been used as a lifetime "killer" in Si for fast-recovery power rectifiers and oxygen is used for intrinsic gettering of other undesirable impurities in Si. In addition, the efficient charge trapping characteristics of silicon nitride films have resulted in MNOS non- volatile memory devices. One memory state corre- sponds to excess electrons in the silicon nitride, and the other memory state corresponds to excess holes in the silicon nitride.

Since traps in silicon nitride are responsible for memory action and charge transport, the microscopic nature of these traps is relevant to a physically consistent description of device behavior. The evi- dence of the nitride film being charged negatively (positively) under charge injection of electrons (holes) from the Si substrate leads to two possibilities:

(a) Non-interacting, close-compensating donor and acceptor traps which are present to densities of more

tPresent affiliation: WaferScale Integration, 47280 Kato Road, Fremont, CA 94538, U.S.A.

than 10mcm 3. A donor trap has two charge states (D~, D °) and an acceptor trap has two charge states (D A , D°). The traps interact with electrons (e-) and holes (h +) independent of each other (see Fig. la).

(b) Amphoteric traps which have three charge states D +, D D, D - ) and two transition energies (ErD, ETA). An amphoteric trap interacts with electrons and holes as shown in Fig. lb. From theoretical calculations of Robertson and Powell[l] and the electron spin reson- ance and injection experiments of Fujita and Sasaki[2] and Krick et al.[3], the amphoteric traps in silicon nitride are postulated to arise from a trivalent Si center which offers a single atomistic origin for the nitride traps. In this paper we will present our formulism of the capture and emission processes via amphoteric traps. We will present a new approach to determine the trapped charge distribution in the nitride and apply this method to the memory reten- tion data on a scaled MONOS transistor.

The four capture processes and four emission pro- cesses involving the three charge states of an ampho- teric trap can be expressed with two coupled first-order rate equations for the occupancy functions f + (D + state), f - ( D - state) and f0 (D O state):

dff+ 0 ~ 0 dt = apvthpvf - e ; f + - a+~ Vthncf + + e ~ f °, (1)

d f - = a°vthncP -- e : f - -- a ; vthp~f- + e°pf °, (2)

dt

where Uth is the thermal velocity of the carriers in the o a ; , a~- and nitride. For the capture cross-sections ap,

a , + and emission coefficients e 7, e °, e ° and e~, the superscript denotes the charge state and the subscript

1083

Page 2: Determination of the trapped charge distribution in scaled silicon nitride MONOS nonvolatile memory devices by tunneling spectroscopy

1084 ANIRBAN ROY and MARVIN H. WHITE

C o m D e n s a t i n a D o n o r - A c c e D t o r

T r a p M o d e l

E m i s s i o n P r o c e s s e s f o r P o s l t l v #

a n d NeClat lve C h a r o e d S t a t e s

e" h + o - h + ~ / x, /

D D D ° D ° = / ~" D :

- o .

D o n o r T r a p A c c e p t o r T r a p

A m p h o t e r i c T r a p M o d Q I

÷ D

/ = 0 ; ¢ \ D e- h + e" h +

D_

EG N __,,.FJJ/-g#~A~fYdY/////~'/~. ( 0 / = ) E T A

( + / 0 ) - - E T D E = 0 ~/ / / / / / / / / / / / /~ / / / / / / / / / / / /~ ,

Fig. 1. Charge states and electron and hole processes for: (a) compensating donor acceptor traps; and (b) amphoteric trap; the transitional energies EjA and ErD are also shown.

A = - ~ E TA

o ~ - - ~ ETD

o O O M

E m i s s i o n P r o c e s s e s f o r

T r a o in t h e N e u t r a l S t a t e

o ~ TA ...................

OOn ~ E T D

o

S 0 N 0 M

Fig. 2. Emmission processes from the amphoteric trap; the two kinds of emission processes are back-tunneling to the Si

and Poole-Frenkel emission to the nitride band.

denotes hole (p) or electron (n) process. Pv(nc) is the hole(electron) density in the valence(conduction) band of the nitride. Note, the occupancy functions satisfy the relation:

f 0 + f + f + = l . (3)

The trapped charge in the nitride is:

pN(x, t) = q N x ( x ) [ f + (x, t ) - f - ( x , t)]

= qNx(x)[I - f ° ( x , t ) - 2 f (x,t)]. (4)

White and Chao[8] have solved the coupled eqns (1) and (2) together with the I-D continuity equation for the case of electron injection and capture-only processes, i.e. emission processes are neglected {Pv,

0 e,,, °}=0 a n d f + (x, 0)= 1 (nitride initially e + , e p , e n

saturated with holes). These solutions are applicable to the erase/write operation of the non-volatile MONOS device structure.

The retention or memory characteristics of the non-volatile MNOS device structures may be studied by considering only the emission (detrapping) pro- cesses, i.e. {Pv, no} =0. In general:

df + d---~ = - e;j '~ + e'°f° ~ - e ; f + ' (5)

d f - d-"~ = - e ; f - + e ° f ° ,~ - e ; f - . (6)

0 e0<<e~ - ' e ; because for: The emission coefficients ep, (a) tunnel emission from the neutral state, the Si conduction(valence) band is aligned with the trap level for hole(electron) emission; and (b) Poole-

Frenkel emission to the nitride band is small because of the additional energy U = ETA--ETo for the neutral state (see Fig. 2). The above approximation decouples the emission equations and the solutions are:

f ÷ ( x , t ) = f + ( x , 0)exp[ -ep (x)t], (7)

f - ( x , t ) = f (x, 0)exp[e,~ (x)t]. (8)

From nitride etch-back experiments of Krick et al.[3] and other workers, the nitride bulk trap density has been found to be uniform. For uniform composition nitrides we shall assume N T ( x ) = N T. Consider the case of electron injection into the nitride layer in the MONOS transistor under positive gate bias. After the programming operation, there are trapped elec- trons in the nitride traps. These electrons undergo back-tunneling transitions to the conduction band of Si and, thereby, discharge the nitride. In the next section we shall formulate a model of the back-tunneling phenomenon and demonstrate that it leads to the determination of the trapped electron distribution after programming. Then, we will pre- sent experimental conditions which result in back- tunneling as the dominant discharge process. Finally, the trapped charge distribution will be extracted from the decay data.

2. MODEL

The last section on amphoteric trap statistics con- sidered discrete energy levels (ETA, Era) for the amphoteric trap. In this section we shall introduce the

Page 3: Determination of the trapped charge distribution in scaled silicon nitride MONOS nonvolatile memory devices by tunneling spectroscopy

Trapped charge distribution in MONOS 1085

energy distribution of the acceptor and donor levels. For simplicity, we shall assume that the energy difference U = E r A - ETD is constant for the dis- tributed energy levels. The joint density of states g(ETA , ETD ) can be expressed as g(ETA, U). The occupancy functions now satisfy the following re- lation:

fu cN U)fi(x, ETA, t)dEtA g(Eta , f i (x , t) = (9)

f~N g(ETA, U)dETA

where i e { + , 0, - } and EGN is the silicon nitride energy band gap. Figure 3 is an energy band diagram for the MONOS structure after being programmed with a positive gate voltage. Electrons are spatially and energetically distributed in the nitride. As dis- cussed in the last section, emission from the neutral state is neglected. We shall only consider back-tunnel- ing from negatively charged traps. Poole-Frenkel or thermally assisted detrapping into the nitride band and the injection of holes to the neutral traps will be excluded since these processes can be suppressed by appropriate experimental conditions (temperature and gate voltage conditions during storage).

The electron back-tunneling from the acceptor levels will be modeled with the tunneling time formu- lation of Lundquist et al.[5]. They have shown (as- suming a 3-D delta function potential for the traps) that the tunneling time constant for trap to band tunneling can be expressed as:

where the WKB approximation and low field expan- sion leads to:

~t°x(gTA) ~ h (EGN - - ETA + ,~NO) 1'2

and

._ . 2 2 x / / ~ ~N [/2'TA ) ~ (ETA)1:2.

h

ZNo is the nitride oxide electronegativity difference. The WKB approximation, together with a low field expansion, has also been employed by Manzini et al.[6] to describe the tunneling discharge of holes in SiO:. Equation (8), modified with the energy distri- bution of the amphoteric traps, may be written as:

f - (x, ErA, t) = f - (x, ETA, 0)

We will now assume the trapping (programming) process is insensitive to the energy distribution of the acceptor level. Thus, f - ( x , EtA, O)=f (x, O) de- scribes the spatial distribution of the negatively charged traps after programming. From electrostatics the threshold voltage VTH(t) for the MONOS transis- tor can be written as:

VTH(t)=c~MS+~ks(Qs+Qit+Qf) C~r q jIe°n f[N u

× N T If+ (x, ETA, t ) - - f - (X, ETA, t )]

t (x, ErA) = t0 exp[~o~ (ETA)XOT] exp [0t N (EvA)x]

= t 0 (EvA) exp [ct N (ETA)X ]

J

S

-.I " x O T x N

X NO

N

\

O \

d "1

OB

(10)

EFG

M

Fig. 3. Energy band diagram for the MONOS structure at zero bias with excess electrons trapped in the nitride; the electron emission processes include thermal excitation from the negative charged state into the nitride conduction band, back-tunneling into the Si conduction band from the nega- tive charged state; there is possibility of hole injection from

the Si to the neutral charge state.

× g(ETA, U)h(x)dx dETA, (12)

where Qs is the charge in the Si, Q. is the interface trap charge at the Si-tunneling oxide interface, Qr is the fixed charge in the tunneling oxide, Ce is the capacitance of the ONO gate dielectric, h(x)=(XN -- X)/EN + XOS/Eo~ and x = 0 denotes the tunnel oxide-nitride interface. We differentiate both sides of eqn (12) with respect to t:

dVTH(t) ('ECN ('.~Nt~f-(x,ETA,t) =qNT | |

3t J u do ~t

xg(ETA, U)h(x)dxdExa . (13)

From eqns (11) and (13), the threshold decay rate becomes:

dVm(t~) - qt IeCNdETAg(EIA, U) t31nt

x [~Nn~(x)h(X)exp[ _t - ]dx (14) Jo t (X, ETA ) t (X, ETA )J '

where n£(x)= NTf-(x,O) is the initial number of spatially-distributed negatively charged nitride traps. The function:

, [ , ] t(x, ETA) exp t(x, ETA)

Page 4: Determination of the trapped charge distribution in scaled silicon nitride MONOS nonvolatile memory devices by tunneling spectroscopy

1086 ANIRBAN ROY and MARVIN H. WHITE

t=1000 s, ETA=3.9 eV, 'Co(ETA) =1.18x10"4s ,

t_....j__ exo [- t__L_ ]=21 .sA et N(ETA) =0.71/A, (x, ETA ) "~ (X, I:TA )

0.4 - -

"I~" 0.3 '..2.

~, 0.2

0.1

, J 0 10 20 30

Nitride d e p t h x (A)

Fig. 4. Spatial dependence of the function:

_ _ t exp[ t ] "C(X, ETA ) Z ; (ETA)

I 40

at time t = 1000s, ETA= 3.9eV, z~ (ETA)=I.18 × 10-4S, ~N(ETA)=0.71 A -I and x' = 21.5 A.

is sharply peaked around x = x ' , where

1 t x ' ( E , a ) = - - l n { - - ) ,

~N (ETA) ~T ~) (ETA) / ]

(see Fig. 4). If we consider the integral:

[ ' ] f x N n T ( x ) h ( X ) e x p dx, I = t Jo Z (x, ETA ) Z (x, ETA )

with the above approximation, then we obtain (see Appendix):

1 I ~ ~N (ETA) n T (x ') h (x ' ) , (15)

where x ' is a function of ETA, viz.

x'(ETA ) = aN (ETA) In

Combining eqns (14) and (15), we have the general expression for the threshold decay rate:

63 VTH(t) f[GN O l n t = - q ,

X g(ETA' U) n~ [ x ' ( E T A ) l f IX' (ETA)] dETA.

~N(EvA) (16)

The above threshold decay rate equation depends on the initial trapped charge distribution in space and energy in the nitride layer. Given the trapped charge distribution in the nitride, one can predict the threshold decay rate of the transistor in storage. Given the threshold decay rate can one determine the trapped charge distribution7 We shall suggest one approach to determine the nitride trapped charge distribution.

Assume a polynomial form for nT (X) i.e.

M n T (X ) = E an, x m .

o

For a given g(ETA , U) function, we may define

feCN g(ETA, U) X '" In dETA. /

du OtN (ETA) Equation (16) can be rewritten as:

d l n t q ~ o

[ a " ~ ( X N + X o B ~ I " - - I }] x --1.,+1 , (17)

L LkEN Eox / EN

where

I ecN g(E.rA ' U) ]o = J u ~---N (-'-ETA5 dETA '

//~'E~'N g(ETA, U) dE ~ 1, = ~Jt.' [aN (ETA)IZ TA/] In t

( ~'EoN g(ETA, U)In[~0(ETA)] dE -U,,, iC-E w }

= l l l l n t - / t o ,

From the experimental V~-~ vs In t data, we obtain a polynomial fit. After differentiating the polynomial we obtain:

8 V ~ u 81n t ~ b,(In t)". (18)

0

We choose N = M and perform coefficient matching for (ln t) t V l = 0, 1,.. M to obtain MA = B, where M is a N × N square matrix, A is a column vector of coefficients ao, a~ . . . . au and B is a column vector with elements bo, b~ . . . . b N. After matrix inversion, we haveA =M-~B.

Thus, the spatial distribution of trapped charges is given by:

M n T (X) = E a, ,x" = A T x , (19)

0

where X=( I x x 2 . . xU) T. Equation (19) represents the trapped electron density in negatively-charged nitride traps. The positively charged traps do not appear in the calculations since their occupancy does not change based on the discussion in the last section. In the next section we shall apply the above method for scaled-down MONOS devices.

3. APPLICATION TO MONOS RETENTION DATA

A MONOS memory transistor with 20 A tunneling oxide, 87 A LPCVD silicon nitride and 50 A steam oxidized blocking oxide was cooled to 110 K. This p-channel transistor was programmed by +10V pulses into the excess electron state (ERASED state).

Page 5: Determination of the trapped charge distribution in scaled silicon nitride MONOS nonvolatile memory devices by tunneling spectroscopy

Trapped charge distribution in MONOS

0 F Programmed with PMONOS 4

! -IOV, los; IOV, lOOms

° t 2° -o -1 1.5 .~ 1.0

0.5 0.0

e- l-.-

- 2 t l i t l l t l i I i l t t l l i l I l i l l l l d 11111 tU l I I t l l l l d I I l t i r t l l t i i l i l l t l I IIIIllll 10-5 10-3 10-1 10 1 10 3

Read delay (s)

1087

Evs M

Q -l .sev (c) ~

(b)

Fig. 5. Biased retention characteristics of a p-channel MONOS transistor with :COT = 20 A, X N ---- 87 ,~ and XoB = 50 A at 110 K; gate voltage during discharge varied from 0--2.5 V. Energy band diagrams correspond to the following conditions at the Si surface: (a) strong inversion; (b) weak inversion or depletion; and

(c) accumulation.

The low temperature suppresses the thermal detrap- ping process. The retention characteristics were ob- tained for different values of gate bias during discharge. In Fig. 5, bias voltage V~ during discharge was varied from 0 to 2.5 V in 0.5 V increments. The decay rate decreases monotonically with increasing bias voltage. Also, for voltages 1-1.5 V, the decay curves are almost identical. We interpret three pro- cesses in order to explain the curves: (a) electron back-tunneling; (b) hole injection from the inversion layer to the nitride traps; and (c) electron injection into the nitride traps from the Si conduction band. Figure 6 is the subthreshold conduction character- istics of the p-channel transistor in Fig. 5 and, thus,

relates the measured threshold voltages (channel cur- rent of 10pA) in Fig. 5 to the weak inversion condition at the surface (Si surface potential g's ~ 1.5 ~bB). The energy band diagrams in Fig. 5 in terms of bias voltages and conditions at the Si surface; viz (a) 0 and 0.5 V curves correspond to strong inversion; (b) 1 and i.5 V curves correspond to weak inversion or depletion; and (c) 2 and 2.5 V curves correspond to accumulation. From the above treat- ment we conclude that i f retention data is obtained by applying a bias voltage during discharge such that the Si surface is maintained in a weak inversion or de- pletion condition then we can interpret the threshold decay to be primarily controlled by trapped charge

Page 6: Determination of the trapped charge distribution in scaled silicon nitride MONOS nonvolatile memory devices by tunneling spectroscopy

1088 ANIRBAN ROY a n d MARVIN H . WroTE

L)

Wafer MT, PMONOS 4

10" 4

10 - 6

10" 8

10" tO

- 12 tO 0

SUBTHRESHOLD CONDUCTION

(472pA,-1.33v)

%1 ~. ",,ll-IP.i I I 1

- 0 . 8 -1.6 - 2 . 4 - 3 . 2 - 4 . 0

Gate Voltage (V) Fig. 6. Channel current as a function of gate voltage for the transistor in Fig. 5 with - 5 V on the drain and source and

substrate grounded.

2x1019 _ T rapped e lec t rons

E T A = 3 . 9 e V

E mN = 0 ' 3 5 m 0

~.~ x 0=6x10 -14 s

o m o x : 0 " 4 9 m o c~ N=8

.~ N=4

"o

I--

I b 0 10 20 30

Nitride depth (A)

Fig. 8. Spatial distribution of the initial electron trapped charge density in the nitride for the data in Fig. 7 for two different orders of polynomial fit N = 4 and N = 8 and

single aeceptor level 3.9 eV.

back-tunneling. Under these conditions the model derived in the last subsection is relevant in determin- ing the trapped charge distribution in the nitride. Note, the low field approximation is also justified. Figure 7 illustrates MONOS transistor biased reten- tion data where the idle voltage V~ is applied to ensure only electron back-tunneling. The initial threshold voltage VT, for the measurement in Fig. 5 is ~0.5 V and for depletion/weak inversion at the Si surface Vc;~ 1-1.5V, which amounts to (V~,-Vv~)~I .5-2V. For the measurement in Fig. 7, VT~=IV, so VG~=3V is chosen to get (V~ - VT~ ) = 2 V. A polynomial fit to the decay curve is also obtained. The results of extracting the spatial initial trapped charge distribution for two different orders of polynomial fit (N = 4, N = 8) and a single energy level are summarized in Fig. 8. The method is relatively insensitive to the degree of polynomial fit. The spatial trapped charge distribution increases

2 --

P r o g r a m m e d with ~" o l0V. 10s; 10V, 10s

o Po lynomia l fit

o Data > 1

o t-

o r-

0 ........ I ..... J ...... l . ,,,,.J ..... .L ..... d ..... d ...... J .... .J ...... J

10 .5 10 -3 10 -1 101 10 3 105

Read delay (s)

Fig. 7. Biased retention data at 110 K and the polynomial fit for the p-channel transistor from Fig. 5 programmed with initial threshold voltage ~ 1.5 V higher than in Fig. 5 and

bias voltage of 3 V.

into the nitride from the tunneling oxide interface and finally saturates around 20 A into the film. Note, the programming action involves modified Fowler- Nordheim tunnel injection of electrons into the nitride with subsequent trapping. Since the capture cross-section of the traps in the neutral state is of the order of 10-14cm217], the centroid of the negatively charged traps is away from the tunnel oxide-nitride interface. We believe that the distribution reflects the trapped charge distribution and not the trap density variation in the film; i.e. non-uniform trapped charge and uniform trap density. This conclusion is contrary to the suggestions of Bernt and Scholtens[8] who have interpreted charge decay in MNOS memory capacitors in terms of charge distributions in the nitride by assuming different functions for the spatial distribution of a trapped charge with subsequent fitting to the experimental data. The quasi-saturation of the trapped charge distribution in Fig. 8 implies that trap density is constant in the nitride, a con- clusion supported by the etch-back experiments of other workers[3].

4. C O N C L U S I O N S

We have modeled the discharge of MONOS devices for the case when the Si surface is maintained in depletion/weak-inversion. The discharge is mod- eled to be primarily due to electron back-tunneling from negatively charged memory traps for an excess electron state. For an arbitrary energetic distribution of amphoteric traps, the spatial distribution of the negatively charged traps in the nitride has been determined. For a 20 A tunneling oxide, 87 A nitride and 50 A blocking oxide memory transistor, + 10 V, 10 s programming at 110 K yields a spatial distri- bution of negatively charged traps, linearly increasing into the nitride bulk from the tunneling oxide inter- face and saturating to about 1019 c m - 3 , 20-30/k into the nitride. The spatial distribution shows a non- uniform trapped charge distribution for a uniform

Page 7: Determination of the trapped charge distribution in scaled silicon nitride MONOS nonvolatile memory devices by tunneling spectroscopy

Trapped charge distribution in MONOS

trap density material. Our numerical simulation of the charging action of the nitride under an applied gate bias agrees well with the trapped charge distri- bution obtained with the analytical model.

Acknowledgements--The authors would like to acknowl- edge the Office of Naval Research under Contract N00014- 86-K-411 and the National Science Foundat ion (NSF) ECS-8506575 and ECS-9023607 under the Solid-State Microstructures Engineering Program for supporting the work. A word of thanks to Dr C. C. Chao for the MONOS transistor samples. The helpful discussions with Dr A. K. Agarwal and the support of Chun-Yu Malcolm Chen in the preparation of this manuscript are appreciated.

REFERENCES

1. J. Robertson, Phil. Mag. B44, 215-237 (1981). 2. S. Fujita and A. Sasaki, J. Electrochem. Soc. 132,

398~,02 (1985). 3. D. T. Krick, P. M. Lenahan and J. Kanicki, Phys. Rev.

B 38, 822(~8229 (1988). 4. M. H. White and C. C. Chao, J. Appl. Phys. 57, 2318

(1985). 5. L. Lundkvist, I. Lundstrom and C. Svensson, Solid-St.

Electron. 16, 811 823 (1973). 6. S. Manzini and A. Modelli, In Proc. Int. Conf. INFOS

1983 (Edited by J. F. Verweij and D. R. Wolters), Eindhoven, The Netherlands, p. 112. North-Holland, Amsterdam (1983).

7. C. C. Chao and M. H. White, Solid-St. Electron 30, 307-319 (1987).

8. H. Bernt and J. W. Scholtens, Solid-St. Electronic. 25, 843-850 (1982).

A P P E N D I X

The integral:

1=t Jo~'-x{x)h{X)exp~r(x'ETA) ~ z(x.t-E~A)] dx with the scanning function approximation (4) we obtain:

f x ' + ~ ~ n r ( x ) h ( x ) I t i l l = t ' -a~ r(x,ETA) exp ,(x,~ETA dx.

Integration by parts leads to

I'~t\In~(x)h(x) j z dxI.._ax

dx'-ax ( ax

exf t I ) x f dx dx

) l ._..

-Ix'+"~O[n~(x)h(X)]ex~-~)} dx [ ,x

Choose

~-otr~ ( n~(x'+Ax)h(x'+Ax)

× exp exp[a N (ETA) Ax

- n ~ ( x ' - Ax)

x h (x ' - Ax) exp { - exp[aN (ETA) Ax] } ) .

1 Ax = - - In(10):

~N (ERA)

1 I _ ~ - - n ~ (x') h (x')

~ (ETA) where x ' is a function of E t viz.

x ' ( E - r A ) = ~ l n ~ •

1089

(A1)