development and performance verification of the gandalf high-resolution transient recorder system
DESCRIPTION
Development and Performance Verification of the GANDALF High-Resolution Transient Recorder System. COMPASS – Fixed Target Experiment. COMPASS – Experiment: 240 physicists from 11 countries and 28 institutions. COMPASS Facility (since 2002). Hadron Spectroscopy, Deep Inelastic Scattering. - PowerPoint PPT PresentationTRANSCRIPT
Sebastian SchopfererUniversity of Freiburg
IEEE RT 2010, Lisboa
Development and Performance Verificationof the GANDALF High-Resolution Transient
Recorder System
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 2/18
COMPASS – Fixed Target Experiment
COMPASS – Experiment:240 physicists from11 countries and28 institutions
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 3/18
COMPASS Facility (since 2002)
50m
Hadron Spectroscopy, Deep Inelastic Scattering
μ 190 GeV/chigh intensity (2∙107 s-1)large halo
polarized target (NH3 or LiD) 2-stage spectrometer several types of trackers calorimeters (ECAL, HCAL) PID (Muon-Filters, RICH)
,K
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 4/18
COMPASS-II Upgrade
2,5m liquid hydrogen target
COMPASS spectrometer:
trackers, calorimeters, PID
p
μ
μRecoil Proton Detector:to ensure exclusivity of the observed process
DVCS: p p COMPASS-II proposal: determination ofGeneralized Parton Distributions
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 5/18
Recoil Proton Detector (RPD)
4m
-4V
measurement of:-time-of-flight (σ < 200ps)-energy deposit
high luminosity:separation of pile-up pulses is required p
inner barrel (A): Ø 0.50 mouter barrel (B): Ø 2.20 m
μ
0V0ns 40ns
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 6/18
VME64x InterfaceVME64x Interface
USB 2.0USB 2.0
S-Link Interfaceto DAQ
S-Link Interfaceto DAQ
VITA 41.0VXS Interface
VITA 41.0VXS InterfaceTCSTCS
8 Analog Inputs
8 Analog Inputs
8 Analog Inputs
8 Analog Inputs
144Mbit QDRII+4Gbit DDR2Memories
144Mbit QDRII+4Gbit DDR2Memories
V5 LXT FPGA forMemory Control& Data Output
V5 LXT FPGA forMemory Control& Data Output
500MhzBandwidth
Analog Inputs
500MhzBandwidth
Analog Inputs
V5 SXT FPGA for Data ProcessingV5 SXT FPGA for Data Processing
12 bit500MS/s ADCs
12 bit500MS/s ADCs
16bit DACs forOffset Correction
16bit DACs forOffset Correction
Digital Pulse Processing for real-time extraction of time, amplitude and integral information
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 7/18
ADC Mezzanine Card
• 8 ADC channels(12bit@500MS/s or 14bit@400MS/s)
• optional time-interleaved mode• offsets are adjustable by DACs• gain is adjustable by changing some
passive components• flexible input range
(e.g. -4V..0V, -1V..0V, -2V..+2V, …)
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 8/18
Time Interleaved Mode
• Advantage: High Resolution @ High Sampling Rate
12bit @ 1Gsps
• Challenges– Symmetric clock distribution– Clock Jitter < 1ps– Symmetric placement of devices
FPGAAnalogIN
DSPLLClock
System
38.88MHz Exp. Clock
500MHz 0°
500MHz 180°
AI
AI ADC
ADC
Time
Anal
og
Dig
ital
Dig
ital
Time Time
• Possible errors are corrected– Gain error– Offset error
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 9/18
Sampling Clock Requirements
ENOB = (SNR – 1.76) / 6.02
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 10/18
Sampling Clock QualityAnalogIN
LMH6552
ADC
ClockSynth
TCSReceiver
155,52MHz
505.44MHz
Si5326
ADS5463
AnalogINLMH6552
ADC
ClockSynth
OCXO
500MHz
20MHz
Si5326
ADS5463
Sampling JitterTCS Jitter
ns ps
900 fs
Sampling JitterOCXO Jitter
ns ps
730 fs
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 11/18
GANDALF Performance• Signal-to-Noise Ratio (Effective Number of Bits)
fin
LMH6552
ADC
Measurement Setup:AFG3252 andhigh performanceband-pass filters
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 12/18
Fit Algorithms for Time Extraction• Digital Constant Fraction Discrimination
DelayFractionfactor
t meas.
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 13/18
GANDALF dCFD Performance• create PMT-like pulses
with function generator• pile-up pulses with
amplitude and phase modulation
timing resolution vs. pulse amplitudesampled in 1GS/s mode
4V40mV
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 14/18
GANDALF Laser TestPMT: RT14501.1 – 1.3kV
Laser Pulser
GANDALF
sampled in 1GS/s mode
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 15/18
Fast Recoil Detector Trigger
TriggerProcessor
GANDALF
Proton Trigger
VXS BackplaneAnalogInputs
Exp. Trigger
i
target
inner Layer
outer Layer
Ai+1
Ai
Ai-1
Bi+1
Bi-1
t proton - t muonenergy deposit vs. geometric structure
μ
pB
A
VITA 41.0Specification
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 16/18
GANDALF as TDC & Logic Module
Trigger &Clock
DataProcessing,Analog TriggerGeneration
MemoryController
VMEInterface,BoardConfig.
CompactFlashMemory
16 HSChannelsvia VXS toSwitch
To Backplane
To Backplane
To Transition
VME64xInterface toVME CPU
QDRII144Mb
DDR24Gb
HFCLK
S-Link Interfacevia P2
USB
TCS
64 channelLVDS/LVPECL
inputs
1 NIM Input2 NIM Outputs
64 channelLVDS/LVPECL
inputs
1 NIM Input2 NIM Outputs
32 ch. LVDS input
32 ch. LVDS input
NIM I/O (LEMO)
NIM I/O (LEMO)
NIM I/O (LEMO)
32 ch. LVDS input
32 ch. LVDS input
NIM I/O (LEMO)
NIM I/O (LEMO)
NIM I/O (LEMO)
Implementation of TDCs, scalers, mean-timers, …inside the FPGA
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 17/18
GANDALF Mean-Timer• 64 mean timer channels• max. time difference: 29 ns• resolution: 230 ps• variable input delay (max 8ns)
to compensate cable lengths• mean-timer signals are fed
into coincidence matrix• matrix pixels can be switched
on/off on-the-fly
(John Bieling, University of Bonn)„delay group“
OR cascade
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 18/18
Generic Advanced Numerical Device for Analog and Logic Functions
• … is a VME64x readout system for high energy physics
• … is a transient recorder which meets all design goals:– Effective Number of Bits > 10 bit– Time resolution < 50 ps
• … is a logic module with possibilities to implement TDC, Scaler, mean-timer and trigger matrix functionalities
• … is a VXS payload board to allow multi-module trigger decisions
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 19/18
Thanks for your attention!
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 20/18
Backup
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 21/18
Timing ResolutionMethods convergeat low amplitudes
Spline algorithm reaches better timing resolution
Constant Fraction reaches good timing resolution with very low calculation efforts!
Tim
ing
Res
olut
ion
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 22/18
Near following Pulses• Best achievable resolution fornear following pulses• Digital signal process developedfor double risetime range
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 23/18
GANDALF Performance II
1GHz sampling rate
Offset correction by DACGain correction by FPGA
1GHz sampling rate
Offset correction by DACGain correction by FPGA
y = 6,9926x - 0,0082
R2 = 0,9996
-20
-15
-10
-5
0
5
10
15
20
-2,5 -1,5 -0,5 0,5 1,5 2,5
Diff Linear (Diff)
Gain AdjustmentGain Adjustment
10bit ENOBInterleaved:
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 24/18
FPGA TDC Implementation• Shifted Clock Sampling
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 25/18
Share FPGA Resources
ConstantFraction
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 26/18
8 ChannelAD Conversion
@ 500Msps 12bit
16bit offset DAC
Trigger &Clock
8 ChannelAD Conversion
@ 500Msps 12bit
16bit offset DAC
8
An
alo
g
In
puts
USB
TCS
Data Processing
Online Feature Extraction
MemoryController
VMEInterface,BoardConfig.
CompactFlashMemory
low latencyconnectionvia VXS toTrigger Processor
To Backplane
To Transition
VME64xInterface
QDRII144Mb
DDR24Gb
HFCLK
Readout viaCERN S-LinkInterface
8
An
alo
g
Inp
uts
To Backplane
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 27/18
Data
Bus
to G
AN
DA
LF B
oard
Digital Mezzanine Card
NIM I/O (LEMO)
NIM I/O (LEMO)
NIM I/O (LEMO)
TTL to NIMBuffer
Hig
h D
ensi
ty C
onne
ctor
32 ch. LVDS input
32 ch. LVDS input
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
LVDSBuffer
NIM to TTLBuffer
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 28/18
Messungen zur Zeitauflösung
Jitter TCS Si5326
TIE 130ps 16ps
Board vs Board
90ps 5ps
Differenz der TIEs zwischen 2 GANDALF Boards: 5psZeit 2,5μs / div
TIE
10
ps
/ d
iv
Exp. Clock
FANOUT
GANDALF
27 May 2010 Sebastian Schopferer, RT 2010, Lisboa 29/18
Transient Recorder Challenges– Define and calculate the time of
the signal shape
– Time of Flight calculation with a resolution of < 200ps
– Determine the amplitude of the signals with high dynamic range
– Seperate signals from pile-up pulses
– Create a trigger for recoil protons frommultiple signal channels