development of a high performance tdc module for the grapes-3 experiment b.satyanarayana department...

Development of aDevelopment of ahigh performance TDC modulehigh performance TDC module

for the Grapes-3 experimentfor the Grapes-3 experiment

B.SatyanarayanaB.SatyanarayanaDepartment of High Energy PhysicsDepartment of High Energy Physics

Performance of the TDC module Performance of the TDC module developed for the developed for the

Grapes-3 experimentGrapes-3 experiment

S.KarthikeyanS.Karthikeyan

Department of High Energy PhysicsDepartment of High Energy Physics

Next ASET ColloquiumNext ASET Colloquium

ASET Colloquium on Oct 13, 2006ASET Colloquium on Oct 13, 2006 B.Satyanarayana, DHEPB.Satyanarayana, DHEP

The teamThe team

S.K.GuptaS.K.Gupta¶¶, Y.Hayashi, Y.Hayashi§§, A.Iyer, A.Iyer¶¶, P.Jagadeesan, P.Jagadeesan¶¶, , A.JainA.Jain¶¶, S.Karthikeyan, S.Karthikeyan¶¶, S.Kawakami, S.Kawakami§§, ,

K.C.RavindranK.C.Ravindran¶¶, B.Satyanarayana, B.Satyanarayana¶¶ and S.C.Tonwar and S.C.Tonwar¶¶

¶¶Tata Institute of Fundamental Research, Mumbai, INDIATata Institute of Fundamental Research, Mumbai, INDIA§§Osaka City University, Osaka, JapanOsaka City University, Osaka, Japan


Plan of the talkPlan of the talk

Introduction to Time to Digital ConvertersIntroduction to Time to Digital Converters Grapes’ time measurement requirementsGrapes’ time measurement requirements Specifications of the TDC32 ASICSpecifications of the TDC32 ASIC Functional blocks of TDC32Functional blocks of TDC32 Hardware design of the TDC moduleHardware design of the TDC module JTAG interface designsJTAG interface designs Deployment in the Grapes-3 experimentDeployment in the Grapes-3 experiment Summary and outlookSummary and outlook AcknowledgementsAcknowledgements


Next topic of the talkNext topic of the talk



Why TDCs?Why TDCs?TDCs are used to measure time or intervalsTDCs are used to measure time or intervals

• Start – Stop measurementStart – Stop measurement Measurement of time interval between two events:Measurement of time interval between two events:

Start signal – Stop signalStart signal – Stop signal Used to measure relatively short time intervals with Used to measure relatively short time intervals with

high precisionhigh precision Like a stop watch used to measure sport competitionsLike a stop watch used to measure sport competitions

• Time taggingTime tagging Measure time of occurrence of events with a given Measure time of occurrence of events with a given

time reference:time reference:Time reference (Clock)Time reference (Clock)

Events to be measured (Hits)Events to be measured (Hits) Used to measure relative occurrence of many events Used to measure relative occurrence of many events

on a defined time scale:on a defined time scale:Such a time scale will have limited range; like 12/24 hourSuch a time scale will have limited range; like 12/24 hour

time scale on your watch when having no date and yeartime scale on your watch when having no date and year

Time scale (clock)

Hits

Start

Stop


Where TDCs?Where TDCs?

Special needs for High Energy PhysicsSpecial needs for High Energy Physics• Many thousands of channels needed Many thousands of channels needed • Rate of measurements can be very highRate of measurements can be very high• Very high timing resolutionVery high timing resolution• A mechanism to store measurements during a given interval A mechanism to store measurements during a given interval

and extract only those related to an interesting event, and extract only those related to an interesting event, signaled by a trigger, must be integrated with TDC functionsignaled by a trigger, must be integrated with TDC function

Other applicationsOther applications• Laser/radar ranging to measure distance between carsLaser/radar ranging to measure distance between cars• Time delay reflection to measure location of broken fiberTime delay reflection to measure location of broken fiber• Most other applications only needs one or a few channelsMost other applications only needs one or a few channels


Pipelined TDC architecturePipelined TDC architecture Stores hit data every clock cycleStores hit data every clock cycle High hit rates (one per clock cycle)High hit rates (one per clock cycle) Fixed dead time; but limited double pulse Fixed dead time; but limited double pulse

resolutionresolution Fixed trigger latency; limited by buffer sizeFixed trigger latency; limited by buffer size Only useful in triggered modeOnly useful in triggered mode Difficult to support overlapping triggersDifficult to support overlapping triggers No problem with buffer occupanciesNo problem with buffer occupancies Narrow but deep latency bufferNarrow but deep latency buffer Simple architecture; quick implementationSimple architecture; quick implementation LimitedLimited flexibilityflexibility ExamplesExamples

• LeCroy’s FASTBUS DC TDCsLeCroy’s FASTBUS DC TDCs• DAQ of KGF underground experimentsDAQ of KGF underground experiments

Hit

Clock

Synchronoustrigger

OutputFIFO

Small dynamic range (25ns)


Data driven TDC architectureData driven TDC architecture Only stores data when hit detectedOnly stores data when hit detected Variable latency over full dynamic rangeVariable latency over full dynamic range Compromise between hit rate and latencyCompromise between hit rate and latency Triggered/non triggered modesTriggered/non triggered modes Multiple overlapping triggersMultiple overlapping triggers Channel merging via de-randomizers;Channel merging via de-randomizers;

Limits hit ratesLimits hit rates Good double pulse resolution;Good double pulse resolution;

But complicated dead time analysisBut complicated dead time analysis Buffer occupancies must be seriously analyzedBuffer occupancies must be seriously analyzed Buffer overflows must be handled carefullyBuffer overflows must be handled carefully

• Hit may be lost if markedHit may be lost if marked• Complete events must never be lostComplete events must never be lost

Wide latency buffer (covers full dynamic range)Wide latency buffer (covers full dynamic range) More complicated architecture/implementationMore complicated architecture/implementation

• Logic complication handled by logic synthesisLogic complication handled by logic synthesis• Extended verifications at behavioral/register/gate levelExtended verifications at behavioral/register/gate level

High flexibilityHigh flexibility

Large dynamic range

FIFO orDual port RAM

Hit

Triggertime tag

Compare time

OutputFIFO

Trigger

-

Latency

Derandomizer FIFO’s

Common FIFO


Basic TDC types - IBasic TDC types - I Counter typeCounter type

• AdvantagesAdvantages Simple; but still useful!Simple; but still useful! DigitalDigital large dynamic range possiblelarge dynamic range possible Easy to integrate many channels per chipEasy to integrate many channels per chip

• DisadvantagesDisadvantages Limited time resolution (1ns using modern Limited time resolution (1ns using modern

CMOS technology)CMOS technology) Metastability (use of Gray code counter)Metastability (use of Gray code counter)

Single Delay chain typeSingle Delay chain type• Cable delay chain (distributed L-C)Cable delay chain (distributed L-C)

Very good resolution (5ps mm)Very good resolution (5ps mm) Not easy to integrate on integrated circuitsNot easy to integrate on integrated circuits

• Simple delay chain using active Simple delay chain using active gatesgates Good resolution (~100ps using modern tech)Good resolution (~100ps using modern tech) Limited dynamic range (long delay chain and Limited dynamic range (long delay chain and

register)register) Only start-stop typeOnly start-stop type Large delay variations between chips and with Large delay variations between chips and with

temperature and supply voltagetemperature and supply voltage

CounterClock

Start Stop

Start-stop type

Register

Start

Stop

Delay chain with non-inverting gates

Cable delay chain

CounterClock

RegisterHit

Reset

Time tagging type


Basic TDC types - IIBasic TDC types - II Single Delay chain type (Contd…)Single Delay chain type (Contd…)

• Delay locked loopDelay locked loop Self calibrating using external frequency Self calibrating using external frequency

reference (clock)reference (clock) Allows combination with counterAllows combination with counter Delicate feedback loop design (jitter)Delicate feedback loop design (jitter)

• R-C delay chainR-C delay chain Very good resolutionVery good resolution Signal slew rate deterioratesSignal slew rate deteriorates Delay chain with losses; so only short delay chain Delay chain with losses; so only short delay chain

possiblepossible Large sensitivity to process parameters (and Large sensitivity to process parameters (and

temperature)temperature)

Register

PhaseClock

Hit

Delay Locked Loop

R

C

R

C

R

C

V

t

RC delay chain

R

C


Basic TDC types - IIIBasic TDC types - III Multiple delay chain typeMultiple delay chain type

• Vernier delay chain typesVernier delay chain types Resolution determined by delay difference Resolution determined by delay difference

between two chains. Delay difference can between two chains. Delay difference can be made very small and very high resolution be made very small and very high resolution can be obtained.can be obtained.

Small dynamic range (long chains)Small dynamic range (long chains) Delay chains can not be directly calibrated Delay chains can not be directly calibrated

using DLLusing DLL Matching between delay cells becomes Matching between delay cells becomes

criticalcritical

• Coupled delay locked loopsCoupled delay locked loops Sub-delay cell resolution (¼)Sub-delay cell resolution (¼) All DLLs use common time reference (clock)All DLLs use common time reference (clock) Common timing generator for multiple Common timing generator for multiple

channelschannels Jitter analysis not trivialJitter analysis not trivial

Start

Stop

D D D D D D D D

Start delay chain: Tstart

Stop delay chain: Tstop

Vernier principle

Resolution: Tstart - Tstop

Clock

PD

PD

PD

PD

PD

T1T2 = T1 + Δ

Resolution: T2 – T1 = Δ


Basic TDC types - IVBasic TDC types - IV Charge integrationCharge integration

• Using ADC (TAC)Using ADC (TAC) High resolutionHigh resolution Low dynamic rangeLow dynamic range Sensitive analog designSensitive analog design Low hit rateLow hit rate Requires ADCRequires ADC

• Using double slope (time stretcher)Using double slope (time stretcher) No need for ADC (substituted with a counter)No need for ADC (substituted with a counter)

Multiple Multiple exoticexotic architectures architectures• Heavily coupled phase locked loopsHeavily coupled phase locked loops

• Beating between two PLLsBeating between two PLLs

• Re-circulating delay loopsRe-circulating delay loops

• Summing of signals with different slew ratesSumming of signals with different slew rates

Start Stop

ADC

Start

Stop

I1

I2 = I1/k

Counter

ClockDisc.

Start

Start StopStretched time

Stop


How to compare TDCs?How to compare TDCs? MeritsMerits

• ResolutionResolution Bin size and effective resolution (RMS, INL, DNL)Bin size and effective resolution (RMS, INL, DNL)

• Dynamic rangeDynamic range• StabilityStability

Use of external referenceUse of external reference Drift (e.g. temperature)Drift (e.g. temperature) Jitter and NoiseJitter and Noise

• Integration issuesIntegration issues Digital / analogDigital / analog Noise / power supply sensitivityNoise / power supply sensitivity Sensitivity to matching of active elementsSensitivity to matching of active elements Required IC areaRequired IC area Common timing block per channelCommon timing block per channel Time critical block must be implemented on chip together with noisy digital logicTime critical block must be implemented on chip together with noisy digital logic

Use in final systemUse in final system Can one actually use effectively very high time resolution in large systems (detectors)Can one actually use effectively very high time resolution in large systems (detectors) Calibration - stabilityCalibration - stability Distribution of timing reference (start signal or reference clock)Distribution of timing reference (start signal or reference clock) Other features: data buffering, triggering, readout, test, radiation, etc.Other features: data buffering, triggering, readout, test, radiation, etc.


Grapes’ TDC requirementsGrapes’ TDC requirements• Many hundreds of channels needed Many hundreds of channels needed • Low cost per channelLow cost per channel• Considerations of the input signal type Considerations of the input signal type • Rate of measurements can be very highRate of measurements can be very high• Decent timing resolutionDecent timing resolution• Trigger matching capabilityTrigger matching capability• Multi-hit facility preferableMulti-hit facility preferable• High stability, low jitter and driftHigh stability, low jitter and drift• Simple calibration procedureSimple calibration procedure• Individual channel offsets/presetsIndividual channel offsets/presets


The TDC32 ASIC chipThe TDC32 ASIC chipChip designerChip designer

JÖÖrgen ChristiansenECP-MIC

Microelectronics GroupCERN, Geneva

Prominent usersProminent users

LHC, ALICE, CMS, ATLAS, BES, NA48,

STAR, CAEN etc.

84-p

in P

LCC


Specifications of the TDC32 ASICSpecifications of the TDC32 ASIC Number of channels: 32 + 1 Common startNumber of channels: 32 + 1 Common start Clock frequency: 20-60MHzClock frequency: 20-60MHz Time bin size: 520ps @60MHzTime bin size: 520ps @60MHz DNL: ±130ps(max), 63ps(RMS) @60MHzDNL: ±130ps(max), 63ps(RMS) @60MHz INL: ±280ps(max), 130ps(RMS) @60MHzINL: ±280ps(max), 130ps(RMS) @60MHz Time resolution: 200ps(RMS) @60MHzTime resolution: 200ps(RMS) @60MHz Difference between channels: One time bin (max)Difference between channels: One time bin (max) Variation with temperature: One time bin (max)Variation with temperature: One time bin (max) Dynamic range: 21 bitsDynamic range: 21 bits Double pulse resolution: 15nsDouble pulse resolution: 15ns Max recommended hit rate: 750KHz per channelMax recommended hit rate: 750KHz per channel Event buffer size: 256Event buffer size: 256 Read-out buffer size: 32Read-out buffer size: 32 Trigger buffer size: 8Trigger buffer size: 8 Power supply: 4.75-5.25Volts, ~100mA @60MHzPower supply: 4.75-5.25Volts, ~100mA @60MHz Temperature range: -40 to 80Temperature range: -40 to 80o o CC Hit input threshold voltage: Standard TTLHit input threshold voltage: Standard TTL


Architecture of TDC32Architecture of TDC32


Delay Locked LoopDelay Locked Loop

Three major components:Three major components:• Chain of 32 delay elements; Chain of 32 delay elements;

adjustable delayadjustable delay• Phase detector between clock Phase detector between clock

and delayed signaland delayed signal• Charge pump & level shifter Charge pump & level shifter

generating control voltage to the generating control voltage to the delay elementsdelay elements

Jitter in the delay chainJitter in the delay chain Lock monitoringLock monitoring Dynamics of the control loopDynamics of the control loop Programmable charge pump Programmable charge pump

current levelcurrent level


Coarse time countCoarse time count Dynamic range of the fine time measurement, Dynamic range of the fine time measurement,

extracted from the state of DLL is expanded, byextracted from the state of DLL is expanded, by Storing the state of a clock synchronous counterStoring the state of a clock synchronous counter Hit signal is synchronous to the clocking, soHit signal is synchronous to the clocking, so Two count values, ½ a clock cycle out of phase storedTwo count values, ½ a clock cycle out of phase stored At reset, coarse time counter loaded with time offsetAt reset, coarse time counter loaded with time offset


Hit registersHit registers Programmable edge (rising or falling) detectionProgrammable edge (rising or falling) detection De-glitched hit signal is used to load a timing registerDe-glitched hit signal is used to load a timing register Individual channels can be enabled or disabledIndividual channels can be enabled or disabled Self timed controller based double timing registersSelf timed controller based double timing registers De-randomisation; double synchronisersDe-randomisation; double synchronisers


Channel offset adjustmentChannel offset adjustment Variable detector-to-control room Variable detector-to-control room

distances and thus cable lengthsdistances and thus cable lengths Coaxial cable – Astronomer's best Coaxial cable – Astronomer's best

choice for signal delay choice for signal delay adjustment, but a costly one!adjustment, but a costly one!

Common programmable coarse Common programmable coarse time count offsettime count offset

Individual programmable fine time Individual programmable fine time adjustment possibleadjustment possible

Eight bit (3 bits coarse, 5 bits fine) Eight bit (3 bits coarse, 5 bits fine) channel dependent constantchannel dependent constant

Stored in a 32 words by 8 bits Stored in a 32 words by 8 bits wide memorywide memory


Start-Stop timingStart-Stop timing Start time measurement done by a dedicated channelStart time measurement done by a dedicated channel Start channel is just a superior priority channelStart channel is just a superior priority channel Start time transferred to the register on hit - immediatelyStart time transferred to the register on hit - immediately Previous data must therefore be stored before next startPrevious data must therefore be stored before next start Start time can be subtracted from all hitsStart time can be subtracted from all hits Start signal can gate all the stops; used in Grapes’ modulesStart signal can gate all the stops; used in Grapes’ modules

Common start time subtraction Start gating


Event bufferEvent buffer 256 hits deep circular buffer256 hits deep circular buffer Coarse and fine time counts Coarse and fine time counts

+ Channel id + Time tag+ Channel id + Time tag Channel arbitration schemesChannel arbitration schemes Reading is random accessReading is random access Trigger matching can search Trigger matching can search

for data belonging to the for data belonging to the received triggersreceived triggers

Write pointer never Write pointer never overtakes read pointerovertakes read pointer

Error flagged if the event Error flagged if the event buffer overflowsbuffer overflows

Hits data lost only if both Hits data lost only if both primary and secondary primary and secondary registers are fullregisters are full


Trigger matchingTrigger matching Time match between trigger time tag and stopsTime match between trigger time tag and stops Hits matching trigger pushed to readout FIFOHits matching trigger pushed to readout FIFO Trigger time tag can be subtracted from all stops – bunch crossingTrigger time tag can be subtracted from all stops – bunch crossing Global time reference – t0 – time since TDC RESETGlobal time reference – t0 – time since TDC RESET Trigger matching within a programmable windowTrigger matching within a programmable window Allowed trigger latency 32768 clock periodsAllowed trigger latency 32768 clock periods Hits are not written in strict temporal orderHits are not written in strict temporal order A hit may belong to several closely spaced triggersA hit may belong to several closely spaced triggers Two search pointers and two programmable windows usedTwo search pointers and two programmable windows used


Trigger interfaceTrigger interface Trigger matching based on Trigger matching based on

trigger tag locating in time trigger tag locating in time where hits belong to an where hits belong to an event of interestevent of interest

Trigger tags pushed into 8-Trigger tags pushed into 8-word deep trigger FIFOword deep trigger FIFO

Several ways of supplying Several ways of supplying trigger time tagstrigger time tags• Parallel transfer via Parallel transfer via

readout busreadout bus• Serial transferSerial transfer• Centrally loading time tag Centrally loading time tag

counter into a registercounter into a register


Readout FIFOReadout FIFO 32 words deep32 words deep Enable one event to be readout, while another Enable one event to be readout, while another

is being processedis being processed If readout FIFO runs full, the trigger matching If readout FIFO runs full, the trigger matching

process stopsprocess stops Event separators if trigger matching enabled; Event separators if trigger matching enabled;

effective readout FIFO size reducedeffective readout FIFO size reduced


Readout interfaceReadout interface Readout via clock synchronous busReadout via clock synchronous bus Several TDCs may share a busSeveral TDCs may share a bus Event synchronised readout if trigger matching enabled using Event synchronised readout if trigger matching enabled using

Event_end and Next_event handshakeEvent_end and Next_event handshake Readout of individual hits using Data_ready and Get_data Readout of individual hits using Data_ready and Get_data

handshakehandshake Readout at TDC’s full speed if Get_data held HIGHReadout at TDC’s full speed if Get_data held HIGH Low speed readout via Data_ready and Get_data handshakeLow speed readout via Data_ready and Get_data handshake Token based readout protocol for multiple chip boardsToken based readout protocol for multiple chip boards


JTAG test and programming portJTAG test and programming port

JTAG registersJTAG registers• JTAG instruction register (4)JTAG instruction register (4)• Boundary scan register (89)Boundary scan register (89)• Setup registers (127)Setup registers (127)• Control registers (33)Control registers (33)• Status registers (5)Status registers (5)• Internal status registers (59)Internal status registers (59)

JTAG instructionsJTAG instructions• EXTEST: Boundary scan for inter-chip EXTEST: Boundary scan for inter-chip

connectionsconnections• IDCODE: Read 32-bit chip ID codeIDCODE: Read 32-bit chip ID code• SAMPLE: Sample of all chip pinsSAMPLE: Sample of all chip pins• INTEST: Use boundary scan registers to test INTEST: Use boundary scan registers to test

the chipthe chip• SETUP: Load of setup dataSETUP: Load of setup data• CONTROL: Load of control informationCONTROL: Load of control information• STATUS: Read of status informationSTATUS: Read of status information• CORETEST: Access to internal test scan CORETEST: Access to internal test scan

registersregisters• BYPASS: Bypass the chip in a cascadeBYPASS: Bypass the chip in a cascade

Joint Test Action Group (JTAG)Joint Test Action Group (JTAG) Standard IEEE 1149.1Standard IEEE 1149.1 Used to setup programmable featuresUsed to setup programmable features Get access to test facilities built into the chipGet access to test facilities built into the chip


JTAG setup register fieldsJTAG setup register fields

[15:0] [15:0] Yes/No trigger time tag offset Yes/No trigger time tag offset [16][16] Enable parallel trigger Enable parallel trigger [17][17] Enable synchronous trigger Enable synchronous trigger [18][18] Enable Serial trigger Enable Serial trigger [34:19][34:19] Trigger matching window Trigger matching window [35][35] Enable readout of start Enable readout of start

measurements measurements [36] [36] Enable subtraction of trigger time Enable subtraction of trigger time

tagtag [37][37] Enable overlapping triggers Enable overlapping triggers [45:38][45:38] Looking back window [7:0] Looking back window [7:0] [53:46] Looking forward window [7:0][53:46] Looking forward window [7:0] [54][54] Enable subtraction of start time Enable subtraction of start time [55][55] Enable matching Enable matching [56][56] Enable automatic reject Enable automatic reject [72:57][72:57] Reject offset [15:0] Reject offset [15:0] [78:73][78:73] Adjust channel offset [5:0] Adjust channel offset [5:0] [86:79][86:79] Adjust common offset [7:0] Adjust common offset [7:0] [87][87] Enable individual adjust Enable individual adjust [89:88][89:88] Operating mode: 00 = normal Operating mode: 00 = normal

[94:90][94:90] DLL current level DLL current level [95][95] DLL reset DLL reset [96][96] Detect falling edge start Detect falling edge start [97][97] Detect falling edge odd channels Detect falling edge odd channels [98][98] Detect falling edge even channels Detect falling edge even channels [99][99] Detect both edges (all channels) Detect both edges (all channels) [100][100] Enable empty start Enable empty start [101][101] Must be equal to setup [54] Must be equal to setup [54] [102][102] Enable double synchronisers Enable double synchronisers [103][103] Enable double hit priority queue Enable double hit priority queue [104] [104] Enable start gating Enable start gating [120:105] Coarse count offset [120:105] Coarse count offset [121][121] Enable token read-out mode Enable token read-out mode [122][122] Not locked error mask Not locked error mask [123][123] Hit error error mask Hit error error mask [124][124] Event buffer overflow error mask Event buffer overflow error mask [125] [125] Trigger buffer overflow error Trigger buffer overflow error

maskmask [126][126] Serial trigger error error mask Serial trigger error error mask


TDC resetTDC reset Main reference of the TDC is clockMain reference of the TDC is clock Synchronous TDC Reset defines Synchronous TDC Reset defines TT00 DLL is not reset when Reset pin of the TDC DLL is not reset when Reset pin of the TDC

asserted; must be done via JTAG interfaceasserted; must be done via JTAG interface All buffers, counters and state machines are All buffers, counters and state machines are

initialised on reset to their default valuesinitialised on reset to their default values Needs to be done only at startupNeeds to be done only at startup


Error and status flagsError and status flags All main functional blocks are continuously monitored All main functional blocks are continuously monitored

for error conditionsfor error conditions Error state of individual parts can only be accessed via Error state of individual parts can only be accessed via

JTAG status scan pathJTAG status scan path Error flags supportedError flags supported

• (DLL) Not_locked(DLL) Not_locked• Hit_error (while writing to event buffer)Hit_error (while writing to event buffer)• Event_buffer_overflowEvent_buffer_overflow• Trigger_buffer_overflowTrigger_buffer_overflow• Serial_trigger_errorSerial_trigger_error• All but the Not_locked error cleared by ResetAll but the Not_locked error cleared by Reset

A general purpose error pin can be programmed to A general purpose error pin can be programmed to signal the error conditions neededsignal the error conditions needed


Block diagram of the TDC moduleBlock diagram of the TDC module

Power


TDC module: Input sectionTDC module: Input section


TDC module: Core sectionTDC module: Core section


TDC module: Control sectionTDC module: Control section


TDC module: CAMAC sectionTDC module: CAMAC section


TDC module: JTAG sectionTDC module: JTAG section


TDC module: Power suppliesTDC module: Power supplies


What had begun like this …What had begun like this …


… … ended like thisended like this


Schematics of JTAG controllersSchematics of JTAG controllers

PC Printer port

NIM module

1 MHz


Deployment in Grapes-3Deployment in Grapes-3 Module supports Module supports standardstandard CAMAC as well as Grapes’ CAMAC as well as Grapes’

CAMAC interfacesCAMAC interfaces Module tested with 20, 40 and Module tested with 20, 40 and 6060MHz clocks using a MHz clocks using a

sophisticated custom built TDC calibration systemsophisticated custom built TDC calibration system First module installed in the experiment using Start-First module installed in the experiment using Start-

Stop mode in December 2003; parallel readout along Stop mode in December 2003; parallel readout along with a Phillips Scientific module for comparisonwith a Phillips Scientific module for comparison

Second module installed in April 2004 using trigger Second module installed in April 2004 using trigger matching mode; got rid of 80m/channel coaxial cables!matching mode; got rid of 80m/channel coaxial cables!

Module with improved PCB installed in January 2005Module with improved PCB installed in January 2005• Supports both Start-stop and trigger matching modesSupports both Start-stop and trigger matching modes• CAMAC interface packed in an iSPL chipCAMAC interface packed in an iSPL chip

Currently three modules in the system and two more Currently three modules in the system and two more waiting for their turnwaiting for their turn

In-situ calibration scheme used for rigorous monitoring In-situ calibration scheme used for rigorous monitoring


Summary and outlookSummary and outlook Successful development and deployment of high Successful development and deployment of high

performance TDC moduleperformance TDC module Development of simple JTAG controllersDevelopment of simple JTAG controllers Exceeds the Grapes’ TDC requirementsExceeds the Grapes’ TDC requirements Three modules in the system for many yearsThree modules in the system for many years TDC32 chip availability is a major concernTDC32 chip availability is a major concern HPTDC: the next generation chip is the answerHPTDC: the next generation chip is the answer Major improvements in several aspects; butMajor improvements in several aspects; but Package specific difficulties with HPTDCPackage specific difficulties with HPTDC Plan to design modules with HPTDC; work in progressPlan to design modules with HPTDC; work in progress Good scope for building CAMAC/VME based high Good scope for building CAMAC/VME based high

density, but low cost TDC modulesdensity, but low cost TDC modules How about using HPTDC core for indigenous, high How about using HPTDC core for indigenous, high

density, front-end ASIC chip designs?density, front-end ASIC chip designs?


HPTDCHPTDC DLL, hit registers, RC delay DLL, hit registers, RC delay

and PLL implemented as and PLL implemented as full customfull custom

0.25 µm CMOS technology0.25 µm CMOS technology 6.5 x 6.5 mm6.5 x 6.5 mm 1 million transistors1 million transistors 225 ball grid array package225 ball grid array package


Architecture of HPTDCArchitecture of HPTDC


AcknowledgementsAcknowledgementsJJÖÖrgen Christiansenrgen Christiansen

Prof N.K.MondalProf N.K.Mondal

Dr H.TanakaDr H.Tanaka

Dr T.NonakaDr T.Nonaka

K.ManjunathK.Manjunath

C.RavindranC.Ravindran

Grapes colleaguesGrapes colleagues

ASET ForumASET Forum

Backup slidesBackup slides


ispLSI 1016ispLSI 1016 In system programmable high density PLDIn system programmable high density PLD 2000 PLD gates2000 PLD gates 32 I/O pins32 I/O pins 96 registers96 registers Maximum operating frequency 60 MHzMaximum operating frequency 60 MHz Propagation delay 20 nsPropagation delay 20 ns


DNL and ANL conceptsDNL and ANL concepts


Time measurement in HPTDCTime measurement in HPTDC Combination ofCombination of

• Counter with PLL for clock multiplication (x1, x4, x8)Counter with PLL for clock multiplication (x1, x4, x8) Double phase shifted counters to resolve possible Double phase shifted counters to resolve possible

metastability in coarse count measurement.metastability in coarse count measurement.• DLL with 32 taps for clock interpolationDLL with 32 taps for clock interpolation

Use of differential delay cell for power supply noise immunityUse of differential delay cell for power supply noise immunity• R-C delay line on hit signals for very high resolutionR-C delay line on hit signals for very high resolution

Channel reduction by factor 4 (8 channels per chip)Channel reduction by factor 4 (8 channels per chip)

PLL

320MHz

160MHz

40MHz

Mux

DLL

Coarse counter

R

C R

C R

C R

C

Hit

Low resolution: 781 ps

Medium resolution: 195 ps

High resolution: 98ps

Very high resolution: 24ps (8 channels)

Very high resolution

R-C delay line dependent on IC processing (Only small difference between chips seen)R-C delay line independent of temperature in range of 20 degInfrequent calibration requiredCalibration can be obtained with code density test with physics hitsOption of correcting integral errors from DLL8 channels per chipNot possible to pair leading and trailing edges

N N+1

N N+1

Clock

Cnt1

Cnt2

Ch0

Ch1

Ch2

Ch3


Trigger matching in HPTDCTrigger matching in HPTDC

Trigger matching based on hit measurements and trigger time tagTrigger matching based on hit measurements and trigger time tag 16 deep trigger FIFO to receive new triggers while matching function is busy16 deep trigger FIFO to receive new triggers while matching function is busy Trigger remove old hits when no triggers waitingTrigger remove old hits when no triggers waiting Matching based on coarse count (25 ns resolution)Matching based on coarse count (25 ns resolution) Programmable latency and matching windowProgrammable latency and matching window Supports assigning hits to multiple overlapping triggersSupports assigning hits to multiple overlapping triggers Reject function to work across counter overflows (3564 for LHC)Reject function to work across counter overflows (3564 for LHC) Maximum number of hits per event programmableMaximum number of hits per event programmable Trigger matching can be disabledTrigger matching can be disabled

Hits

Overlap

Trigger N Trigger N+1

Latency

Triggers

Match window

Match window


Readout in HPTDCReadout in HPTDC 256 deep readout FIFO to de-couple matching and readout256 deep readout FIFO to de-couple matching and readout Readout FIFO can artificially be reduced to prevent data pile-upReadout FIFO can artificially be reduced to prevent data pile-up Token based sharing of readout port with bypass optionToken based sharing of readout port with bypass option

• Triggered: Token only passed when all hits in event have been read outTriggered: Token only passed when all hits in event have been read out• Non triggered: Token constantly circulating to find TDC’s with dataNon triggered: Token constantly circulating to find TDC’s with data• Bypass option skip failing chip in token chainBypass option skip failing chip in token chain

Possibility to readout buffer occupancy informationPossibility to readout buffer occupancy information 32 bit parallel readout for high rate applications32 bit parallel readout for high rate applications Byte-wise readout to drive commercial serializersByte-wise readout to drive commercial serializers Serial readout for low rate applicationsSerial readout for low rate applications Readout via JTAG possible for debuggingReadout via JTAG possible for debugging

MasterTDC A

SlaveTDC B

SlaveTDC C

Token ring4 channel groups

Readout FIFO256 hits

40 MHz round Robin

L1 buffers


HPTDC’s programmable featuresHPTDC’s programmable features ResolutionResolution Integral error correction from DLLIntegral error correction from DLL Channel offsetsChannel offsets Leading/trailing/pairLeading/trailing/pair Channel enable/disableChannel enable/disable LVDS or TTL hit inputsLVDS or TTL hit inputs Channel dead time (5 - 100ns)Channel dead time (5 - 100ns) Encoding of triggers and resetsEncoding of triggers and resets Trigger matching optionTrigger matching option Trigger latencyTrigger latency Matching windowMatching window Reject latencyReject latency Roll-over and machine cycle Roll-over and machine cycle

separatorsseparators

Limiting number of hits per eventLimiting number of hits per event Readout FIFO sizeReadout FIFO size Readout of buffer occupancies per eventReadout of buffer occupancies per event Buffer back propagationBuffer back propagation Serial, Byte, 32 bit Parallel or JTAG readoutSerial, Byte, 32 bit Parallel or JTAG readout Force specific readout patternForce specific readout pattern Serial readout speed 80Mbits/s - 0.3 Mbits/sSerial readout speed 80Mbits/s - 0.3 Mbits/s Use of event headers and trailersUse of event headers and trailers Token passing schemeToken passing scheme Generation of global error stateGeneration of global error state Low power modeLow power mode DLL and PLL control parametersDLL and PLL control parameters Test modesTest modes

This large set of programmable features has made design verification very difficult

Flexibility does not come for free


NIM based JTAG controller moduleNIM based JTAG controller module


TDC calibration circuitTDC calibration circuit

development of a high performance tdc module for the grapes-3 experiment b.satyanarayana department...

Documents

given time reference

defined time scale

time reference clockevents

short time intervals

clock cyclefixed dead

hit rate

high precisionlike

limited range