development of an fpga-based real-time power system ... · for traveling wave-based protective...

UNIVERSIDADE DO RIO GRANDE DO NORTEFEDERAL

UNIVERSIDADE FEDERAL DO RIO GRANDE DO NORTE

CENTRO DE TECNOLOGIA

PROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E

DE COMPUTAÇÃO

Development of an FPGA-Based Real-TimePower System Simulator for Traveling

Wave-Based Protective Relay Validation

Marcos Sérgio Rodrigues Leal

Supervisor: Prof. Dr. Flavio Bezerra Costa

M.Sc Dissertation presented to GraduateProgram in Electrical and Computer Engi-neering (area: Automation and Systems) aspart of the requirements to obtain the Masterof Science degree.

Número de Ordem do PPgEEC: M559Natal, RN, Sept 06th, 2019

Leal, Marcos Sérgio Rodrigues. Development of an FPGA-based real-time power system simulatorfor traveling wave-based protective relay validation / MarcosSérgio Rodrigues Leal. - 2019. 143 f.: il.

Dissertação (Mestrado) - Universidade Federal do Rio Grandedo Norte, Centro de Tecnologia, Programa de Pós-Graduação emEngenharia Elétrica e de Computação (PPgEEC), Natal, RN, 2019. Orientador: Prof. Dr. Flavio Bezerra Costa.

1. Real-time simulation - Dissertação. 2. Hardware-in-the-loop - Dissertação. 3. EMTP program - Dissertação. 4. Travelingwave-based protection - Dissertação. 5. FPGA - Dissertação. 6.DSP - Dissertação. I. Costa, Flavio Bezerra. II. Título.

RN/UF/BCZM CDU 004.383.4

Universidade Federal do Rio Grande do Norte - UFRNSistema de Bibliotecas - SISBI

Catalogação de Publicação na Fonte. UFRN - Biblioteca Central Zila Mamede

Elaborado por Kalline Bezerra da Silva - CRB-15 / 327

To my parents, Ana Meire RodriguesLeal and Adauto Borges Leal, andmy brother, Lucas Ramon RodriguesLeal, the reason for it all.

Acknowledgment

To God in the first place for this opportunity.To my parents, Ana Meire Rodrigues Leal and Adauto Borges Leal, and my brother,

Lucas Ramon Rodrigues Leal, the most important people of my life. I thank them for thetrust and daily efforts made to support my education.

To my grandparents, Maria, Tiago, Ana ("Dona Ana") and Antônio Borges (my brother"Borjão"), good-hearted people. I thank them for their daily prayers dedicated to me.

To Albano Nascimento and Wanda Bastos, my parents from Natal, I thank them verymuch for the support.

To all my family, I am grateful for their support and for teaching me the true meaningof family.

To my supervisor professor Dr. Flavio Bezerra Costa for the guidance, opportunity,advisement, and support in the making of this dissertation. As my grandfather would say:"Dr. Flavio is a giant!".

To my colleagues of the ProRedes research group for their support during this journey,especially Mônica M. Leal, Rafael Lucas, Max Marques, Cícero Josean, Igor Prado, Ro-drigo Prado, Daniel Marques, Lucas Simões, Frankelene Pinheiro, Jéssika Fonseca, andSamuel.

To my friends Caniggia Diniz and Vanessa Sabucco, firstly, for being incredible peopleand great references, then for the provided help on the improvement of my English skills.

To all my friends, especially Mônica M. Leal, Matheus Carlos, Felipe Carlos, Ví-tor Borges, João Vítor, Wanderley Figueiredo, Lucas Andriel, Carlos Júnior, and FelipeCarvalho. Thank them for the support and incentive for the realization of this work.

To the Coordination for the Improvement of Higher Education Personnel (CAPES)and the National Council for Scientific and Technological Development (CNPq) for fi-nancial support.

To sum it up, to all of those who, directly or indirectly, contributed to the realizationof this work.

Abstract

In this work a real-time digital simulator of power systems is implemented using alow-cost custom platform based on FPGA (field-programmable gate array) proper to per-form real-time validation of traveling-wave-based transmission line protections. The op-erational view of the simulator is introduced by means of the modeling, implementation,and simulation steps of a transmission system, which is used to highlight the simulatorcapability to represent high-frequency transient phenomenon taking place transmissionlines. Hence, at first, the mathematical models of the power system used in the casestudy are presented as well as the solver design, which is developed based on the elec-tromagnetic transients program (EMTP). Then, the simulator characteristics, such as thehardware architecture, development software, communication strategies, graphical inter-face, input/output, and data export, are introduced, as well as the implementation stagesof the test system. Moreover, it addresses the implementation of a relay prototype usinga hardware based on DSP (digital signal processor), running an existing traveling-wave-based protection scheme, besides its closed-loop integration with the simulation. A GUI(graphical user interface) is developed to set the simulation parameters, including the con-ditions for applying an electrical fault, and to monitor the dynamic of the power systemused as a case study. Off-line simulations obtained from Matlab/Simulink are used tovalidate the real-time results.

Keywords: Real-time simulation, hardware-in-the-loop, EMTP program, digital re-lays, traveling-wave-based protection, FPGAs, DSP, RIO architecture.

Resumo

Neste trabalho é proposto o desenvolvimento de um simulador digital em tempo realde sistemas de potência utilizando uma plataforma customizada de baixo custo baseadaem FPGA do inglês, field-programmable gate array, adequada para realizar a validaçãoem tempo real de métodos de proteção aplicados a linhas de transmissão baseadas em on-das viajantes. A descrição do simulador se desenvolve a partir das etapas de modelagem,implementação e simulação de um sistema de transmissão, que é usado para destacara capacidade do simulador de representar fenômenos transitórios de alta freqüência emlinhas de transmissão. Assim, inicialmente, o equacionamento matemático dos modelosimplementados bem como o desenho geral do solver, que é desenvolvido tomando comoreferência o programa de transitórios eletromagnéticos (EMTP), são apresentados. Emseguida, são apresentadas as características do simulador, como a arquitetura de hard-ware, software de desenvolvimento, estratégias de comunicação, interface gráfica, mó-dulos de entrada/saída e exportação de dados, bem como os estágios de implementaçãodo sistema de teste. Adicionalmente, neste trabalho propõe-se a implementação de umrelé protótipo usando um dispositivo de hardware baseado em DSP do inglês, digital sig-nal processing, executando um esquema de proteção baseado na teoria ondas viajantes,além de sua integração em malha fechada com a simulação. Uma interface gráfica (GUIdo inglês, graphical user interface) é desenvolvida para que os parâmetros de simulaçãosejam definidos, incluindo as condições para aplicação de faltas elétricas, e monitorara dinâmica do sistema de potência utilizado como estudo de caso. Simulações offlineobtidas do Matlab/Simulink são usadas para validar os resultados em tempo real.

Palavras-chave: Simulação em tempo real, hardware-in-the-loop, programa EMTP,relés digitais, proteção de ondas viajantes, FPGA, DSP, arquitetura RIO.

Contents

Summary i

List of Figures iv

List of Tables viii

List of Symbols ix

List of Symbols and Abbreviations ix

List of Abbreviations xi

1 Introduction 11.1 Electromagnetic Transients Simulation of Power Systems . . . . . . . . . 21.2 Real-Time Simulation of Electromagnetic Transients of Power Systems . 31.3 Digital Real-Time Simulation: Challenges . . . . . . . . . . . . . . . . . 51.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.5 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.6 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.7 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.8 Work Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 State-of-The-Art 92.1 DSP-Based Real-Time Simulators . . . . . . . . . . . . . . . . . . . . . 92.2 Supercomputer-Based Real-time Simulators . . . . . . . . . . . . . . . . 102.3 CPU-Based Real-Time Simulators . . . . . . . . . . . . . . . . . . . . . 102.4 FPGA-based Real-Time Simulators . . . . . . . . . . . . . . . . . . . . 112.5 Commercial Real-Time Simulators . . . . . . . . . . . . . . . . . . . . . 142.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 EMTP Models of Power Systems 173.1 Linear Lumped Elements Modeling . . . . . . . . . . . . . . . . . . . . 17

3.1.1 Generic Formulation . . . . . . . . . . . . . . . . . . . . . . . . 173.1.2 Numerical Integration Methods . . . . . . . . . . . . . . . . . . 183.1.3 Choosing The Numerical Integration Method . . . . . . . . . . . 193.1.4 Resistance (R) Element . . . . . . . . . . . . . . . . . . . . . . . 203.1.5 Inductance (L) Element . . . . . . . . . . . . . . . . . . . . . . . 21

i

3.1.6 Capacitance (C) element . . . . . . . . . . . . . . . . . . . . . . 223.1.7 Series RL Branch Element . . . . . . . . . . . . . . . . . . . . . 233.1.8 Series RC Branch Elements . . . . . . . . . . . . . . . . . . . . 243.1.9 Others Branches Combinations . . . . . . . . . . . . . . . . . . . 26

3.2 Switch Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.3 Voltage Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.4 Graphic Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.5 Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.5.1 Mathematical Formulation . . . . . . . . . . . . . . . . . . . . . 313.5.2 Solution for a Lossless Line . . . . . . . . . . . . . . . . . . . . 333.5.3 Lossy Transmission Line Model . . . . . . . . . . . . . . . . . . 34

3.6 Network Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.7 EMTP algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.7.1 Parallelism to be exploited in the EMTP . . . . . . . . . . . . . . 383.8 Simulation of a Single-phase Transmission System . . . . . . . . . . . . 39

3.8.1 Single-phase Transmission System . . . . . . . . . . . . . . . . . 393.8.2 Offline Simulation Results . . . . . . . . . . . . . . . . . . . . . 42

3.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4 Digital Relays 454.1 Power System Under Study . . . . . . . . . . . . . . . . . . . . . . . . . 454.2 Relay Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.3 Analog Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.4 Anti-Aliasing Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.5 A/D Conversion Module . . . . . . . . . . . . . . . . . . . . . . . . . . 504.6 Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.6.1 Phasor-Based Protection of Transmission Lines . . . . . . . . . . 514.6.2 Traveling-Waves-Based Relay . . . . . . . . . . . . . . . . . . . 54

4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 Real-Time Simulator Design 635.1 The developed Real-Time Simulator: Physical Setup . . . . . . . . . . . 635.2 Hardware Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2.1 FPGA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 655.2.2 Single Board RIO-9637 (sbRIO-9637) . . . . . . . . . . . . . . . 675.2.3 TMS320F2833x . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.3 Application Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715.3.1 LabVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715.3.2 Code Composer Studio - CCS . . . . . . . . . . . . . . . . . . . 71

5.4 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725.4.1 Computational Model of the Power System . . . . . . . . . . . . 72

5.5 Goals and Demands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.6 Numeric Representation . . . . . . . . . . . . . . . . . . . . . . . . . . 745.7 Time-Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755.8 General Programming Architecture . . . . . . . . . . . . . . . . . . . . . 75

5.8.1 Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . 775.8.2 Pre-Calculation Stage . . . . . . . . . . . . . . . . . . . . . . . . 785.8.3 Producer-Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 815.8.4 Consumer-Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 845.8.5 Receiving the Simulation Parameters . . . . . . . . . . . . . . . 845.8.6 EMTP Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855.8.7 Traveling-Wave-Based Transmission-Line Relay . . . . . . . . . 97

5.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6 Results 1036.1 Real-Time Simulation Validation . . . . . . . . . . . . . . . . . . . . . . 1036.2 Device Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046.3 Validation of the Real-Time Simulation with a Traveling-Wave-Based

Transmission-lines Relay . . . . . . . . . . . . . . . . . . . . . . . . . . 1086.3.1 Protection Settings . . . . . . . . . . . . . . . . . . . . . . . . . 1086.3.2 Case 1: Fault Far 150 km from Bus 1 . . . . . . . . . . . . . . . 1096.3.3 Case 2: Fault Far 41 km from Bus 1 . . . . . . . . . . . . . . . . 1116.3.4 Case 3: Fault Far 40 km from Bus 1 . . . . . . . . . . . . . . . . 1126.3.5 Case 4: Fault Far 20 km from Bus 1 . . . . . . . . . . . . . . . . 114

6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7 Conclusion 1177.1 General Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

7.2.1 Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Bibliography 119

List of Figures

1.1 Hil setups: a) CHIL and, b) PHIL. Adapted from [Faruque et al. 2015]. . 4

3.1 Norton equivalent circuit for linear lumped elements. . . . . . . . . . . . 183.2 Function u(t). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.3 The resistance R element and its discrete-time model. . . . . . . . . . . . 203.4 An inductance L element. . . . . . . . . . . . . . . . . . . . . . . . . . . 213.5 Norton equivalent circuit of a lumped inductance. . . . . . . . . . . . . . 223.6 A capacitance C element. . . . . . . . . . . . . . . . . . . . . . . . . . . 223.7 Norton equivalent circuit of a lumped capacitance. . . . . . . . . . . . . . 233.8 A series RL branch element. . . . . . . . . . . . . . . . . . . . . . . . . 233.9 Norton equivalent circuit of a lumped RL branch. . . . . . . . . . . . . . 243.10 A series RC branch element. . . . . . . . . . . . . . . . . . . . . . . . . 253.11 Discrete circuit of a lumped RL branch. . . . . . . . . . . . . . . . . . . 253.12 Norton equivalent circuit of a lumped RC branch. . . . . . . . . . . . . . 263.13 Switches representation. . . . . . . . . . . . . . . . . . . . . . . . . . . 273.14 Single-phase system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.15 Combination of the S and L element into a single Norton equivalent circuit. 293.16 Computational view of the single-phase system. . . . . . . . . . . . . . . 293.17 Transmission lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.18 Propagation of traveling waves in transmission lines. Adapted from [Costa

et al. 2017]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.19 Transmission line illustration. . . . . . . . . . . . . . . . . . . . . . . . . 313.20 Computational transmission line model. . . . . . . . . . . . . . . . . . . 343.21 Lossy transmission line approximation. . . . . . . . . . . . . . . . . . . 343.22 Phase-modal transformation operation. . . . . . . . . . . . . . . . . . . . 363.23 EMTP-based program. . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.24 Single-phase transmission system. . . . . . . . . . . . . . . . . . . . . . 403.25 Single-phase transmission system. . . . . . . . . . . . . . . . . . . . . . 413.26 Computational form of the single-phase transmission system. . . . . . . . 413.27 Comparing results obtained from the real-time simulator, matlab pro-

gramming environment and Simulink. a) current at CB1. b) current atCB2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.28 Comparing results obtained from the real-time simulator, matlab pro-gramming environment and Simulink. a) current at CB1. b) current atCB2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

iv



4.1 Power system under study. . . . . . . . . . . . . . . . . . . . . . . . . . 464.2 Relay building blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 474.3 Auxiliary potential transformer. . . . . . . . . . . . . . . . . . . . . . . . 474.4 Auxiliary current transformer. . . . . . . . . . . . . . . . . . . . . . . . 484.5 Low-pass filter design. . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.6 Bode diagram presenting magnitude and phase response of a Butterworth

filter: a) depicts the filter magnitude response; b) illustrates the filter phaseresponse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.7 Current monitored at filter input and output. . . . . . . . . . . . . . . . . 504.8 Illustration of the sampling and hold process regarding the A/D conver-

sion module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514.9 Module estimation of the current phasor (|IA,S|) measured by relay 1 (Fig-

ure 4.1) of the power system under study. . . . . . . . . . . . . . . . . . 534.10 Phase estimation of the current phasor (φ(IA,S)) measured by relay 1 (Fig-

ure 4.1) of the power system under study. . . . . . . . . . . . . . . . . . 534.11 The trajectory followed by the relative impedance (ZR) on the Z plane. . . 544.12 Relay building blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.13 Lattice diagram illustrating the traveling waves propagation in a transmis-

sion line right after the occurrence of an internal fault at the time tF . . . . 564.14 Protected, uncertainty, and unprotected zones. . . . . . . . . . . . . . . . 584.15 Simulation results regarding the operation of a traveling-wave-based re-

lay: cases a), b), and c) illustrate the current at the relay 1 input, thewavelet coefficient calculated by its detection unit, and the trip signal,determined after the traveling wave detection and according to the pro-tection equation; cases d), e), and f) illustrate those results consideringrelay 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.16 Closer view on the simulation results regarding the operation of a traveling-wave-based relay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.17 Closer view on the simulation results regarding the operation of a traveling-wave-based relay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.1 Physical setup of the real-time simulator. . . . . . . . . . . . . . . . . . . 645.2 Hardware devices used in the real-time simulator design. . . . . . . . . . 645.3 Illustration of modern FPGAs configuration. . . . . . . . . . . . . . . . . 665.4 Illustration of modern FPGAs configuration. . . . . . . . . . . . . . . . . 665.5 RIO technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675.6 Features of the SbRIO-9637 controller board. . . . . . . . . . . . . . . . 685.7 TMS320F2833x block diagram. . . . . . . . . . . . . . . . . . . . . . . 70

5.8 The power system used as case study. . . . . . . . . . . . . . . . . . . . 735.9 Computational model of the power system . . . . . . . . . . . . . . . . . 735.10 Standard 32-bit IEEE single-precision format. . . . . . . . . . . . . . . . 745.11 RTS programming structure. . . . . . . . . . . . . . . . . . . . . . . . . 765.12 RTS programming structure. . . . . . . . . . . . . . . . . . . . . . . . . 775.13 Computational model of the power system . . . . . . . . . . . . . . . . . 805.14 DMA channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815.15 DMA channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.16 Queue structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.17 Read/Write control function. . . . . . . . . . . . . . . . . . . . . . . . . 835.18 Phasor Estimator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845.19 Distance Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845.20 Updating the graphic indicators. . . . . . . . . . . . . . . . . . . . . . . 855.21 Diagram illustrating the logic implemented to receive the simulation pa-

rameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865.22 Diagram of an EMTP-type algorithm. . . . . . . . . . . . . . . . . . . . 875.23 Voltage source unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875.24 Auxiliary transmission line unit (ATLU). . . . . . . . . . . . . . . . . . . 885.25 Auxiliary unit for one transmission line. . . . . . . . . . . . . . . . . . . 895.26 Transmission line unit (TLU). . . . . . . . . . . . . . . . . . . . . . . . 895.27 Transmission line model. . . . . . . . . . . . . . . . . . . . . . . . . . . 905.28 Lumped Element Unit (LEU)/Network Reduction Unit (NRU). . . . . . . 915.29 Lumped Element Unit (LEU). . . . . . . . . . . . . . . . . . . . . . . . 915.30 Network Solution Unit (NSU). . . . . . . . . . . . . . . . . . . . . . . . 925.31 Subsystem 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935.32 Subsystem 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935.33 Subsystem 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945.34 Trip logic selection unit. . . . . . . . . . . . . . . . . . . . . . . . . . . 945.35 Trip logic selection unit. . . . . . . . . . . . . . . . . . . . . . . . . . . 955.36 Fault logic unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965.37 Current measurement unit. . . . . . . . . . . . . . . . . . . . . . . . . . 965.38 General relay structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 985.39 Acquiring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005.40 Detection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.41 Protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.42 GPIO setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

6.1 Power system under study. . . . . . . . . . . . . . . . . . . . . . . . . . 1036.2 General results obtained from the real-time simulator and the ones ob-

tained from Matlab/Simulink. a) current at CB1. b) current at CB2. c)voltage at bus 1. d) voltage at bus 2. . . . . . . . . . . . . . . . . . . . . 105

6.3 A closer view of the results generated using the real-time simulator andthe ones obtained from Matlab/Simulink. a) current at CB1. b) current atCB2. c) voltage at bus 1. d) voltage at bus 2. . . . . . . . . . . . . . . . . 106

6.4 A closer view of the results generated using the real-time simulator andthe ones obtained from Matlab/Simulink. a) current at CB1. b) current atCB2. c) voltage at bus 1. d) voltage at bus 2. . . . . . . . . . . . . . . . . 107

6.5 Protected, uncertainty and unprotected zones. . . . . . . . . . . . . . . . 1096.6 Results obtained from the implemented hardware-in-the-loop setup con-

sidering a fault taking place the transmission line far 150 km from bus1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.7 Results obtained from the implemented hardware-in-the-loop setup con-sidering a fault taking place the transmission line far 41 km from bus 1. . 113



List of Tables

1.1 The classification of electromagnetic transients in power systems. . . . . 2

2.1 Summary of the literature review related to the real-time simulation ofelectric power systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Summary of some EMTP lumped models using the backward Euler method. 263.2 Summary of the some EMTP lumped models using trapezoidal method. . 273.3 Power System Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 403.4 Parameters of the computational model (∆t = 20µs and dF = 200 km). . . 41

5.1 CPU specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685.2 FPGA specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685.3 Analog input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 695.4 Analog output characteristics. . . . . . . . . . . . . . . . . . . . . . . . 695.5 3.3 V digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695.6 Pre-calculation required for the Lumped elements model. . . . . . . . . . 785.7 Pre-calculation required for the transmission line model. . . . . . . . . . 795.8 Protection System Parameters. . . . . . . . . . . . . . . . . . . . . . . . 985.9 Registers Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 99

6.1 Device Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

7.1 Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

viii

List of Symbols

∆t Time stepR Lumped resistanceL Lumped inductanceC Lumped capacitanceRL Resistive-inductive branchRC Resistive-capacitive branchRLC Resistive-inductive-capacitive branchi Currentv VoltageReq Equivalent ResistanceI(t−∆t) Historic currentG ConductancetOp Opening timetCl Closing timeZeq Characteristic equivalent impedanceI(t− τ) Historic current of the transmission line modelτ traveling wave propagation timeω frequency variablez(ω) Series impedancey(ω) Shunt admittancer resistance per unit of lengthl inductance per unit of lengthg conductance per unit of lengthc capacitance per unit of lengthYc Characteristic admittanceZc Characteristic impedanceγ Propagation functionα Attenuation factorβ Phase constantd Transmission line lengthYeq Characteristic equivalent admittanceh Constant

d Transmission line lengthYeq Characteristic equivalent admittanceh ConstantT Clark’s matrixY Admittance matrix of the power systemSo Operation vectorSR Restriction vectorZN Line impedanceZR Relative impedancef Power system operational frequencyfs Sampling frequencydF Fault distancec Speed of lightvt Traveling wave velocity for a lossless linesx Scale coefficientwx Wavelet coefficientnφ,F Fault inception angleTe Execution time

List of Abbreviations

ASICs Application specific integrated circuitsADC Analog to digital converterAI Analog inputALTU Auxiliary transmission line unitAO Analog outputCB Circuit breakerCCVT Capacitor voltage transformerCHIL Controller hardware-in-the-loopCLB Configurable logic blockCMU Current measurement unitCOTS Commercial-off-the-shelf computerCPU Central processing unitCT Current transformerDAC Digital to analog converterDFT Discret Fourier TransformDIO Digital input/outputDMA Direct memory accessDSC Digital signal controllerDSP Digital signal processorEMT Electromagnetic transientEMTP Electromagnetic transients programFACTS Flexible ac transmission systemsFIFO First-input-first-outputFL Fault logic unitFPGA Field programmable gate arrayGPIO General-purposed-input-outputGPP General-purpose processorGUI Graphical user interfaceHiL Hardware-in-the-loopHuT Hardware-under-testHVDC High voltage direct current transmission systemLEU Lumped element unitLUT Lookup tablesMOV Metal Oxide VaristorNRU Norton reduction unitNSU Network solution unit

PHIL Power hardware-in-the-loopPSMS permanent magnet synchronous machinePWM Pulse width modulationR&D Research and developmentRIO Reconfigurable Input/OutputRTS Real-time simulatorSOP Sum of productSR Shift register elementSTARTCOM Reactive power compensator systemSW Switch elementTL Trip logic selection unitTLU Transmission line unitTNA Transient network analyzerVHSIC Very-high-speed integrated circuitVSC Voltage source converterVSU Voltage source unit

Chapter 1

Introduction

The current power system environment is becoming more and more complex. Thehosting to the electrical network of subsystems and equipment such as renewable genera-tion systems (e.g., solar and wind power plants) and high voltage direct current (HVDC)transmission systems, besides the own growth in size of existing electrical network, hasdriven the R&D teams (research and development) to study and develop new technologiesaiming to ensure the operational conditions of the power system and comply the safety,reliability and efficiency requirements.

Protection and control systems are among the fields that most have had advances inthe context of modern power systems. The protection scenario includes the developmentof relays with rapid decision making such as the traveling-wave based relays of trans-mission lines, which is designed to operate based on the arrival of the voltage/currenttraveling waves at the line terminals and to provide fault diagnoses in the order of few ms(e.g., the relay SEL-T400L lasts 1ms to act). For this application, the protection systemneeds to operate at a high sampling frequency (e.g., the SEL-T400L operates at 1MHz).It needs to be able to describe fault transients accurately. In this context, it is essential toperform EMTs (electromagnetic transient) studies due to uncontrolled switching events,such as faults in transmission lines, especially in the sense of the fault detection meth-ods, where the magnitude of high-frequency components can be used as a fault identifier[Costa 2014].

In addition to the protection area, there are many other important topics straight re-lated to EMTs analysis, such as energy quality studies and insulation coordination, deter-mination of component ratings, surge arrester influences, precise determination of shortcircuits [Mahseredjian et al. 2009]. EMT studies, indeed, are essential and have sup-ported analytically the development of technologies and, consequently, the power systemmodernization process.

Conceptually EMTs are defined as temporary overvoltages and overcurrents causedby a change in the power system topology due to controlled and uncontrolled switchingevents, lighting strike, and other disturbances [Dommel and Meyer 1974]. It can span ina wide range of frequency, from DC to several MHz [Chen 2012].

CHAPTER 1. INTRODUCTION 2

Table 1.1 summarizes the classification of transient phenomena in power systems, thecomprised frequency range, and examples [Mahseredjian et al. 2009]. Faults taking placea transmission line fall into the list of uncontrolled events, thereby, the analysis of voltageand current waveforms during the transient state may reveal frequency components up to20 kHz. The possibility of representing these frequency content, i.e., the reproduction ofthe transient regime with the desired precision, pave the way for developing new studiesand technologies which take into account information contained in that time window.

Table 1.1: The classification of electromagnetic transients in power systems.

Transients Frequency range ExamplesVery fast front 100 kHz to 50 MHz EMTs due to restrikes in gas insu-

lated substationsFast front 10 kHz to 3 MHz EMTs due to lighting strokesSlow front fundamental to 20 kHz EMTs due to switching events.

E.g., faults in transmission linesTemporary Up to 1 kHz EMTs due to open line energiza-

tion, load-shedding

1.1 Electromagnetic Transients Simulation of Power Sys-tems

The difficulty for conducting tests of the operating power system, as well as its non-viability (costly and time-consuming tasks), motivated researchers to develop platformsdesigned to imitate, for an implemented model, the real system’s behavior. [Dommel1969] reported the fundamental theory regarding modeling and computational solutionfor the time-domain calculation of EMTs in power systems, the EMTP program, which isbuilt by taking advantage of the possibility to represent mathematically the power systemelements in the form of equivalent circuits, basically composed of sources and resistances,and from using the nodal analysis technique. The off-line EMT simulation software pack-ages such as ATP, PSCAD/EMTDC, EMTP-RV, MICROTRAN, NETOMAC, etc., are re-ferred to EMTP-type due to their structure be designed based on the theory presented in[Dommel 1969].

The possibility to reproduce EMTs of a power system, considering a range of situa-tions, have made simulation platforms essential tools to carry out performance evaluationof protection and control methods, i.e., before being embedded in the commercial equip-ment hosted in the real system. These simulation tools fall into offline and real-time cat-egories. The offline simulation environments are commonly used in applications wherethe time constraint is not a determining factor, e.g., a simulator can spend 1 h to compute2 s of a power system’s behavior. One of the benefits of this approach is the possibilityof using more complex models. The real-time simulation platforms of power systemsare commonly used where compliance with simulation time is essential, e.g., a real-time


simulator will spend 2 s to compute 2 s of a power system’s behavior. This approach canbe used to place the simulator linked with another system operating in real-time, such as aphysical subsystem, equipment (e.g., a relay) or hardware device (e.g., a prototype relay).Therefore, real-time simulation platforms enable performing studies in a more realisticscenario.

1.2 Real-Time Simulation of Electromagnetic Transientsof Power Systems

Real-time digital simulation of power systems is a method based on a time-domainsolution which generates results in synchronism with the real-world clock time reproduc-ing accurately the dynamics of the real system being modeled [Faruque et al. 2015], i.e.,for a common starting point of the real power system and its computational form imple-mented in a real-time simulator (e.g., the steady state), the behavior of both must matchand the results (measurements of voltage and current) can be monitored, in synchronism,as time goes by. Real-time digital simulators (RTSs) have been widely used in power sys-tems and power electronics as tools for designing, performing analysis of electromagnetictransients, and for tests of control and protection schemes [Guillaud et al. 2015].

One of the main reasons justifying the use of real-time simulation tools applied toelectrical systems is the possibility of conducting real-time studies using the hardware-in-the-loop (HiL) setup, in which the simulator is linked, in a closed-loop, with physicaldevices (a hardware-under-test, HuT). Consequently, several applications can be coveredusing this mode. For instance, using such configuration it is possible to carry out testsin real-time of commercial relays or prototypes implemented in a hardware device. Fur-thermore, the possibility to perform simulation of high-frequency phenomenon of powersystems, in a general context, pave the way for developing and test new control and pro-tection schemes such as the traveling-wave based protection methods. Therefore, newprotection and control algorithms can be validated and tested from a perspective closer toreality.

The HiL configuration can be classified based on the occurrence of power transfer toor from the HuT as CHIL (controller hardware-in-the-loop) and PHIL (Power hardware-in-the-loop). The CHIL nomenclature is used when the simulator interacts with the con-troller board by means the exchange of I/O signals, i.e., no power transfer takes place. Onthe other hand, the PHIL nomenclature is used when there is power transfer to or from theHuT [Faruque et al. 2015]. In this case, a power processing interface is required, as wellas an external source (generating or absorbing power). The signals from the simulator areused as a reference, amplified and applied to the equipment under test (e.g., testing ma-chines). Figure 1.1 depicts such a classification. The challenging configuration of today,referenced as hybrid simulation, is based on the closed-loop link established between asimulated system and a physical analog subsystem. In [Mao et al. 2018] is presented aninterfacing system for a hybrid simulator.


Digital real-time simulator

Controller board(HuT)

A/D and D/A conversion

Feedbacksignals

Feedbacksignals

Controlsignals

Controlsignals

Digital real-time simulator

Power hardware(HuT)

Forwardsignals

D/A

~~

A/D

Sensor

Feedbacksignals

a) b)

Amplifier

Powerinterface

CHIL PHIL

Figure 1.1: Hil setups: a) CHIL and, b) PHIL. Adapted from [Faruque et al. 2015].

Besides HiL approach, real-time simulators allow real-time studies to be carried outtaking into account a range of extreme situations and conditions, something that couldbe costly and cumbersome from the point-of-view of tests in the real system, and time-consuming if done by using offline simulators. Moreover, a functional application ofreal-time simulation is regarding educational purposes such as engineers, operator andtechnician training.

Before the digital simulators, TNAs (transient network analyzers) were used to EMTssimulation of power systems. These analog simulators were developed based on scaled-down physical components models of the power system, e.g., the transmission lines beingrepresented by means a cascade analog pi sections. Some advantages of this approachare: the simulations are performed naturally in real-time; it allows the test of real pro-tection/control devices as well as the interface with digital simulators. However, due totheir complexity, high cost, size limitations and, long setup and changeover times, as wellas due to advances of computing, the TNAs have been replaced by the real-time digitalsimulators.

The real-time digital simulators of today are based on parallel processing, whichcan make use as hardware architecture either multi-core CPUs (central processing unit),general-purpose processors (GPPs), digital signal processors (DSPs) or computer clusters[Marti and Linares 1994, Pak et al. 2006, Hollman and Marti 2003], and more recentlyFPGAs.


Usually, CPU-based RTSs are better options for simulating large power systems usinga reasonable time-step (e.g., in order of few microseconds). However, due to its sequentialnature these simulators have limitations on the minimum integration time-step size, e.g.,some architectures allow to use 50 µs (20 kHz) as the time-step to represent voltage/cur-rent high-frequency transients, thereby, the representation of frequency components upto 10 kHz (according to Nyquist criterium). This ends up being a drawback for simula-tions of higher-order terms, such as the ones contained in the EMTs of power convertersor in traveling wave transients taking place in transmission lines. Regarding the protec-tion area, some property (e.g., the magnitude) of this frequency content can be used as aparameter for fault detection.

Addressing those technical limitations, efforts have been made in the development ofFPGA-based real-time simulators as well as its integration with conventional RTSs. Forinstance, [Parma and Dinavahi 2007, Matar and Iravani 2011] present designs to performreal-time simulations of power electronic systems, electric machines and the associatedcontrol strategies, whereas [Chen and Dinavahi 2009, Matar and Iravani 2013, Chen andDinavahi 2013, Razzaghi et al. 2016] describe designs to carry out real-time simulationsof power systems. [Liu and Dinavahi 2018] presents the implementation of a power trans-former for electromagnetic transients studies.

1.3 Digital Real-Time Simulation: ChallengesIn a simplistic way, RTSs can fit into one of these two categories:

• Commercial RTSs.• Laboratory-scaled RTSs.

Commercial RTSs of power systems are designed based on hardware architectureswith high computing power. These simulators are commonly used to be applied to a widerange of applications using a defined time-step, probably chosen for the worst scenarioand obeying the existing compromise between the size of the simulated system vs mini-mum time-step required. Those attributes make them, justifiably and, in a relative manner,expensive RTSs. Some available commercial RTSs are the RTDS (from RDTS Technolo-gies Inc.), HYPERSIM (from Hydro-Quebec), eMEGAsim (from OPAL-RT Technolo-gies Inc.), NETOMAC (from SIEMENS AG) and, Typhoon HIL (Typhoon HIL Inc.).

Laboratory-scaled RTSs usually have a more limited computational power and, there-fore, are usually applied for more specific studies. Despite, according to the used hard-ware architecture, such simulators can be build to allow smaller integration time-stepsthan the commercial ones.


As highlighted earlier, in the context of power system simulation, there is a need of us-ing smaller simulation time-steps in order be able to compute accurately high-frequencytransients of power systems in the sense of taking advantage of this information to performstudies and cover new applications, which potentially can be used to improve existing so-lutions. Taking this point of view, companies, as well as the scientific community, havebeen working towards efficient solutions in terms of processing speed. FPGA-based plat-forms are great to deal with this requirement. These devices have been included in com-mercial technologies to perform real-time simulation and tests using the HIL approach.

What makes FPGA suitable to be used as a computational core of real-time simulatorsis tied to its inherent features, such as reconfigurability and feasible parallel architecture,which make it an excellent solution for speeding up the calculations without compromis-ing accuracy. Other reasons are related to the increased resources (e.g., number of logicresources, RAM blocks, DSPs blocks) and computational power of the FPGAs by theyears as well as its great performance, based on the efficient implementations, in terms ofenergy efficiency.

1.4 MotivationThe motivation of this work is supported on the importance to show the main steps to

perform simulations in real-time using a customized-low-cost platform based on FPGAwith a high-level and friendly programming language. Thus, verify a solution for thecalculation of traveling waves taking place in transmission lines. In other words, the mo-tivation is based on the possibility of providing theoretical and practical information forthe development of a real-time simulator, customized, low-cost, and suitable to performstudies of traveling waves taking place transmission systems. In addition, it is intendedto verify a friendly programming environment as an alternative to implement componentmodels of power systems and, thus, use strategies to perform real-time studies.

A second motivation attached to this work is based on the possibility to carry out stud-ies related to protection systems based on traveling waves using the HiL configuration.Therefore, it is intended to verify the possibility of implementing a traveling-wave relayand place it in a closed-loop with a simulated system in real-time.

1.5 ObjectivesThe goal of this work is to develop a simulation platform suitable to perform real-time

simulations of power systems with hardware-in-the-loop to support the development andassessment of traveling wave-based relays using a low-cost hardware architecture basedon FPGA.

To achieve the expected results, the following specific objectives have been defined:

• Implementation, in the FPGA, of power system models, such as transmission line,lumped elements, switches, sources, and fault circuit following concepts of EMTPprograms.


• The integration of an actual signal generator to the simulation, which is important tohighlight the possibility to integrate actual power system components in real-timesimulations.

• Implementation of a relay prototype in a DSP (Digital signal processor), first run-ning a conventional protection function and, later, executing a protection scheme oftraveling waves.

• Provide the integration link between the relay and power system simulated in real-time in a hardware-in-the-loop. The prototype performance is evaluated for the caseof faults applied to transmission lines.

• The implementation of a graphical user interface (GUI) for setting the simulationparameters and also monitor, in real-time, the dynamic of the simulated power sys-tem.

• To evaluate and validate the results in real-time by means of the comparison withthose obtained from offline simulators.

1.6 ContributionsThe contributions of this work are as follows:

• A methodology to perform real-time simulations of power systems using an low-cost FPGA-based platform to support the development and assessment of travelingwave-based protective relays in a hardware-in-the-loop connection.

• To provide details regarding the implementation and development of a platformsuitable to perform a hardware-in-the-loop real-time simulation by using a high-level and friendly programming language.

1.7 MethodologyThe methodology presented in this research goes from the delimitation of the problem

to the validation of the final results in order to achieve the established goals.Firstly, technical arguments are searched in the literature to put in evidence the impor-

tance of real-time simulation tools for carrying out EMT studies of the electrical powersystem. The understanding of the constraints present in existing real-time simulation plat-forms which end up limiting its use for some specific studies is vital since the motivationof this research is also intended to address those limitations. A theoretical investigationof researches, proposing hardware platforms designed to overcome constraints in existingRTSs, is done.

Thus, a literature review on the RTS applied to EMT studies is made. Then, this workpresents a step-by-step description of the implementation of a real-time simulator usinga low-cost FPGA-based platform, taking into account theoretical and practical aspects,as well as its integration with an implemented relay prototype. The real-time results arepresented and validated by comparing them with those obtained using Matlab/Simulink.


1.8 Work OutlineThis proposal is organized in six chapters:

• Chapter 1 presented an introduction about the real-time simulation technologiesfor EMT studies of electric power systems and its application.

• Chapter 2 illustrates the state-of-the-art regarding digital real-time simulators.• Chapter 3 describes the computational models of power systems components used

in EMTP-based programs. Moreover, it provides simulations results concerning theimplementation of a power system using the theory presented in such chapter.

• Chapter 4 introduces the main building blocks of digital relays. Furthermore, itprovides an introduction regarding a traveling-wave-based transmission-line method.Moreover, it present simulation results concerning the power system presented inChapter 3 for such a relay providing the transmission line protection.

• Chapter 5 present the hardware architectures employed to build the simulator, theFPGA-based simulator design focusing on the power system implementation usedas a case study, and the implementation of a traveling-wave-based transmission-linerelay in DSP.

• Chapter 6 presents the real-time results and, also, its comparison with the onesobtained from offline simulators.

• Chapter 7 presents the conclusions obtained in the development of this work, aswell as proposal topics for future researches.

Chapter 2

State-of-The-Art

This chapter provides a review regarding the development of real-time digital simula-tors of power systems. At first, it highlights the works concerning the primary DSP-basedarchitectures. Then, it is underlined proposals regarding the PC-clusters based simula-tors. The propositions related to the development of FPGAs-based simulation platformsare, then, presented. These last ones appeared from the needs to carry out real-time simu-lations of power systems using small time-steps (e.g., from hundreds of ns to decades ofµs). Moreover, it is introduced, generically, the architectures of two commercial PC-basedsimulators, the RTDS (from RDTS Technologies Inc.) and eMEGAsim (from OPAL-RTTechnologies Inc.).

2.1 DSP-Based Real-Time SimulatorsMathur and Wang (1989) presented the first real-time simulator applied to the analysis

of electromagnetic transients in transmission lines. A simple three-phase system (com-posite by source, impedance, and open-ended line) was implemented, using a single DSPchip of the EVAL KIT NEC77230 development kit, and simulated in real-time. For such,a time-step of up to 85 µs could be used to achieve real-time simulation. Today’s timestep required for EMT simulation of power systems is at least 50 µs.

Wang and Mathur (1989) is an extension of the previous work with the innovationof taking into account the frequency-dependent transmission line model. For the samehardware architecture, a time-step of up to 85 µs could be used to achieve real-time simu-lation. This minimum value limits the simulator resolution for the representation of EMTsof transmission lines.

Kezunovic et al. (1994) proposed a real-time digital simulator of power systems withapplications related to relay testing. The hardware architecture used combines DSPs anda commercial-off-the-shelf (COTS) computer. The firsts devices are used to handle thecalculations regarding the instrument transformers (CTs and CCVT) and to provide inter-facing with external devices, whereas the COTS are used to compute the remaining powersystem components. A Western Area Power Administration 345 kV network was imple-mented and simulated using a 50 µs integration step considering three test cases (varyingthe network complexity). The simulator spends 81 µs and 119 µs to update the outputvariables of a network with 30 and 42 buses, respectively. The results presented are not

CHAPTER 2. STATE-OF-THE-ART 10

in real-time since the integration time-step was smaller than the simulator computationtime. However, real-time simulation is justified by replacing the COST for a more robustcomputer. This paper also covers a HIL test.

Dufour et al. (1996) proposed to perform real-time simulation of transmission lineswith frequency-dependent parameters using a dual-DSP card. An efficient method forfitting both surge impedance and the propagation function of the transmission line is pre-sented. The minimum time-step allowed for transmission system (source, line, and load)simulation used as the case study is 145 µs. This value limits the representation of EMTsin transmission lines due to electric fault events (required at least 50 µs). The authorjustifies the use of smaller time-steps using other DSPs chips.

2.2 Supercomputer-Based Real-time SimulatorsMarti and Linares (1994) proposed a solution in software for efficient implementation

of the EMTP algorithm in order to perform real-time EMTs simulations of power systemsusing superscalar computer architectures. The RISC System/6000 model 560 station wasused to perform the calculations of two power systems chosen as a case study. The mini-mum time-step allowed for simulation of the 30-node system was 107 µs, while the 38 µswas the minimum step-size admitted to performing real-time simulation of the 18-nodesystem. Although this last case being suitable for EMTs representation of power systems,less than the maximum limit of 50 µs, in this work a metric was not established relatingthe required hardware device, the minimum time-step, and the simulated power systemsize.

2.3 CPU-Based Real-Time SimulatorsDinavahi et al. (2001) proposed an approach for the real-time simulation of power

electronic controllers in power systems. The algorithm makes use of a numerical inter-polation and a variable time-step when the firing time of control signal is identified, thusreducing errors in the response of a simulated system. The 250 MHz MIPS R10000 pro-cessor was used as a hardware device to compute a voltage source converter (VSC) basedreactive power compensator system (STATCOM) and its digital controller. The resultsusing a time-step of 50 µs and the proposed method were similar to those obtained usinga fixed time-step of 5 µs. With the proposed approach a single iteration took approxi-mately 54 µs to execute. The results of the presented method are not strictly in real-time.However, this work justifies the possibility of implementing the algorithm in DSPs.

Hollman and Marti (2003) presented a real-time simulator of power systems. The pro-posed hardware architecture is based on PC-clusters linked by an efficient communicationinterface. The idea is to symmetrically distribute the simulated system into computers anduse a fast communication link among them in order to guarantee minimal simulation time-step. A 78-node system was simulated using 3 PCs and a 234-node system was run using5 PCs, both at time-step of 50 µs. This article portrays the simulator hardware architectureand scalability requirements. This last feature might ends up to limit its use in real-timeapplications that require time-steps smaller than 50 µs.


Pak et al. (2006) described a PC-cluster-based RTS. Firstly, the simulator is presentedby means of a description of the hardware setup, software, synchronization methods,and operation. Simulator architecture is formed using PC-clusters named target clus-ters, which act as the main computational engine of the simulator, and host clusters usedfor model development, compilation and loading the compiled programs into the clus-ter nodes. This architecture uses the MATLAB/SIMULINK environment as developingsoftware. A three-level 12-pulse vector-controlled variable speed AC drive was used as acase study for evaluation of the real-time simulator performance. As a result, the wholeevaluation system, formed by an AC supply, a serie filter, 3-phase 3-winding transformer,3-phase dual rectifier bridge, DC filter, and the subsystem under study which correspondsthe squirrel cage induction machine, the drive, and the digital controller, was simulatedwith a time-step of 10 µs for a maximum computation time of 5.35 µs. It provides no cov-ered information regarding how portions of the power system are distributed and handledby PCs-cluster.

Mao et al. (2018) presented a hybrid simulator of power systems. The hybrid termis referred to simulator architecture, which is composed of a physical analog subsystem(PAS), a digital simulation subsystem (DSS) and an interfacing system, thus existing in-teraction between these two subsystems. The power system is modeled in the RTDS,while the PAS is composed of physical scale-down models (e.g., generator, transformer,load, etc.). The interfacing system, based on multiple back-to-back converters in parallelwith 20 kHz (IGBT-based) switching frequency, is formed by a digital side interface, aphysical side interface, and a signal iteration system. The digital interface is modeledusing the RTDS in which a controlled current source is adjusted based on PAS measure-ments. At the physical interface, a VSC with a four-quadrant operation tracks the DSSterminal voltage. Real-time results obtained using the RTDS were used to validate theones acquired using the proposed simulator. These results demonstrated the excellent dy-namic performance of the hybrid simulator. Numerical comparisons could improve theaccuracy measurement of the simulations.

2.4 FPGA-based Real-Time SimulatorsChen and Dinavahi (2009) presented the development of an RTS based on FPGA

for simulation of electromagnetic transients in power systems. The main steps relatedto the development of the simulator, from the hardware device description, modeling(e.g., frequency-dependent transmission line model), implementation, the operation ofthe simulator to results, are presented didactically. The EMTP program was implementedin the FPGA, exploiting, when possible, several levels of parallelism. For validationpurposes, a power system was implemented and simulated using a time-step of 12 µs,which is a suitable value for EMT simulation of power systems. A HIL test could beperformed to evaluate the simulator performance when connected to an external device.


Matar and Iravani (2010) illustrated a methodology for real-time simulation of elec-tromagnetic transients of power converters using an FPGA-based hardware device. Thesimulator was designed exploiting the FPGA custom and parallel architecture in order toallow simulations to be performed using time-steps of a few hundred nanoseconds. Theconverter is implemented based on the associated discrete circuit (ADC) model, wich theON (OFF) state is represented by an inductance (capacitance), i.e., the switch is computa-tionally represented by means a Norton equivalent circuit. Consequently, the admittancematrix of the system remains constant. The solver was developed based on the EMTPtheory, exploiting when possible the parallelism levels allowed by the algorithm. Forvalidation purposes, two- and three-level VSCs were implemented and simulated. TheMatlab/Simulink results were used as a benchmark to prove simulator performance. Itwas possible to use a simulation time-step of 60 ns and yet achieving real-time simula-tion. Even the RTS be developed to perform hardware-in-the-loop real-time simulations,tests using this setup were not performed.

Matar and Iravani (2011) proposed a methodology to perform EMTs simulation inreal-time of AC machines using an FPGA-based simulator. The discrete form of the 0dq-based model was implemented taking advantages of possible degrees of parallelism. Thefirst level is attainable from existing decoupling between the electrical and mechanicalsubsystems by introducing one time-step delay between the solutions of the two sets ofequations. The second and third levels are achieved by means the parallel implementationof the matrix-vector multiplication and the primitive operations, respectively. Conse-quently, for the adopted FPGA environment, electrical machine simulations can be per-formed using a minimum time-step of 44 ns. The presented design can be used to sim-ulate field-controlled synchronous machines, permanent-magnet synchronous machines,squirrel-cage induction machine, and doubly-fed asynchronous machine. Despite, someimplementation aspects could be highlighted, such as the FPGA resources allocated tocompute the model and illustration of the power converter integration with the electricmachine.

Chen and Dinavahi (2013) presented a multi FPGA-based RTS for electromagnetictransient simulation of large power systems. For evaluation purposes, two case studieswere implemented and simulated in real-time. The first one is a 42-bus power systemimplemented using a 3-FPGA array and the other a 430-bus network simulated usinga 10-FPGA array. It was proposed a strategy of decomposition of the power systeminto clusters, e.g., calculation units regarding the same element type (e.g., transmissionline unit) are programmed in parallel using the same or in a set of FPGAs. Therefore,besides the parallelism exploited for different components models, a level of parallelismwas achieved for elements of the same type. For such a simulator, the minimum time-steps allowed were 12 and 37 µs for the 42 and 430-bus systems simulation, respectively.FPGA-based architecture can be used to simulate large power systems. Moreover, it ispossible to perform power system simulations at different rates, even though no simulationis carried out using this approach.


Matar and Iravani (2013) presented a reconfigurable FPGA-based RTS for EMTs stud-ies of power systems in real-time and faster than real-time. The simulator was developedto operate in real-time for performing closed-loop protection and control device tests witha power system being executed in real-time, while the faster than real-time operation isdesigned to carry out statistical studies quickly. The structure of the EMTP algorithmis analyzed and implemented in the FPGA taking advantage of all possibles parallelismlevels such as the ones present in the subsystems/components model, equations, and prim-itive operations. A power system used as a case study was implemented and simulatedfor the real-time and faster than real-time modes using a time-step of 5 µs. This last modeis accomplished due the simulator be able to calculate the power system output variablesevery 24 ns, thus, setting the discrete models for a step of 5 µs, the simulation time-step ischanged to 24 ns. The simulator is designed to operate in a hardware-in-the-loop mode.However, simulation using this setup was not established.

Taveiros et al. (2015) proposed an internal model state-feedback control strategy forthe regulation of rotor direct and quadrature currents for wind-driven DFIG. A hardware-in-the-loop configuration was developed to validate the proposed control performanceconsidering a real-time scenario. A DFIG-based wind energy conversion system wasimplemented using an FPGA-based platform, whereas the proposed method is executed ina DSP-based platform running at 1kHz of sampling frequency. This article focused on themethod performance, thereby, details regarding the hardware-in-the-loop implementationare not covered.

Razzaghi et al. (2016) presented the development of an automated RTS using a hard-ware device based on RIO technology which integrates into its architecture an FPGA anda real-time processor. The proposed solver integrates the Modified Augmented NodalAnalysis (MANA) method, the Fixed Admittance Matrix Nodal Method (FAMNM), theoptimal selection of the switch model conductance parameter, and the implementation ofan efficient matrix-vector multiplier. The solver was implemented by taking advantage ofparallelism levels allowed by the element models and also the presented formulation. Theproposed simulator uses the EMTP-RV environment both as a GUI and for generating thedata output file of the power system structure for the solver implemented in the FPGA.As a result, real-time simulations of a power converter and a three-phase distribution sys-tem were performed using a time-steps of 150 ns and 6.4 µs, respectively. Measurementsregarding the simulator scalability were not explored.

Ould-Bachir et al. (2017) presented a methodology to perform for real-time simulationof complex HVDC-MMC systems, with up to 501 levels, using a hardware architecturethat combines CPU and FPGAs. The modular multilevel converter, which is implementedusing FPGAs, is represented by a detailed equivalent model, which is obtained from thediscrete representation of the submodules (discrete model of a half-bridge converter) andby the assembly of a Thevenin equivalent circuit for each converter arm. Meanwhile, therest of the HVDC system is implemented using a CPU and interfaced with the converterusing the SSN (state-space nodal) technique. The simulation technique was validated bymeans of the real-time simulation of an HVDC-MMC system, implemented for the casesof converters with 101 and 501 levels and, using a single (25 µs) and multi-rate samplerate (CPU: 25 µs, FPGA: 5 µs), respectively. Information regarding the parallelism levels


to be exploited using the proposed methodology are not presented.Alvarez-Gonzalez et al. (2017) presented a high-fidelity RTS of a permanent-magnet

synchronous motor drive under stator faults in an FPGA-based platform suitable for HILtests. The machine nonlinearities, e.g., due to saturation and high-order harmonics, wereaccounted by means of data obtained from finite element solutions and stored in lookuptables (LUTs). Therefore, the PMSM model is represented by its discrete equations andby accessing data in the LUTs. The machine model is implemented in the FPGA, while sixPWM gate drivers are implemented in a controller board. Furthermore, an experimentalsetup was designed to provide data to validate the real-time implementation. Several testcases were performed such as the fault transients analysis for a wide range of operatingconditions. A good match between the results from the HIL and finite element analysiswas obtained. Albeit the FPGA is clocked at 40 MHz and simulates the system witha time-step up to 1.25 µs, the digital to analog converter (DAC) limits the outputs toa 115 kS/s. Furthermore, additional practical information about exploiting the parallelarchitecture of the FPGAs are not detailed.

Yang et al. (2018) introduced a co-simulation platform formed by the RTDS and anFPGA-based board. The interface between these two platforms is achieved using the com-putational model of transmission lines. This connection is implemented, physically, usinga bi-directional optical fiber. The proposed solver was programmed taking advantage ofthe parallelism levels of EMTP-type program. For validation purposes, a three-phase 11-bus system was split into two areas, implemented and simulated in the RTDS and FPGA.Then, a three-phase system of 141 buses was simulated using the previous concept, never-theless, with only 5 buses modeled in the RTDS. FPGA simulations were carried out withtime-steps of 5.71 and 26.16 µs for the cases 1 and 2, while in the RTDS this step-size isfixed at 50 µs. The real-time results have shown FPGA-based real-time simulators can becombined with commercial simulators for simulation of larger and complex power sys-tems, eventually, running at different sample rates. No information about FPGA resourceutilization is underlined in this work.

2.5 Commercial Real-Time SimulatorsThe Real-Time Digital Power System Simulator (RTDS) is a simulator from RTDS

Technologies Inc. It was the pioneer project among the available commercial powersystem simulators, launched in 1991, suitable for protection relay tests. McLaren et al.(1992) presented the first RTDS version comprised by parallel processing architecturebased on DSPs. Forsyth et al. (2004) introduces another version of the RTDS alreadycomposed of a hardware architecture based on clusters of PCS and suitable for closed-loop tests of protection and control systems. The RTDS simulator’s processing hardwarecomprised of rack-mounted processor cards connected to a backplane, communicatingwith the user’s workstation by means of a rack-mounted workstation interface card. In2017 it was launched the latest version of the RTDS, the NovaCor, which is based ona powerful multicore processor. It is compatible with previous hardware. Each rack-mounted NovaCor chassis features IBM’s state of the art POWER8 processor, containing10 powerful cores running at 3.5 GHz [RTDS Technologies Inc 2019]. This setup allowsan entire power system simulation to be run on a single core. FPGA-based cards can be


used with RTDS in order to achieve very small time-steps.The simulator eMEGAsim is a commercial real-time simulator from OPAL-RT Tech-

nologies Inc. Bélanger et al. (2007) presented the eMegaSIM structure as well as its usefor a range of applications, especially the ones requiring a hardware-in-the-loop config-uration for protection and control tests. Bélanger et al. (2009) presented eMegaSIM asa tool suitable to perform real-time simulations of large-scale power systems with powerelectronics equipment and integrated control systems. The simulator’s hardware architec-ture comprises a commercial-off-the-shelf (COTS) multi-core processor (Intel or AMD)module along with a fast on-chip inter-processor shared-memory communication. Thesimulated network is modeled using the Matlab/SIMULINK environment. The model iscompiled code and then downloaded into target PCs for real-time simulation.

2.6 SummaryTable 2.1 summarizes the main publications related to real-time simulation of elec-

tric power systems. The core computational engine of the real-time simulator, and thevalidation method, whether via simulations and/or experiments, are highlighted. Basedon the reviewed literature, real-time digital simulators have recently used FPGAs in itshardware architectures with the motivation to make use of its features, such as reconfig-urability, high-speed clock, and inherent parallel design, to carry out real-time simula-tions of electric power systems addressing high-frequency phenomena such as electro-magnetic transients in power converters and travelling waves transients in transmissionlines. The FPGA-based platforms have emerged as a trend for tests of control and protec-tion schemes using an HiL setup. Moreover, it can be noted a gap to be filled towards thehardware-in-loop tests aiming the development and evaluation of new control/protectionsystems, e.g., traveling wave-based transmission line protection systems.

Moreover, based on the presented works (Table 2.1), it can be noted a gap to be filledtowards the hardware-in-loop tests aiming the development and evaluation of new con-trol/protection systems, e.g., traveling wave-based protection methods. In this work, it isdetailed hardware-in-the-loop tests regarding a closed-loop established between a travel-ing wave-based transmission line relay prototype and a power system running in real-timein an FPGA-based platform.


Table 2.1: Summary of the literature review related to the real-time simulation of electricpower systems.

Reference Main Computational Engine Protection HiL test Control HiL testMathur and Wang (1989) DSP − −Wang and Mathur (1989) DSP − −

McLaren et al. (1992) DSP-cluster (RTDS)√

−Kezunovic et al. (1994) DSP/PC − −

Marti and Linares (1994) Supercomputer − −Dufour et al. (1996) Dual-DSP card − −

Dinavahi et al. (2001) PC − −Hollman and Marti (2003) PC-cluster − −

Forsyth et al. (2004) PC-cluster (RTDS) − −Pak et al. (2006) PC-cluster − −

Bélanger et al. (2007) multicore PCs (eMEGASIM) − −Bélanger et al. (2009) multicore PCs (eMEGASIM) − −

Chen and Dinavahi (2009) FPGA − −Matar and Iravani (2010) FPGA − −Matar and Iravani (2011) FPGA − −

Chen and Dinavahi (2013) FPGA-cluster − −Matar and Iravani (2013) FPGA − −

Taveiros et al. (2015) FPGA −√

Razzaghi et al. (2016) FPGA −√

Ould-Bachir et al. (2017) PC/FPGA − −Alvarez-Gonzalez et al. (2017) FPGA −

√

Yang et al. (2018) RTDS/FPGA − −Mao et al. (2018) RTDS/DSPs − −

In this review, two important advantages regarding FPGA-based real-time simulationscan be highlight. The first is related to power system simulation using accurate modelsfor the representation of traveling waves in transmission lines. Using small integrationtime-steps besides allowing a reliable representation of the transients also supports studiesbased on traveling waves, for example, the ones related to fault location in transmissionlines. The second one concerns the development of simulation platforms suitable forperforming relay tests and control devices in an HiL configuration.

Chapter 3

EMTP Models of Power Systems

This chapter introduces the general mathematical formulation regarding the powersystem element models addressed in this work, such as linear lumped elements, switches,transmission lines, voltage sources, etc. The EMTP algorithm is introduced either forunderlying the simulation building process and verifying the possibilities of implementingsections of it in parallel processing architectures. For evaluation purposes, a case studyis implemented in both Matlab, using the theory presented in this chapter, and Simulink.This offline evaluation constitutes an important step towards a posterior efficient real-timeimplementation.

3.1 Linear Lumped Elements ModelingThis section describes the computational models of linear lumped elements such as re-

sistance, inductance, capacitance, and its combination, determined from a chosen numer-ical method. The methodology used in the description of mathematical equations followsthe same basis presented in [Dommel 1969, Dommel 1996, Bayoumi 2009, Chen 2012].

3.1.1 Generic FormulationComputational equations of linear lumped elements can be obtained applying a nu-

meric integration rule to its respective differential equations, for instance, the backwardEuler and trapezoidal rule. As a result, linear lumped elements models such as R (resis-tance), L (inductance), C (capacitance), and its combinations (RL, RC, LC, and RLC) canbe represented by a Norton (or Thevenin) equivalent branch.

For illustration purpose, consider the first-order differential equation

u(t) = Kdy(t)

dt, (3.1)

where K is a constant, y(t) and u(t) are two variables related by (3.1). For instance,suppose y(t) and u(t) are respectively current and voltage of some linear lumped element.(3.1) can be written in the form of

y(t) = y(t−∆t)+1K

∫ t

t−∆tu(t)dt, (3.2)

CHAPTER 3. EMTP MODELS OF POWER SYSTEMS 18

where ∆t is a discrete time-step.A numerical integration rule can then be used to solve (3.2) for each discrete time

interval of ∆t. This operation results in

y(t) = Gu(t)+h(t−∆t), (3.3)

being,

h(t−∆t) = K1 u(t−∆t)+K2 y(t−∆t), (3.4)

where G, k1, and k2 are constant values, and h(t−∆t) is a historical term calculated fromthe previous values of y and u, respectively. Therefore, (3.3) can be represented graph-ically as the same form depicted in Figure 3.1, which is the generic Norton equivalentform of linear lumped elements. Req is theq numeric value representing the equivalentresistance (Req = 1/G). Hence, all linear lumped branches can be represented in a digitalcomputer as current sources and resistances.

1 2

h(t- t)Δ

y(t)

u(t)

Req

+

Figure 3.1: Norton equivalent circuit for linear lumped elements.

3.1.2 Numerical Integration MethodsThe backward Euler and trapezoidal methods are the two integration rules usually

used in EMTP programs. These methods are the ones exploited in this work and, arebriefly described based on Figure 3.2. Suppose u is a continuous function with the time,for instance, a terminal voltage of some linear lumped element. u(t) is the value assumedby u at time t, whereas u(t−∆t) is its previous value.

Figure 3.2: Function u(t).


Consider that the following equation is the one to be solved in the interval delimitedby t−∆t and t, i.e., it is required to solve the integral of u as follows

U(t) =∫ t

t−∆tu(t)dt, (3.5)

where U(t) labels the integral calculation.

Backward Euler Method

Using the backward Euler integration method, then (3.5) is solved as follows

U(t) = u(t)∆t, (3.6)

which can be represented graphically as the rectangle area defined by the boundariesCEBDC in Figure 3.2. Thus, using Backward Euler rule, (3.2) can be written as

y(t) = y(t−∆t)+1K

u(t)∆t, (3.7)

and, can assume the form of

y(t) = Gu(t)+h(t−∆t), (3.8)

which is the same format of (3.3) and, is in the form depicted in Figure 3.1.

Trapezoidal integration method

Using the trapezoidal integration rule, then (3.5) is solved as follows

U(t) =[u(t)+u(t−∆t)]∆t

2, (3.9)

which can be represented graphically as the trapezoidal area defined by the boundariesCABDC in Figure 3.2. Thus, using the trapezoidal rule, (3.2) ca be written as

y(t) = y(t−∆t)+1K[u(t)+u(t−∆t)]∆t

2, (3.10)

and, can assume the form of

y(t) = Gu(t)+h(t−∆t), (3.11)

which is also the same format of ( 3.3) and, is in the form depicted in Figure 3.1.

3.1.3 Choosing The Numerical Integration MethodThe numerical integration rule used to obtain the algebraic equations of the linear

lumped elements must be chosen based on the following requirements:

• numerical stability,


• computational efficiency, and• accuracy.

In terms of computational efficiency, the trapezoidal and the backward Euler methodsrequire values known at the previous time-step. However, the numerical solution foundusing the backward Euler method requires fewer operations to the one obtained from thetrapezoidal rule. In terms of stability, in Bayoumi (2009) is illustrated, according to thelocation of poles and zeros in Z plane (Z transform domain), that both methods satisfy thestability condition,

|Z| ≤ 1, (3.12)

i.e, the poles and zeros are not outside the unit circle defined in plane Z.In terms of accuracy, and for a fixed time-step, the trapezoidal rule is more accurate

than the backward Euler. However, the simulation results can exhibit numerical oscilla-tion when discontinuities occur, e.g., due to switching events. Therefore, it is requiredan additional method for damping those oscillations [Marti and Lin 1989]. On the otherhand, the backward Euler method, inherently, provides the damping of numerical os-cillation. Furthermore, selecting smaller time-steps, backward Euler rule can providethe acceptable accuracy when the results are compared with the ones obtained using thetrapezoidal rule and a larger integration time-step, e.g., for a ratio 1:2. Therefore, thelinear lumped element models used in this work are based on the Backward Euler rule ofintegration.

3.1.4 Resistance (R) ElementFigure 3.3 depicts the lumped resistance element. The variables i12(t) and v12(t) are

current flowing from node 1 to 2, and the voltage between the nodes 1 and 2, respectively,in the specific element, which is a resistor with resistance R in this case.

1 2

i (t)12 R

+ -v (t)12

Figure 3.3: The resistance R element and its discrete-time model.

The discrete-time model of this element is equal to the continuous case. However, thecomputational model is solved at a fixed time-step ∆t. The equation relating current andvoltage is give by

v12(t) = R i12(t). (3.13)


3.1.5 Inductance (L) ElementFigure 3.4 depicts the lumped inductance element L.

1 2

i (t)12

L

+ -v (t)12

Figure 3.4: An inductance L element.

Voltage and current relationship for an inductance L is given as

v12(t) = Ldi12(t)

dt, (3.14)

which can be written in the form of

i12(t) = i12(t−∆t)+1L

∫ t

t−∆tv12(t)dt. (3.15)

Applying the backward Euler rule yields

i12(t) = i12(t−∆t)+∆tL

v12(t), (3.16)

thus, (3.15) can be written as

i12(t) =v12(t)Req,L

+ Ih,L(t−∆t), (3.17)

which assumes the standard form of the Norton equivalent circuit, depicted in Figure 3.5.The term Req,L is a real value representing the equivalent resistance of the computationalinductance model. Req,L is defined as

Req,L =L∆t

, (3.18)

and the history term Ih,L(t−∆t), which is known from the solution at preceding time-step,is computed by

Ih,L(t−∆t) = i12(t−∆t). (3.19)


1 2

Ih,L(t- t)Δ

i (t)12

+ -v (t)12

Req,L

i (t)

Figure 3.5: Norton equivalent circuit of a lumped inductance.

3.1.6 Capacitance (C) elementFigure 3.6 depicts the lumped capacitance element. C is its capacitance value.

1 2

i (t)12

C

+ -v (t)12

Figure 3.6: A capacitance C element.

The voltage and current relationship for a capacitance C element is given by

i12(t) =Cdv12(t)

dt, (3.20)

which can be written in the form of

v12(t) = v12(t−∆t)+1C

∫ t

t−∆ti12(t)dt. (3.21)

Applying the backward Euler method yields

i12(t) =C∆t

v12(t)−C∆t

v12(t−∆t), (3.22)

thus, (3.22) can be written as

i12(t) =v12(t)Req,C

+ Ih,C(t−∆t), (3.23)

which assumes the standard form of the Norton equivalent circuit depicted in Figure 3.7.The term Req,C is a real value representing the equivalent resistance of the computationalcapacitance model. Req,C is defined as


Req,C =∆tC, (3.24)

and the history term Ih,C(t−∆t), which is known from the solution at preceding time-step,is computed by

Ih,C(t−∆t) =−C∆t

v12(t−∆t). (3.25)

1 2

Ih,C(t- t)Δ

i (t)12

+ -v (t)12

Req,C

i (t)

Figure 3.7: Norton equivalent circuit of a lumped capacitance.

3.1.7 Series RL Branch ElementFigure 3.8 depicts the RL branch element.

1 2

i (t)12L

+ -v (t)12

R

Figure 3.8: A series RL branch element.

Assuming an imaginary node with nomenclature k (at RL junction), a following dif-ferential equation can be written

R i12(t)+Ldi12(t)

dt= v12(t), (3.26)

thus, applying the integral operator to both sides of equation (3.26) yields

R∫ t

t−∆ti12(t)dt +L

∫ t

t−∆td(i12(t)) =

∫ t

t−∆tv12(t)dt, (3.27)

and, using the backward Euler method results in

R i12(t)∆t +L(i12(t)− i12(t−∆t)) = v12(t)∆t. (3.28)


Therefore, (3.26) can be written as

i12(t) =v12(t)Req,RL

+ Ih,RL(t−∆t), (3.29)

as a result, (3.29) assumes the standard form of the Norton equivalent circuit depicted inFigure 3.9. The term Req,RL is a real value representing the equivalent resistance of thecomputational RL branch model. Req,RL is defined as

Req,RL = R+L∆t

, (3.30)

and the history term Ih,RL(t−∆t), which is known from the solution at preceding time-step, is computed by

Ih,RL(t−∆t) =L∆t

i12(t−∆t)Req,RL

. (3.31)

1 2

Ih,RC(t- t)Δ

i (t)12

+ -v (t)12

Req,RL

i (t)

Figure 3.9: Norton equivalent circuit of a lumped RL branch.

Depending on the study, and considering short transmission lines, a transmission linecould be represented as an RL branch element.

3.1.8 Series RC Branch ElementsFigure 3.10 depicts the RC branch element. The procedure used to determine the

equivalent Norton circuit of RC branch is similar to the idea adopted for the RL branch.Firstly, a differential equation, as a function of the branch voltage and current variables,is set. Then, a difference equation is established using the backward Euler method and,rearranging the terms a Norton equivalent circuit can be written.

Another way to determine the models of combinations formed by the elements R, Land C is to use and combine the simplest models described earlier, i.e., finding a Nortonequivalent circuit by means the association of resistance, inductance, and capacitancemodels. These steps are underlined on the determination of RC branch computationalmodel.

First, it is highlighted a computational format of the RC branch by simply replacingthe resistance and capacitance illustrated in Figure 3.10 by its computational forms. This


1 2

i (t)12 C

+ -v (t)12

R

Figure 3.10: A series RC branch element.

initial shape of the RC branch model is depicted in Figure 3.11.

1 2

Ih,C(t- t)Δ

i (t)12

+ -v (t)12

Req,C

Ri (t)

Figure 3.11: Discrete circuit of a lumped RL branch.

Assuming a node with nomenclature k (at RL junction), the following equation can bewritten

i12(t) = Ih,C(t−∆t)+vk2(t)Req,C

, (3.32)

which by means the substitution of capacitor model historic current will lead to

i12(t) =−vk2(t−∆t)

Req,C+

vk2(t)Req,C

. (3.33)

Underlying the voltage and current relationship of the lumped resistance, node k canbe eliminated using

vk(t) = v1(t)−R i12(t), (3.34)

thus, substituting (3.34) into (3.33) yields

i12(t) =−(

v1(t−∆t)−R i12(t−∆t)− v2(t−∆t)Req,C

)+

(v1(t)−R i12(t)− v2(t)

Req,C

). (3.35)

Rearranging the terms a Norton equivalent equation is written as

i12(t) =v12(t)Req,RC

− v12(t−∆t)Req,RC

+R

Req,RCi12(t−∆t), (3.36)


which in a standard form yields

i12(t) =v12(t)Req,RC

+ Ih,RC(t−∆t). (3.37)

Hence, for the computational RC model, Req,RC is defined as

Req,RC = Req,C +R =∆tC

+R, (3.38)

and the history term Ih,RC(t−∆t), which is known from the solution at preceding time-step, is computed by

Ih,RC(t−∆t) =−v12(t−∆t)Req,RC

+R

Req,RCi12(t−∆t). (3.39)

The computational model of a linear lumped RC branch is depicted in Figure 3.12.

1 2

Ih,RC(t- t)Δ

i (t)12

+ -v (t)12

Req,RC

i (t)

Figure 3.12: Norton equivalent circuit of a lumped RC branch.

3.1.9 Others Branches CombinationsThe same argument used for elucidating the computational RC branch model can be

applied to all remainder associations formed by the R, L, C and G (conductance) elements.Therefore, the linear lumped elements and its specific combination can be representedcomputationally as a Norton equivalent circuit. Table 3.1 summarizes the lumped elementmodels presented in this work, obtained using the Backward Euler methods.

Table 3.1: Summary of some EMTP lumped models using the backward Euler method.

Element I(t−∆t) ReqResistance − RInductance i12(t−∆t) L/∆t

Capacitance −v12(t−∆t)/Req ∆t/CRL branch i12(t−∆t)(L/∆t)/Req R+L/∆tRC branch −v12(t−∆t)/Req + i12(t−∆t)(R/Req) R+∆t/C


In [Dommel 1996, Chen 2012, Watson and Arrillaga 2003] are present the discretemodels of lumped elements using the trapezoidal integration method, summarized in Ta-ble 3.2.

Table 3.2: Summary of the some EMTP lumped models using trapezoidal method.

Element I(t−∆t) ReqResistance − RInductance v12(t−∆t)/Req + i12(t−∆t) 2L/∆tCapacitance −v12(t−∆t)/Req− i12(t−∆t) ∆t/2CRL branch v12(t−∆t)/Req− i12(t−∆t)(R−2L/∆t)/Req R+2L/∆tRC branch −v12(t−∆t)/Req− i12(t−∆t)(∆t/2C−R)/Req R+∆t/2C

3.2 Switch ModelingFigure 3.13 depicts a switch representation, which can be modeled, ideally, as a time-

controlled switch with resistance equal to zero and infinity representing the closed andopened conditions, respectively. The operation time of these elements are defined byvariables tOp (opening time) and tCl (closing time). In terms of modeling, a switch oper-ation implies a change in the power system configuration, which computationally reflectsin a change of the admittance matrix of the system. For the adopted strategy and currentpurposes, the switch operation is computationally interpreted by the choice of the spe-cific admittance matrix of the system. This approach will be detailed further during theimplementation steps.

1 2

tOp

tCl

Figure 3.13: Switches representation.

In the literature, some works use the switching representation by linear lumped ele-ments. For instance, the switching closed state is represented by an inductance, whereas inthe open state this element is represented by a capacitance [Matar and Iravani 2010, Raz-zaghi et al. 2016]. Thus, the computational model of such an element is represented bya Norton equivalent circuit. Consequently, using this approach, the power system admit-tance matrix is kept fixed. This possibility is related to the selection of inductance andcapacitance parameters for the switches, which is chosen to allow the use of a fixed resis-tance for its computational model. [Razzaghi et al. 2014] proposes the optimal assessmentof these parameters aiming a switch representation closed to the ideal case.


In this work switches represent circuit breakers and also, they are part of a fault cir-cuit. The switching operation of circuit breakers (CBs) is determined by a relay or amanual command, whereas operation time used to applying short-circuits is set by a timeparameter or a manual command. Implementation details will be covered in the followingchapters.

3.3 Voltage SourcesA voltage source can be represented, ideally, either from a digital sinusoidal func-

tion implemented in the FPGA or by storing a cycle of it in a fixed memory buffer andaccessing the addresses at each simulation time-step. As will be described further, anactual voltage source is used in this work to provide a sinusoidal function as input to thesimulation.

Machines models, consequently, its dynamic studies are not covered at this moment.

3.4 Graphic IllustrationFor illustration purposes, Figure 3.14 depicts a single-phase system containing the ele-

ments just introduced. This network is composed of two Thevenin equivalents, which arerepresented by voltage sources and lumped inductance (S1−L1, S2−L2), three switches(SW ), which are representing two circuit breakers and a short-circuit switch, and two RLbranches, which are representing a short transmission line.

S1 S2L1 L1R 1L R 2L

S 1W S 2WS 3W

Figure 3.14: Single-phase system.

A computational outlook of the network shown in Figure 3.14 is achieved simplyreplacing each element by its respective computational model. Firstly, the voltage sourcecan be combined with the inductance computational model to form a Norton equivalentcircuit. Figure 3.15 depicts these steps.

Figure 3.16 depicts the computational form of the power system illustrated in Fig-ure 3.14, which is obtained replacing each component by its discrete model. ReqL1,ReqL2, ReqRL1, and ReqRL2 are the equivalent resistance of the inductance and resistance-inductance element models.


Figure 3.15: Combination of the S and L element into a single Norton equivalent circuit.

ReqRL1

I (t- t)RL1 Δ

ReqRL1 ReqRL2

I (t- t)RL2 Δ

ReqL1 ReqL2

I (t- t)S1L1

Δ I (t- t)S2L2Δ

Figure 3.16: Computational view of the single-phase system.

3.5 Transmission LinesTransmission lines are power system components in charge of electric energy trans-

portation from the generation to distribution systems, thus being a fundamental element ofthe power transmission system. These elements vary in length, according to the distancebetween source and load, from decades to hundreds of km.

Figure 3.17 illustrates a transmission system section. This arrangement is comprisedof overhead grounding wires, insulators, towers, and transmission lines. When a dis-turbance hits a transmission system traveling waves (voltage and current surges) propa-gate through the transmission line structure until be amortized by the line resistance andground losses after successive reflections at discontinuity points (e.g., at the line terminalsand fault location) [Araújo and Neves 2005].

Traveling wave-based transmission-line relays operate based on detecting the arrivaltimes of wavefronts at the transmission line terminals. Hence, an essential demand duringevaluation steps of this type of protection (simulation stage) is to use models allowing thecorrect reproduction of traveling waves in transmission lines.

Figure 3.18 depicts the Lattice diagram illustrating the traveling waves propagationin a transmission line right after the occurrence of an internal fault at the time tF . kF/ fs,ki/ fs, and k j/ fs concerns the fault instant, the arrival time of the first wavefront at bus i,and the arrival time of the first wavefront at bus j, from the point of view a relay operatingat a sampling frequency fS. i.e., in the discrete time-domain [Costa et al. 2017].


Figure 3.17: Transmission lines.

Internal fault

Time (s)Time (s)

t

k /f

Traveling waves F

Fj S

k /fFi S

tFTraveling waves

Wal

avefrontarriv time

k /fF Sk /fF S

Discrete time

Bus i Bus j

Figure 3.18: Propagation of traveling waves in transmission lines. Adapted from [Costaet al. 2017].

In the modeling context, the representation of phenomena taking place transmissionline depends on the selected line model. This choice concerns the type of study re-quired. Usually, the π model is used for steady-state analysis (e.g., load flow), whereasthe distributed-parameter transmission line models are used to perform studies which takethe propagation phenomena into account, which ends up an accurate representation of thetransient state (e.g., EMT studies).


Bergeron model is the lossy distributed parameter transmission line model used inthis work [Dommel 1969]. This model is suitable for validating two-terminal travelingwave-based fault location and protection methods that use aerial mode waves, i.e., meth-ods which do not require the use of zero-component modal waves or wave reflections.Single-terminal methods generally require the use of modal components and wave reflec-tions. For these, the frequency-dependent model would be the most appropriate for thetransmission line representation. The terminology lossy regards the inclusion of lumpedresistive losses into the original Bergeron model. Hence, the remainder of this sectionintroduces the mathematics basis regarding Bergeron model. The general equations de-scribing the transmission lines model follow the same basis presented in [Araújo andNeves 2005].

3.5.1 Mathematical FormulationFigure 3.19 depicts a single-phase transmission line of length d. Consider x being a

real variable denoting a finite-length axis with limits zero (at bus 1) and d (at bus 2) and,the line being a distributed parameters transmission line. v1, v2, i12 and i21 are voltagesand currents at the line terminals.

Figure 3.19: Transmission line illustration.

The start point for this analysis is the presentation of two second-order differentialequations in the frequency domain relating voltages and currents with the transmissionlines parameters obtained from Telegrapher’s equations. Therefore, in the Fourier domain,the following equations can be written

d2V (x,ω)dx2 = z(ω)y(ω)V (x,ω), (3.40)

d2I(x,ω)dx2 = y(ω)z(ω)I(x,ω), (3.41)

where z(ω) represents the transmission line series elements, whereas y(ω) states the shuntparameters. ω refers the frequency domain. z(ω) and y(ω) are calculated by means of

z(ω) = r+ jωl, (3.42)

and,y(ω) = g+ jωc, (3.43)

where r, l, g, and c are the resistance, inductance, conductance, and capacitance per unitof length, respectively.


The solution of (3.40) and (3.41) are in the form of

V (x,ω) = A1(ω)e−γ(ω)x +A2(ω)eγ(ω)x, (3.44)

and,I(x,ω) = Yc(ω)[A1(ω)e−γ(ω)x−A2(ω)eγ(ω)x], (3.45)

where A1(ω) and A2(ω) are frequency-dependent functions. Yc(ω) and γ(ω) are the char-acteristic admittance and the propagation function. These terms are defined as

Yc(ω) = Z−1c (ω) =

[√y(ω)z(ω)

]−1y(ω), (3.46)

and,

γ(ω) =√

z(w)y(w) = α(ω)+ jβ(ω), (3.47)

being, Zc(ω), α(ω) and β(ω) the characteristic impedance, attenuation factor, and phaseconstant, respectively.

To relate the line voltage and current in the frequency domain some mathematicaloperations must be taken into account. Adding and subtracting (3.44) and (3.45) yield

V (x,ω)+Zc(ω)I(x,ω) = 2A1(ω)e−γ(ω)x, (3.48)

and,V (x,ω)−Zc(ω)I(x,ω) = 2A2(ω)eγ(ω)x. (3.49)

In addition, line terminal conditions for x = 0 and x = d can be set (Figure 3.19). Forx = 0,

V (0,ω) =V1(ω); I(0,ω) = I12(ω), (3.50)

and x = d,

V (d,ω) =V2(ω); I(d,ω) =−I21(ω), (3.51)

as a result, a set of equations can be defined based on (3.48) and (3.49), which are, forx = 0,

V1(ω)+Zc(ω)I12(ω) = 2A1(ω), (3.52)

V1(ω)−Zc(ω)I12(ω) = 2A2(ω), (3.53)

and x = d,

V2(ω)−Zc(ω)I21(ω) = 2A1(ω)e−γ(ω)d, (3.54)

V2(ω)+Zc(ω)I21(ω) = 2A1(ω)eγ(ω)d. (3.55)


Functions represented by the terms of (3.52) and (3.55) are referred in the literature asthe forward traveling wave functions, whereas (3.53) and (3.54) represents the backwardtraveling wave functions [Marti 1982, Wang and Mathur 1989].

Forward traveling wave functions are given by

F1(ω) =V1(ω)+Zc(ω)I12(ω),

F2(ω) =V2(ω)+Zc(ω)I21(ω),

and backward traveling waves functions are given by

B1(ω) =V1(ω)−Zc(ω)I12(ω),

B2(ω) =V2(ω)−Zc(ω)I21(ω).

Combining ( 3.52) with ( 3.54), and ( 3.53) with ( 3.55) yields

V1(ω)−Zc(ω)I12(ω) = [V2(ω)+Zc(ω)I21(ω)]e−γ(ω)d (3.56)

and,V2(ω)−Zc(ω)I21(ω) = [V1(ω)+Zc(ω)I12(ω)]e−γ(ω)d (3.57)

The time-domain solution regarding the transmission line model is obtained from(3.56) and (3.57).

3.5.2 Solution for a Lossless LineIn a lossless line the parameter z(ω) = jωl and y(ω) = jωc. Consequently, Zc(ω) is a

real number and, γc(ω) is a pure imaginary. Taking these into account, ( 3.56) and ( 3.56)can be rewritten as

I12(ω) = YcV1(ω)− [YcV2(ω)+ I21(ω)]e− jω√

lcd, (3.58)

andI21(ω) = YcV2(ω)+ [YcV1(ω)+ I12(ω)]e− jω

√lcd. (3.59)

Using the time shifting property of Fourier transformation, these equations can bewritten in the time domain as

i12(t) = Ycv1(t)− [Ycv2(t− τ)+ i21(t− τ)], (3.60)

andI21(t) = Ycv2(t)+ [Ycv1(t− τ)+ i12(t− τ)], (3.61)

where τ = (√

lc)d is the traveling wave propagation time.In addition, these equations can be written in the form of

i12(t) = Ycv1(t)− I1(t− τ), (3.62)


andi21(t) = Ycv2(t)− I2(t− τ), (3.63)

being I1(t− τ) and I2(t− τ) history terms of current calculated at (t− τ), and determinedby means of

I1(t− τ) = Ycv2(t− τ)+ i21(t− τ), (3.64)

and,I2(t− τ) = Ycv1(t− τ)+ i12(t− τ). (3.65)

As a result, equations (3.62) and ( 3.63) suggest that a transmission line can be mod-eled by two Norton equivalent circuits. Indeed, using the Bergeron model a transmis-sion line can be represented as two Norton equivalent circuits. Figure 3.20 depicts thecomputational representation of a transmission line. Zeq is the characteristic equiva-lent impedance. I1(t − τ) and I2(t − τ) correspond to the sending-end (terminal 1) andreceiving-end (terminal 2) backward traveling wave functions. τ is the traveling wavepropagation time.

i (t)12i (t)21

ZeqZeq

1 2

Figure 3.20: Computational transmission line model.

3.5.3 Lossy Transmission Line ModelAs previously pointed out, the Bergeron model does not take into account the effect

of losses distributed along the transmission line. However, as verified in [Dommel 1969],acceptable results are achieved for the lossless model combined with lumped resistances.Figure 3.21 depicts a case related to the combination of two lossless line sections with 3lumped resistances. The total resistance R, which represents the transmission line resistivelosses, is placed at the beginning, middle, and end of the line, respectively.

Figure 3.21: Lossy transmission line approximation.


The mathematics used for arranging the equations into a Norton equivalent circuitsis not presented in this text. However, it is described in [Araújo and Neves 2005]. Thetime-domain model used to represent the lossy transmission is described by the followingset of equations

i12(t) = Yev1(t)− I1(t− τ), (3.66)

and,i21(t) = Yv2(t)− I2(t− τ), (3.67)

where I1(t−τ) and I2(t−τ) history terms of current calculated at (t−τ), and determinedby means of

I1(t− τ) =1+h

2[Yev2(t− τ)+ i21(t− τ)]+

1−h2

[Yev1(t− τ)+ i12(t− τ)] (3.68)

and,

I2(t− τ) =1+h

2[Yev1(t− τ)+ i12(t− τ)]+

1−h2

[Yev2(t− τ)+ i21(t− τ)], (3.69)

where Ye and h are the characteristic equivalent admittance and a constant parameter,respectively. Ye and h are calculated as follows

Ye =1

Zc +R4, (3.70)

h =Zc− R

4

Zc +R4, (3.71)

where R is the total lumped resistance and Zc the transmission line characteristic impedance.Hence, the lossy transmission line model also assumes the form depicted in Figure 3.20,thereby, the transmission line can be represented computationally by two Norton equiva-lent circuits.

The MATLAB documentation [Mathworks n.d.] presents a recursive form of (3.68)and (3.69) which are defined as

I1H(t) =1+h

2[(1+h)Yev2(t−τ)−hI2H(t−τ)]+

1−h2

[(1+h)Yev1(t−τ)−hI1H(t−τ)],

(3.72)and

I2H(t) =1+h

2[(1+h)Yev1(t−τ)−hI1H(t−τ)]+

1−h2

[(1+h)Yev2(t−τ)−hI2H(t−τ)],

(3.73)where I1H(t) = I1(t−τ) and I2H(t) = I2(t−τ). Thus, ( 3.66) and ( 3.67) can be written inthe form of


i12(t) = Yev1(t)− I1H(t), (3.74)

andi21(t) = Yv2(t)− I2H(t), (3.75)

which is the standard form of the Norton equivalent circuit as depicted in Figure 3.20.For a three-phase transmission line, a transformation operation must be used to decou-

ple the system into three separate systems [Dommel 1996]. For instance, Clarke’s trans-formation can be used to calculate the power system (with transposition) for the aerial(α, β) and ground (0) modes, i.e, the transmission line is computed in modal-domain andinterfaced with the power system by means of a transformation unit. Clarke’s transforma-tion matrix is in the form of

T =

1√

2 01 −1√

2

√3√2

1 −1√2−√

3√2

. (3.76)

Figure 3.22 depicts the interface of a three-phase transmission line module with theremainder power system model. A transformation operation must be taken into accountto simplify the transmission line model solution. Each mode (0, α and β) is solved basedon the aforementioned equations.

Bus 1 Bus 2

modalv (t)a,1

phase

modal

phase

v (t)b,1

v (t)c,1

v (t)a,2

v (t)b,2

v (t)c,2

i (t)a,12

i (t)b,12

i (t)c,12

i (t)a,21

i (t)b,21

i (t)c,21v (t),1

v (t),1

v (t)0,1

α

β

v (t)0,2

v (t),2α

v (t),2β

i (t)0,12

i (t),12

i (t),12

α

β

i (t)0,21

i (t),21

i (t),21

α

β

Phasedomain

Modaldomain

Phasedomain

Figure 3.22: Phase-modal transformation operation.

3.6 Network SolutionThe network solution is a technique based on nodal analysis that can be used for

determining the unknown voltages at the buses of a power system. For a given topologyand, representing each power system element by its computational form, an admittancematrix and also a node current injection vector can be defined. Thus, the network solutionequations are used to find the unknown voltages at specific nodes.

For a power system with n nodes, the nodal equation is in the form of

i(t) = Y v(t), (3.77)


where v(t), i(t) and Y , are the nx1 vector of nodal voltages, the nx1 vector of currentsources and, the nxn admittance matrix. (3.77) can be written as[

iUiK

]=

[YUU YUKYKU YKK

][vUvK

], (3.78)

where U referrers unknown voltages nodes, whereas K referrers known voltages nodes.Thus, a solution for unknown voltages are

VU = Y−1UU(IU −YUKVK), (3.79)

where IU is the current sources of unknown voltages.

3.7 EMTP algorithmTaking into account the presented models, which are useful for modeling power sys-

tems comprised of switches, transmission lines, ideal voltage sources, and lumped ele-ments, the next step lies in understanding the EMTP program structure, i.e., to provide adescription regarding the simulation building process.

Figure 3.23 depicts a simplified diagram illustrating an EMTP-type algorithm used fortransients simulation. This schematic is split up into two parts. The first one concerns thestages of variable initialization and information preprocessing to be used in the simulationstages. The second part concerns the properly simulations loop.

In the pre-simulation stage (Figure 3.23) it is set the power system parameters, aswell as the simulation ones (e.g., time-step, simulation time, fault conditions, etc.). Inaddition, the system variables (e.g., currents and voltages) are initialized manually orusing a phasor solution (e.g., a steady-state solution provided by a load flow program).Norton equivalent impedances, as well as the history current sources coefficients, aredetermined. The changes of power system configuration, which is based on switchingstates, are considered by building the corresponding admittance matrices.

In the simulation stage (Figure 3.23) all the history current sources of power systemcomputational models are updated using its corresponding equations and initial variablesstates. Based on switching states node current injection vector is updated as well as itis selected the corresponding admittance matrix. Then, the equation concerning networksolution is calculated to determine the unknown voltages. The loop runs indefinitely orup to the predefined simulation time is attained.

There is an inherent sequencing into the simulation loop. However, operations withineach stage of it can be carried out in parallel. These levels of parallelism can be ex-ploited for EMTP-type programs implemented in parallel processing architectures, espe-cially when it is desired to carry out real-time simulations using time-steps in order ofdecades microseconds or even nanoseconds scale.


Figure 3.23: EMTP-based program.

3.7.1 Parallelism to be exploited in the EMTPThree levels of parallelism can be exploited in the EMTP, which are: a) subsystem/-

model level; a) level of equations; c) level of primitive operations [Matar and Iravani2013]. The implementation of these is a tradeoff between the available hardware re-sources and the desired integration time-step. The comments that will be presented areapplied to FPGA-based hardware platforms.

Subsystems level

Parallelism at the component level is possible due to the existing independence be-tween the power system component models. For instance, equations for calculating his-torical current sources of the lumped elements as well as those of the transmission linesis related to information (voltage and current) computed in previous time steps and storedin memory. Therefore, each component may have its own calculating unit. In addition,calculation units related to the same component type could be implemented in parallel.Moreover, the transmission line model allows the formation of subsystems and its alloca-tion in different hardware devices.


Equations level

Parallelism at the level of the equations can be exploited within a calculation unit ofthe power system elements. For instance, the transmission line model is characterizedby the calculation of two historical current sources that use voltage and current infor-mation already calculated in previous time steps and stored in memories, thereby, thesetwo equations can be calculated in parallel. In addition, considering a three-phase trans-mission line, the equations for the modal components (0, α and β) can be computed inparallel. Moreover, the three-phase model of lumped components can adopt levels of par-allelism by transforming the matrix-vector operation into a sum of product (SOP). Thissame rationale can be adopted in the network solution.

Primitive operations level

Parallelism at the level of primitive operations can be exploited by implementing basicmathematical operations in parallel. For example, performing an optimized SOP.

3.8 Simulation of a Single-phase Transmission SystemThe implementation and simulation of a single-phase transmission system, which is

used as a case study, are covered in the remaining of this section with a purpose to sum-marize the general idea regarding EMT simulation of power systems. An EMTP-typeprogram structured using the schematic depicted in Figure 3.23 is implemented in Mat-lab. The simulation results are compared with the ones obtained using the Simulink powersystem toolbox.

3.8.1 Single-phase Transmission SystemFigure 3.24 depicts the transmission system used as a case study. This power sys-

tem is comprised of two voltage sources, two lumped RL elements, two circuit breakers(CBs), a fault branch, and a transmission line with 400 km of length. The voltage sourcecomponents are represented by sinusoidal functions which values related to one cycle ofit are stored to and retrieved from two buffers.

The transmission line is represented by two smaller line segments to allow varyingthe fault point since the Bergeron Model is terminal. Thus, a short-circuit can be appliedat the node formed from the connection of those sections (Figure 3.24). The change offault point is able by setting the fault distance and the transmission line length. Lengthof the first line section is the same value used for the fault distance. The second linesection length is calculated from the difference between line length and fault distance.The current and potential transformers, as well as the relays, are all ideal elements. Theprotection system is covered afterward.


1

Circuit reakerb s

Transmission inel s

Switch

Fault esistancer

Relay Relay

21 11 2 2 2 21

1 2

RL branches

Sources

Figure 3.24: Single-phase transmission system.

Table 3.3 summarizes the parameters to implement the power system used as the casestudy.

Table 3.3: Power System Parameters.

Parameter ValueVoltage source 1 230 ∠0 VVoltage source 2 230 ∠−π/10 V

Resistance of branch 1 2.21 Ω

Inductance of branch 1 0.0443 HResistance of branch 2 2.21 Ω

Inductance of branch 2 0.0443 HTransmission line inductance 0.0021 H/kmTransmission line capacitance 7.9714e-9 F/kmTransmission line resistance 0.113 Ω/km

Transmission line length 400 kmFault instant 2 s

Fault distance (dF ) 200 kmFault angle π/3 rad

Fault resistance 0.1 Ω

As illustrated earlier, a computational outlook of the network shown in Figure 3.24 ispossible simply replacing each element by its respective computational model. Startingfrom that same point, firstly, the voltage source is combined with the inductance compu-tational model to form a Norton equivalent circuit. Figure 3.25 depicts these steps.

Figure 3.26 depicts the computational form of the power system illustrated in Figure3.24, which is obtained replacing each component by its discrete model. VS, LEM, TLM,SW, and FCM stand for the voltage sources elements, lumped element model, transmis-sion line model, switch element, and fault circuit model.


ReqRL

ΔvS(t)

ReqRLI (t- t)S LR Δ

I ( -RL t t)

ZRL

vS(t)

Figure 3.25: Single-phase transmission system.

The transmission line model (Figure 3.26) allows the original system to be split upinto three separate subsystems. Therefore, it enhances the possibility of solving networksolution in parallel using the suitable hardware resource. A common strategy used bycommercial simulators to simulate large power systems is to take advantage of modelssuch as the transmission line ones to allocate smaller parts of the original power systeminto parallel computing modules.

TLM

FCM

S ystemubs

VS + LEM

SW SW

S ystemubs S ystemubs

Figure 3.26: Computational form of the single-phase transmission system.

Table 3.4 summarizes the computational model parameters achieved when using theelements parameters aforementioned, time step (∆t) of 20 µs, and fault distance (dF ) 200km.

Table 3.4: Parameters of the computational model (∆t = 20µs and dF = 200 km).

Parameter Valueconductance of the VS1+LEM1 model 4.5204e-04 Ω−1

conductance of the VS2+LEM2 model 4.5204e-04 Ω−1

conductance of the TLM1 model 0.001927 Ω−1

conductance of the TLM2 model 0.001927Ω−1

conductance of the FCM model 10 Ω−1


The power system implementation follows the same structure depicted in Figure 3.23.Comments postulated for each stage fit exactly for this study case. As shown in Figure3.26, the modeled power system is split up into smaller subsystems, thus, the networksolution is built for each subsystem. Switching states define the current sources injectedat each node as well as the selection of corresponding admittances matrices. Switchingtimes are taken into account from the fault instant and circuit-breakers operation instantparameters. In subsequent chapters, it is presented a case example in which a protectionsystem can also commands the circuit breaker operation.

3.8.2 Offline Simulation ResultsA time-step of 20 µs is used for the system simulation and building the models. At

sample related to the time of 2 s, a short-circuit is applied at the distance 100 km fromcircuit-breaker 1.

Figure3.27 depicts a comparison between current waveforms obtained using the pro-gram implemented in Matlab and those obtained using Simulink. Figure 3.27-a) depictsthe measurements from the relay 1, meanwhile 3.27-b) illustrates the measurements fromthe relay 2. Figures 3.28 depicts those same comparisons, however with a higher level ofdetails.

Figure 3.27: Comparing results obtained from the real-time simulator, matlab program-ming environment and Simulink. a) current at CB1. b) current at CB2.



In the same way, Figure 3.29 depicts a comparison between voltages waveforms ob-tained using the program implemented in Matlab and those obtained using Simulink. Fig-ure 3.29-a) depicts the measurements from the relay 1, meanwhile 3.29-b) illustrates themeasurements from the relay 2. Figure 3.30 depicts those same comparisons, howeverwith a higher level of details.

The simulation results illustrated in Figures 3.27, 3.28, 3.29 and 3.30 allow conclud-ing that the implemented algorithm using Matlab performs the required calculations forEMTs simulation of power systems since current and voltage waveforms, both in steady-state and in the transient-state, are overlapped with ones obtained from Simulink. There-fore, after this evaluation step, the next one is to implement this same algorithm using animplementation methodology and an FPGA-based hardware device aiming to carry outreal-time simulation of power systems.

3.9 SummaryThis chapter presented the models of some electrical components used for modeling

power systems. Moreover, the general structure of an EMTP-type program was intro-duced. For the sake of illustration purposes, a single-phase transmission system was im-plemented and simulated using the theory presented in this Chapter, and the results werein accordance with existing models in the Simulink.

Chapter 4

Digital Relays

One of the applications to be addressed in this work regards the possibility of per-forming a closed-loop interconnection between the real-time simulator and an externalhardware device. Specifically, it is intended to provide a solution to validate traveling-waves based relays prototypes used for transmission lines protection. At this stage, itshould be clear that to achieve such an objective the simulator must have the capability torepresent the traveling waves which take place on transmission lines, i.e., it must carry outreal-time simulations using time-steps preferably less than 50 µs (e.g., in order of units ofµs).

For this reason, in this chapter, it is presented a brief description of a two-terminalprotection method based on traveling waves theory, which is the same used in the real-timevalidation. Simulations carried out using the Simulink environment are then introducedto support the understanding of this type of protection.

At first, before the traveling-wave relay introduction, it is presented a description ofthe conventional relay structure as well as the algorithms embedded in it. Then simulationresults regarding a classical protection method of transmission lines (distance protection)are presented. This initial idea is introduced aiming also to highlight further the simulationplatform usage for validation of conventional protection schemes.

4.1 Power System Under StudySimulations results described in this chapter regards the case study introduced in

Chapter 3, although starting from the point of presenting the relay modules. Firstly, thesimulation results related to the conventional relay units are elucidated in a simplisticperspective. The central description is highlighted in more details later for the traveling-waves-based relays, specifically, concerning fault detection and protection methods.

Figure 4.1 depicts the power system used as a case study, now highlighting the pro-tection panorama. This power system is implemented on Simulink as well as a relay fortransmission line protection.

CHAPTER 4. DIGITAL RELAYS 46

Relay Relay

1 2

Figure 4.1: Power system under study.

4.2 Relay StructureFigure 4.2 depicts the structure of a generic digital relay. This component is composed

of internal modules such as the analog scaling module, anti-aliasing filter, stapler circuit,sample and hold circuit, A/D (analog to digital) converter, and the processing unit. It re-ceives analog inputs related to the power system current and voltage measurements, whichare scaled-down by the instrument transformers, and sends as digital output a commandsignal related to the circuit breaker trip.

The analog-scaling module (auxiliary transformers) function is scaling down the volt-age and current waveforms acquired by the instrument transformers to voltage levels ofthe relay components (e.g., A/D converter). Furthermore, this module is used to provideelectric isolation between the relay and the power system. The anti-aliasing block corre-sponds to a low-pass analog filter which is designed to select the desired frequency bandof the input signal and minimize problems related to the aliasing phenomenon that occursin the sampling step [Oppenheim 1999]. The stapler circuit module is designed to set avoltage limit to be applied in the A/D conversion system since an overvoltage surge, forinstance, in the secondary winding of the auxiliary current transformer could damage thatcircuit. These three modules form the relay signal conditioning block.

The A/D conversion module is comprised of, considering a simplistic view, a sam-pling and hold (S/H) circuit and A/D conversion stage. The first one is designed, assuggested by its name, to sample the input analog signal at a specific sampling frequency,keeping it constant during a single time-step interval. The A/D conversion stage is usedto convert the outputs of the S/H circuit in a bit sequence to properly be computed by themicroprocessor.

The digital current/voltage data are, therefore, inputs of the processing unit whichhandle, conventionally, phasor estimation techniques and protection schemes. Neverthe-less, also depending on the application, there are several functions implemented in theprocessing unit such as the ones associated with electric fault location and classification.


Dig

ital Relay

Anti-AliasingFilter

Processing Unit

AnalogInput

DigitalOutput

CCVT/PT

CT

52

Stapler Circuit

Analog Scaling

A/D ConversionModule

Figure 4.2: Relay building blocks.

4.3 Analog ScalingThe Analog Scaling module is comprised of auxiliary transformers (TP and a TC)

in which the main functionality is scaling down the input signal at ratings of the relaycomponents.

Figure 4.3 depicts a diagram of the auxiliary potential transformer within the AnalogScaling module. It receives the voltage signal from the secondary winding of the PT (orCCVT) and sends to the output an adjusted voltage at levels suitable for the relay com-ponents [Perez 2006]. In addition, this equipment provides an isolation function betweenthe relay and the power system as aforementioned. A Metal Oxide Varistor (MOV) isused to protect the data acquisition system against surges.

MOV

VoltageInput

Auxiliary PT

Potenciometer

VoltageOutput

Figure 4.3: Auxiliary potential transformer.


Figure 4.4 depicts a diagram of the auxiliary current transformer enclosed in the Ana-log Scaling module. The input signal of this component is the current waveform availableby the secondary winding of the CT, whereas the output is a voltage signal, which is re-lated directly with the current flowing its secondary winding. Similarly, this componentprovides an isolation role between the power system and the relay components.

MOV

Auxiliary CT

CurrentInput

VoltageOutput

Figure 4.4: Auxiliary current transformer.

4.4 Anti-Aliasing FilterIn normal operation conditions, the power system voltage and current waveforms,

which are input variables of the digital relays, are composed in frequency by a dominantfundamental component as well as, consonant the measuring location, by limited/con-trolled levels of harmonic components. However, an analysis of the voltage and currentoscillography for a disturbance occurrence, e.g., a manual switching operation or a re-strike event, short-circuits, open-phase condition, lightning strikes, etc., reveals that thetransient state contains components in a wide frequency range depending on the typeof event and the physical system response itself. For protection systems context, usefulinformation to be used depends on the relay design.

The tasks executing in relays are designed to attend its general protection purposes,e.g., the amount of required filtering depends on the relay nature [Perez 2006]. Tradi-tional methods such as those related to overcurrent, distance, differential, directional, andovervoltage protection, are based on phasor measurements. For instance, distance pro-tection uses voltage and current information of the fundamental component (module andphase), whereas the transformer differential protection uses additionally the second andfourth components to define energization events and the fifth for the overexcitation eventand, thereby, distinguish them of a short-circuit.

In this sense, the anti-aliasing module illustrated in Figure 4.2 corresponds to a low-pass filter. This module is the one in charge to limit the bandwidth of the relay inputsignals (voltages and currents). Figure 4.5 depicts generically the frequency response ofa low-pass filter and the requirements used in its design. The variables δp1, δp2, and δsconcerns the ripples allowed in the passband and stopband, respectively. The parametersωp and ωs are the angular frequency delimiting the boundaries of passband and stopband.The math formulation regarding the implementation of such a module (analog or digital


design) is not within the scope of this work. This one can be found in the references[Oppenheim 1999, Perez 2006].

1+δp1

1-δp2

δs

0 ωp ωs ω

Stopband

H(s)

Passband Transition

Figure 4.5: Low-pass filter design.

Figure 4.6 depicts the Bode diagram regarding a 2-order Butterworth filter design,respectively it depicts the magnitude (Figure 4.6-a) and phase (Figure 4.6-b) response.Additionally, Figure 4.7 depicts the current signal caught at the filter input and output. IAis the phase current at the relay input terminal. IA,F is that same variable monitored atthe filter output. The purpose of these illustrations is only to highlight the filtering oper-ation module for conventional phasor-based protection (e.g., transmission lines distanceprotection) in which acts by selecting the fundamental component or eventual low-orderharmonics.

Mag

.(d

B)

(deg

)

ϕ

0

-50

-150

-200

0

-90

-180

-27010

110

210

310

410

5

ω (rad/s)

a)

b)

H(s)

H(s)

Figure 4.6: Bode diagram presenting magnitude and phase response of a Butterworthfilter: a) depicts the filter magnitude response; b) illustrates the filter phase response.


-1

0

1

2IA

IA,F

Time (s)

1.94 1.96 1.98 2 2.02 2.04 2.06 2.08

Curr

ent

(kA

)

Figure 4.7: Current monitored at filter input and output.

4.5 A/D Conversion ModuleThe sampling frequency and resolution of the A/D conversion (ADC) module are

essential parameters in a protection system design. According to Nyquist theorem, thesampling frequency is directly related to the frequency components representation of thesampled signal. Therefore, in relay design, this parameter concerns the type of protectionused. For instance, phasor-based (conventional) protection relays operate at a samplingfrequency close to 1 kHz, since useful information for these schemes regards the funda-mental component and low-order harmonics. On the other hand, protection relays basedon traveling waves must operate preferentially with sampling frequencies in the order ofMHz. The ADC resolution, or rather, the number of bits used for mapping the input signallevels enable the accurate representation of it.

The sample and hold circuit is designed to allow the reproduction of each cycle of theinput signal at a specified number of levels. Therefore, the sampling frequency parameteris directly related to the number of possible levels per cycle. To illustrate this, Figure4.8 depicts a simulation result highlighting a comparison between a current waveformat the relay input (Figure 4.1) and this variable monitored in the output of its respectivesubsampling block (Figure 4.2), which for this example emulates the sampling and holdcircuit operation. The current signal (Figure 4.8) is sub-sampled at a frequency of 1 kHz,i.e., 20 samples per cycle of the 50 Hz fundamental component. IA is the phase current atthe relay input terminal. IA,S is that same variable sub-sampled for achieving 20 samplesper current cycle.

Right after the sampling and holding stage, the sampled signal is quantized and theneach sample of it is encoded in a bit sequence. As already mentioned, the number of bitsused for representing the amplitude levels of the signal is a parameter that qualifies theconverter resolution. This step is detailed later in the protection system implementationusing a DSP-based hardware device.


1.98 2.02 2.06

Time (s)

-2.5

-1.25

0

1.25

2.5C

urr

ent

(A)

IA

IA,S

Figure 4.8: Illustration of the sampling and hold process regarding the A/D conversionmodule.

4.6 Processing UnitThe processing module (Figure 4.2) can be qualified as the protection relay brain.

Voltages and current measurements from the power system are processed, qualified andinterpreted based on the algorithms implemented in such unit. The types of algorithmsimplemented in a processing unit are related to protection system nature. For instance, atransmission line protection system based on phasor information of currents and voltages(e.g., distance relay) must handle phasor estimation techniques and respective protectionlogical functions. In the same way, a transmission line relay designed based on travelingwaves theory needs the implementation of methods to determine the arrival time of thetraveling waves at the line terminals as well as the respective logical functions of protec-tion.

The remainder of this section is devoted to the presentation of some of the algorithmsimplemented in the relay processing module. It is presented firstly the algorithms used fora classical transmission line protection, which is the distance protection. Then fundamentsregarding a traveling-wave based protection for transmission lines are described.

4.6.1 Phasor-Based Protection of Transmission LinesPhasor-based protection of transmission lines operates based on information obtained

from current and/or voltage phasors. For instance, the distance protection uses moduleand phase information of current and voltage to determine the relative impedance param-eter. This one is then compared to a characteristic region plotted based on the operatingcharacteristics of the system and design parameters (e.g., line impedance, fault resistance,protected zone, etc.). Thus, by locating this impedance in the reference region (Z plane)and if necessary adding another auxiliary protection logic (for example, overcurrent), therelay update the trip signal state. Overcurrent protection is another example of phasor-based protection, in which case the base information used on protection logic is in thephasor module of the current.


In this context, the phasor estimation technique algorithm, based on discrete Fouriertransform, and a distance protection method are presented for now, which are algorithmsimplemented in this first stage of simulation (offline) and later in real-time.

Phasor Estimation

Fourier-based phasor estimator is a mathematical tool that can be used to extract thefundamental component of a measured signal from a considered power system. Thistechnique makes use of the discrete Fourier transform (DFT) to track back the funda-mental component of an input signal. The detailed theory describing phasor estima-tion techniques for power system applications are found in the reference [Horowitz andPhadke 2008].

The real and imaginary component of the DFT tuned at the fundamental frequencyare computed as follows

Xre =2N

N−1

∑k=0

x(k)cos(

2π

Nk), (4.1)

Xim =2N

N−1

∑k=0

x(k)sin(

2π

Nk), (4.2)

where Xre, Xim, x(k) and N are the real and imaginary component of the DFT, an inputsignal value at the sampling k, and the sliding window length, respectively. So, moduleand angle parameters of the phasor are estimated as follows

|X |=√

X2re +X2

im, (4.3)

φ(X) = arctan(

Xim

Xre

). (4.4)

Figures 4.9 and 4.10 depicts simulation results regarding module and phase estima-tion of the fundamental component of current using the discrete Fourier transform as themathematical tool. This case concerns the results of the phasor estimation unit for a faulttaking place the transmission line (Figure 4.1) at fault instant 2 s. As illustrated in Figure4.9, there is a delay related to the phasor estimation convergence after the fault occurrence,which is mainly due to the one-cycle window required by the Fourier estimator. Consider-ing that the phasor-based protection algorithms use this information or associated ones asinput data for the protective functions, that delay impacts the protection system velocity.

Distance protection

The protection algorithm acts processing the information, usually passed by the phasorestimator, and making a decision based on its implemented logic.


Figure 4.9: Module estimation of the current phasor (|IA,S|) measured by relay 1 (Figure4.1) of the power system under study.

Figure 4.10: Phase estimation of the current phasor (φ(IA,S)) measured by relay 1 (Figure4.1) of the power system under study.

Distance protection is one of the relay classic units commonly applied to providetransmission lines protection. The operation mode of this unit is based on the type ofused region to define the protected areas. The admittance or moh relay is the one con-sidered in this work to provide the transmission line protection. This protection schemeuses the voltage and current samples estimated by the phasor estimator block to determinethe system impedance (relative impedance). The protection trip is issued if the relativeimpedance falls within the characteristic region. The fundamentals of distance protec-tion are presented in [Kasztenny and Finney 2008], and here just a brief explanation isaccomplished.

The relay operating zone is defined here by means a magnitude comparator usingSO = IZN and SR = IZN−2V , which are the operation and restriction vectors, respectively[Kasztenny and Finney 2008]. Using these vectors, the MOH characteristic is defined asfollows

|ZR|2 +|ZN |2

2+2|ZR|

|ZN |2

cos(θ−ξ)≤ |ZN |2

2

, (4.5)


where ZN is the line impedance, ZR is the relative impedance obtained by measurements,θ is the relative impedance angle; and ξ is the angle between ZN e ZR.

Figures 4.9 depicts a simulation result regarding the relative impedance estimationdetermined using module and phase information from the voltage and current phasors.This case highlights the impedance trajectory from the operational state to fault steady-state. Such a result is related to a fault applied at 200 km from relay 1 (Figure 4.1). Theprotection algorithm checks if the relative impedance falls into the protection zone issuinga trip command when the condition governed by (4.5) turns true. In this illustration, thetrip command is disabled in order to verify, from a simple perspective, the operationconcept of this type of protection.

-100 200 500 800

Real Z( )R

-400

-200

0

200

400

600

Imag

inar

y (

ZR) Z

R

ZN

MHO curve

Figure 4.11: The trajectory followed by the relative impedance (ZR) on the Z plane.

4.6.2 Traveling-Waves-Based RelaySafety, operation velocity, and reliability are essential parameters that qualify the pro-

tection systems. In practice, it is sought for solutions to ensure the correct and fastestoperation of the protection systems in order to reduce the damages in the power system[Costa et al. 2017]. The operation speed of the protection system is related to factorssuch as the relay hardware architecture, complexity associated with protection methods,the time for the circuit breakers operation, delays imposed by the communication channeland, etc.

The methods embedded in the protection relays can impose a significant delay in theoperation time of it. For instance, relays based on phasor estimation have an operatingtime in the order of a few tens of microseconds (around a cycle), which is related to thesize of the time window required for phasors estimation of current and voltage. On theother hand, modern traveling-wave-based protection operates in the order of a few unitsof microseconds. This feature makes these modern protection systems of considerableinterest for the industry due to, in addition to their simplicity, allow reducing damages inthe power system as well as the increase of its stability margin.

In this context, the scientific and industrial communities have made efforts in an at-tempt of developing ultra-fast protection schemes. Traveling-waves-based relays are one


of the modern technologies which have been studied to provide reliable and fast protec-tion for transmission lines [Schweitzer Engineering Laboratories n.d., Costa et al. 2017].These relays designed based on the traveling-wave principles are known as high-speedactuation systems regarding the small-time necessary for its decision making, thus, beingable to clear faults taking place transmission-lines as soon as possible.

Towards to address the proposed application of this work in verifying the traveling-waves-based protections, the remainder of this chapter is devoted to present the funda-mental idea regarding the two-terminal traveling-wave-based transmission-line protectionmethod proposed by Costa et al. (2017).

Two-Terminal Traveling Wave-Based Transmission Line Protection Method [Costaet al. 2017]

When a fault occurs in an overhead transmission line the abrupt change of voltage atthe fault point results in the generation and propagation of voltage pulses, referred to asvoltage traveling-waves, towards the transmission line terminals. After a limited time,the traveling waves of voltage and current generated in the disturbance are damped dueto resistive losses and successive reflections at the discontinuity points (transmission lineterminals and fault point). Furthermore, the voltage and current measurements at thetransmission line terminals can reveal the presence of low and high-frequency transientsdepending on the fault distance. Therefore, fault information such as the type, inceptiontime, location, and direction can be calculated and used to enhance the performance ofrelays.

The protection method of two terminals is developed based on the detection of thearrival time of the first wavefront on both terminals of the transmission line. An algorithmto provide fault detection can make use of high-frequency components to detect the arrivaltime of the first wavefront at local buses.

Figure 4.12 depicts a schematic of the relay operation process. For the sake of illustra-tion, the transmission system used to provide the current and voltage data for the relay isthe same presented in Chapter 3. However, the analysis introduced here can be extendedto a more complete power system as presented in Costa et al. (2017). The transmissionline element of length d is represented by two smaller segments to allow the simulation ofan internal fault far dFi km from the bus i. The protection system is composed of relays,the communication equipment, data synchronization system, switch breakers, TC, TP, etc.As depicted in such a figure, the relay must run an algorithm to detect the arrival time ofthe local wavefront, receive similar parameter from the remote relay, as well as handle aprotection algorithm for the internal fault detection and trip generation. A fault locationmethod can also be implemented to estimate the fault location.


Internal fault

Fj

Trip

Com

munic

atio

nch

annel

Protection algorithm:Internal fault detection

+ trip generation

Signal acquisition

Com

munic

atio

n e

quip

men

t

1

2

3

Signal processing:local wavefront arrival

time detection

Relayi

Fault location4

Protection algorithm:Internal fault detection

+ trip generation

Signal acquisition1

2

3

Signal processing:local wavefront arrival

time detection

Relayj

Fault location4C

om

munic

atio

n e

quip

men

t

Trip

Bus i Bus jProtected line with kmd

dFi d d d= - Fi

Figure 4.12: Relay building blocks.

Figure 4.13 depicts a profile of the Lattice diagram drawn for the fault far d km frombus i which takes place the transmission line at the time instant tF . When such a faultoccurs traveling waves propagate towards the transmission-line terminals. The verticalaxis (Figure 4.13) denotes the discrete nature of the relays, i.e., the samples taken by thosedevices operating at a sampling frequency of fs. kF refers to the fault sample representedin the relays time base, whereas kF/ fs denotes the respective discrete time instant. kFi/ fsis the discrete-time in which the relay, located near bus i, detects the arrival of the firstwavefront. Likewise, the discrete time kF j/ fs refers to the detection of the first wavefrontby the relay located at the remote terminal (bus j).

Internal fault

Time (s)Time (s)

t

k /f

Traveling wavesF

Fj S

k /fFi S

tFTraveling waves

Wal

avefrontarriv time

k /fF Sk /fF S

Discrete time

Busi BusjProtected line with kmd

d d d d= -Fi Fj Fi

Figure 4.13: Lattice diagram illustrating the traveling waves propagation in a transmissionline right after the occurrence of an internal fault at the time tF .


Considering the continuous time domain, the time interval required for a travelingwave to traverse the transmission line portion dFi (Figure 4.13), i.e., the propagation delayof the wave from the fault point to the bus i (τFi), is defined as follows

τFi = tFi− tF , (4.6)

where tFi is the time in which the fault starts at the bus i.The time interval for the traveling wave crosses the transmission line is calculated in

the form of

τ =dv, (4.7)

where d and v are the transmission line length and the traveling wave velocity, respec-tively.

Therefore, internal faults taking place a transmission line can be detected as follows

|tFi− tF j|<dv, (4.8)

whereas for external faults, it yields

|tFi− tF j|=dv, (4.9)

where tF j is the time in which the fault starts at the bus j.In the discrete-time domain, which is the relay time base, the equations used for the

detection of internal and external faults takes the form of

|kFi− kFj |< bd fs/vc, (4.10)

|kFi− kFj |= bd fs/vc, (4.11)

where fs ≤ v/d. bc denotes the floor operation.In equations (4.10) and (4.10) it is necessary the velocity estimation of the traveling

wave, which requires correctness determination of the transmission line parameters, i.e,its estimation can introduce errors to distinguish external and internal faults of the protec-tion zone. Costa et al. (2017) suggests using the speed of the light (c) instead of v (c > v)in order to avoid protection misoperation. Therefore, internal faults are identified if

|kFi− kFj |< bd fs/cc, (4.12)

whereas downstream external faults condition are verified as follows

−bd fs/cc−1≤ kFi− kFj ≤−bd fs/cc, (4.13)

and, for upstream external faults yields

bd fs/cc ≤ kFi− kFj ≤ bd fs/cc+1. (4.14)


A complete description regarding such a protection scheme is presented in [Costaet al. 2017]. Costa et al. (2017) also address the error effects, the definition of protectionzones, uncertainty zones, and unprotected zones, effects of the sampling rate and linelength in the protection zone as well as the effect of the traveling wave velocity estimation.

Briefly, the protected, uncertainty, and unprotected zones regarding the two-terminaltraveling wave-based transmission line method are defined as follows

PZ = PZ(vt) =b fsd√

lcc−1fsd√

lc100%, (4.15)

UZ =UZ(vt) =1

fsd√

lc100%, (4.16)

UPZ =UPZ(vt) =

(1− b fsd

√lcc

fsd√

lc

)100%, (4.17)

where PZ, UZ, and UPZ are the protection, uncertainty, and unprotected zones. vt standsfor the traveling-wave velocity for a lossless transmission line.

Figure 4.14 depicts a general drawn of the protected, uncertainty, and unprotectedzones, which are defined based on equations aforementioned.

Figure 4.14: Protected, uncertainty, and unprotected zones.

The aforementioned highlighted method supposes that the discrete samples regardingthe arrival time of the first wavefronts at the transmission line terminals were determinedusing any detection method. The wavelet transform is a suitable tool that can be used toprovide such information since it allows time and frequency resolution, i.e., using framesof time with a duration of microseconds one can extract characteristics of the signal inreal-time related to a particular frequency range [Costa 2014]. For instance, in this work,the first decomposition scale of RT-SWT (Real-Time Stationary Wavelet Transform) fora 4-coefficients mother wavelet filter of Daubechies family was used to calculate waveletcoefficients whose magnitude quantifies high-frequency information contained in the in-put signal.

The following set of equations are used to compute the scaling and wavelet coefficientsof the RT-SWT for the first level of decomposition.

sx(k) =L−1

∑l=0

hφ(l)x(k+ l−L+1), (4.18)


wx(k) =L−1

∑l=0

hψ(l)x(k+ l−L+1), (4.19)

where sx, wx, hφ, hψ, x are the scale coefficients, wavelet coefficients, filters, and the inputsignal, respectively. The L parameter is related to the filter length and the discrete timeframe considered to perform the calculations.

Figure 4.15 depicts simulation results regarding the operation of a traveling-wave-based relay. IA,R1, wCOEF,R1, and TripR1 are the current, wavelet coefficient and trip signalrelated to relay 1, whereas IA,R2, wCOEF,R2, and TripR2 the current, wavelet coefficientand trip signal related to relay 2. These results are related to a fault far 100 km frombus 1 (Figure 4.1) for a 400 km transmission line, fault angle 60°, fault instant 2 s, faultresistance 0.1 Ω. The simulation is conducted using an integration time-step of 20 µs, thesame time-step used for the traveling wave-based relay. For the sake of illustration, thepresented results are used to illustrate the operation mode of this kind o protection. Thus,the relay trip signals are not issued to open the power system circuit breakers, i.e., thesesystems are in an open-loop configuration. A detailed analysis regarding a traveling wave-based transmission line relay prototype, highlighting its performance, is presented in theChapter of results considering a hardware-in-the-loop setup. Such validation also takesinto account practical issues such as the delays of the communication system, mechanicalswitch breaker operation delay, definition of the protection zones, etc.

In Figures 4.15-a), 4.15-b) and 4.15-c) are illustrated, for relay 1 (Figure 4.1), therelay input signal (line terminal current), the wavelet coefficients calculated using (4.19),and the ideal trip signals (without taking into account the communication delays, timerequired for switch breaker operation, etc.) determined based on the protection equation(4.12). Similar results are depicted in Figures 4.15-d), 4.15-e) and 4.15-f) for relay 2(Figure 4.1). The arrival time of the first wavefront at terminal buses are detected by therelays based on the wavelet coefficient magnitude. The relay operates when it detects thatwavefront, receives the sample information regarding the detection from the remote relayand based on the protection equation. A frame in order of µs is highlighted in Figures4.15-a) and 4.15-d) to emphasize it is necessary few samples of the input signal for thetraveling-wave detection, being thus a factor that contributes for the fast operation of therelay.

Figure 4.16 depicts the same results presented in Figure 4.15, nevertheless consideringa better resolution (zoom in the area highlighted in Figure 4.15).The relay located at thebus i detects a wavefront arrival time before the remote one since the fault is near 100 kmfrom bus 1 and far 300 km from bus 2. However, the relay at bus 1 waits for the sampleinformation coming from relay 2 to update the status of the trip signal.

Figure 4.17 depicts the same results presented in Figure 4.16, nevertheless consider-ing a higher resolution aiming to show the arrival time of the first wavefront at the lineterminals.


-4

-2

0

2

4C

urr

ent

(kA

)

-4

-2

0

2

4

-50

-25

0

25

50

Time (s)

0

1

-50

-25

0

25

50

0

1

1.88 1.94 2.00 2.06 2.12 1.88 1.94 2.00 2.06 2.12

Wav

elet

Co

ef.

Idea

lT

rip

Time (s)

a)

b)

c)

d)

e)

f)

IA,R1

wCOEF,R1

IA,R2

wCOEF,R2

TripR1 TripR2

Figure 4.15: Simulation results regarding the operation of a traveling-wave-based relay:cases a), b), and c) illustrate the current at the relay 1 input, the wavelet coefficient calcu-lated by its detection unit, and the trip signal, determined after the traveling wave detec-tion and according to the protection equation; cases d), e), and f) illustrate those resultsconsidering relay 2.

Two important notes concern the verification of traveling-wave-based transmission-lines relays. The first point regards the need to perform simulations of transmission sys-tems using time-steps on the microsecond scale. Such type of protection is associatedwith a detection method and, as underlined, information of the transient regime associ-ated with high-frequency components can be used to determine the arrival time of travel-ing waves at the transmission line terminals. The second point concerns the necessity of ahigh-sampling frequency by the relays for both the reproduction of the higher frequencycomponents and the protection scheme performance.

4.7 SummaryThis Chapter described the main building blocks of a digital relay. Furthermore, it pro-

vided a brief description concerning the two-terminal traveling wave-based transmissionline protection implemented in DSP, as will be shown in the next chapters.


Figure 4.16: Closer view on the simulation results regarding the operation of a traveling-wave-based relay.


Figure 4.17: Closer view on the simulation results regarding the operation of a traveling-wave-based relay.

Chapter 5

Real-Time Simulator Design

This chapter introduces, initially, the hardware architectures used to implement boththe FPGA-based real-time simulator and the traveling-wave-based transmission line relay.Then, it provides a proper description regarding the implementation steps of the powersystem used as the case study as well as the implementation of both a conventional and atraveling wave-based relay.

5.1 The developed Real-Time Simulator: Physical SetupThe current real-time simulator setup is depicted in Figure 5.1. Such a structure are

composed by the SbRIO-9637 board, the eZdsp 320F28335 controller board, a signalgenerator, a PC and, an oscilloscope. The real-time simulation is carried out in the FPGA-based controller board, whereas the traveling wave-based transmission line relay is carriedout in the DSP-based controller board. The graphical user interface (GUI), developedin the LabVIEW environment, is used to monitor the dynamics of the simulated powersystem as well as to set the simulation parameters. The actual signal generator is usedto provide a sinusoidal waveform for the simulation environment, e.g., to emulate idealvoltage sources.

Figure 5.2 highlights the hardware devices used in the real-time simulator design. Thehardware-in-the-loop real-time simulation is achieved by placing the FPGA-based devicein a closed-loop with DSP-based hardware device. The oscilloscope is programmed todisplay the time windows of the simulation containing the transient information used bythe traveling wave-based relay prototypes.

5.2 Hardware ArchitecturesThe hardware device employed in a digital system design is chosen based on the

desired performance and characteristics for the final designed system (e.g., flexibility,hardware efficiency, scalability, etc.). Usually, such a choice leads to architectures basedon microprocessors, reconfigurable hardware, or application specific integrated circuits(ASICs).

CHAPTER 5. REAL-TIME SIMULATOR DESIGN 64

Figure 5.1: Physical setup of the real-time simulator.

Figure 5.2: Hardware devices used in the real-time simulator design.


The microprocessor-based digital systems are flexible (e.g., software programmable),but with low hardware efficiency. The ASICs leads to higher hardware efficiency but withlower flexibility and high development cost. On the other hand, the digital systems basedon reconfigurable hardware (e.g. FPGAs) fill such a gap being flexible and hardwareefficient systems [Chen 2012]. These characteristics make this hardware a suitable choiceto design a real-time system.

As highlighted in earlier chapters, the goals established for this work point to performreal-time simulations of power systems, using time-steps suitable for the representationof traveling-waves taking place transmission lines due to faults occurrence, for the sakeof validating protection schemes based on traveling waves. Thus, to accomplish thesepurposes it is necessary to make use of hardware architectures with available resourcesallowing to improve calculation velocity and communication latency, as well as modelinga demanded power system size. As presented in Chapter 2, FPGA-based architectures area good suggestion towards the simulation of power system using small time-steps.

The single-board RIO-9637 is the available FPGA-based hardware device used toverify its potential to handle the computations regarding the power system real-time sim-ulations, whereas eZdsp F28335 controller board is the hardware used to implement thetraveling-wave-based transmission line protection.

5.2.1 FPGA ArchitectureFPGAs are semiconductor devices based around a two-dimensional array of config-

urable logic blocks (CLBs) interconnected via a matrix of wires and switches. The CLBdesignation regards the logic units of FPGAs developed by Xilinx. Such blocks containthe main logic resources used to implement the sequential and combinational circuits.The field programmability is obtained based on the programmable switches which allowthe interconnection of several CLBs via wires.

Figure 5.3 depicts the structure of modern FPGAs. Besides the CLBs, FPGAs com-prises many memory blocks and specialized circuits such as DSP blocks. The DSPs sliceshave been added into FPGA structure to enhance the speed and efficiency in digital pro-cessing applications such as to performing multiplication and accumulation operations.

Figure 5.4 depicts the CLB unit of the Artix-7 FPGA, which refers to the FPGAfamily from Xilinx used in this work. Each CLB contains two slices. One of this iscomposed basically by four logic-function generators (or look-up tables), eight storageelements (flip-flops), wide-functions multiplexers, carry logic [XILINX n.d.]. In general,these elements are used by CLB slices to provide logic, arithmetic and ROM functions.Nevertheless, some slices also support additional functions regarding storing data usingdistributed RAM and shifting data with a 32-bit register, both of them implemented basedon LUTs.


CLB Mem. DSPCLB

I/O I/O I/O I/O

I/O

I/O

I/O

I/O

CLB Mem. DSPCLB

CLB Mem. DSPCLB

CLB Mem. DSPCLB

I/O I/O I/O I/O

I/O

I/O

I/O

I/O

Figure 5.3: Illustration of modern FPGAs configuration.

Slice0

X0Y1

Slice0

X0Y1

Slice0

X0Y1

Slice1

X1Y1

Slice0

X0Y1

Slice0

X0Y1

Slice0

X0Y0

Slice1

X1Y0

Slice0

X0Y1

Slice0

X0Y1

Slice0

X2Y1

Slice1

X3Y1

Slice0

X0Y1

Slice0

X0Y1

Slice0

X2Y0

Slice0

X3Y0

CLB CLB

CLB CLB

Cout

Cin Cin Cin Cin

Cout Cout Cout

Cout Cout CoutCout

Figure 5.4: Illustration of modern FPGAs configuration.

The internal structure of FPGAs (Figure 5.3), with specialized circuits and resourcesdistributed in space, allows the programming and execution of algorithms efficiently, i.e.,the mathematical operations regarding decoupled models (either in space or time) can becarried out in parallel. For instance, several modules carrying out the SOP (sum of prod-uct) operation can be implemented and executed separately as well as the SOP structure.Thus, besides the reconfigurability, the parallel nature of FPGAs enhance the use of suchdevices for real-time applications.


5.2.2 Single Board RIO-9637 (sbRIO-9637)The single-board RIO-9637 is a hardware device based on RIO technology. The termi-

nology RIO refers to an architecture which integrates a floating-point processor runninga real-time operating system, an FPGA, and modular I/O (inputs and outputs) in a printedcircuit board (PCB). Figure 5.5 depicts the RIO boards architecture.

AIO

AIO

AIO

AIO

Processor FPGA

RIO Architecture

Figure 5.5: RIO technology.

The SbRIO-9637 is a controller board comprised of a 667 MHz CPU, Zynq-7020FPGA, 512 MB DRAM, 512 MB storage, and analog and digital I/O (input/output). Thisboard offers Gigabit Ethernet, CAN, USB, serial, and SDHC interfaces. It contains six-teen 16-bit analog inputs, four 16-bit analog outputs, and 28 digital lines of 3.3 volts.

Figure 5.6 depicts a block diagram of the SbRIO-9637 features. In this work, theFPGA is used as a processing core of the real-time simulation, whereas the processor han-dles functions concerning a graphical user interface, as well as the algorithms regarding aclassical transmission line protection relay. The first implementation stage is based on aninternal interconnection, i.e., a distance relay protecting a transmission line simulated inthe FPGA. A second implementation stage concerns an external closed-loop establishedbetween the transmission system simulation and an external device (DSP-based hardware)emulating a traveling-wave-based relay. For such a setup, two 16-bit analog outputs areused to provide the signals of current for the prototype relay, whereas two digital inputsare used to receive the information regarding the relays trip signal and one analog inputis used to receive voltage data from a signal generator which emulates the ideal voltagesources.

The specifications of SbRIO-9637 regarding the processor and FPGA are presented inTable 5.1 and Table 5.2, respectively. As explained further, the communication betweenthe processor and FPGA is carried out using DMA channels. The specifications related tothe analog inputs and outputs of sbRIO96-37 are described in Tables 5.3 and 5.4, respec-tively. The specifications regarding the 3.3 V digital I/O of the sbRIO-9637 are presentedin the table 5.5.


Processor

FPGA

512 MBNAND Flash

512 MBDDR3

USBFLY

GIGE 0FLY

CANXCVR

RS 232XCVR

RS 232XCVR

RS 485XCVR

FPGALED

StatusLED

UserLED

USBConnector

ENET 0Connector

CAN Port 0Connector

Serial Port 1Connector



Battery

Real-timeClock

TempSensors

x16 MUXAnalog Inputs

x4 MUXAnalog Outputs

x40 MHzOscilator

On-boardpowersupply

SD

IOC

onnec

tor

MIO

Co

nn

ecto

rD

IOC

onnec

tor

Pow

erC

onnec

tor

x4 Digital I/O (3.3 V, 5 V Tolerant)

x24 Digital I/O (3.3 V, 5 V Tolerant)

Zynq-7020SbRIO-9637

Figure 5.6: Features of the SbRIO-9637 controller board.

Table 5.1: CPU specifications.

Type Xilinx Zynq-7000, XC7Z020 All Programmable SoCArchitecture ARM Cortex-A9

Speed 667 MHzCores 2

Operating System NI Linux Real-Time (32 bit)Nonvolatile memory 512 MB

Volatile memory 512 MBReal-time clock, accuracy 5ppm

Flash rebut endurance 100,000 cycles

Table 5.2: FPGA specifications.

Type Xilinx Zynq-7000, XC7Z020 All Programmable SoCNumber of logic cells 85,000Number of flip-flops 106,400

Number of 6-input LUTs 53,200Number of DSP slices (18 x 25 multipliers) 220

Available block RAM 560 KBNumber of DMA channels 16

Number of logical interrupts 32


Table 5.3: Analog input characteristics.

Number of channels 16 single-ended or 8 differentialADC resolution 16 bits

Maximum sampling rate 200 kS/sInput range +/-10 V, +/-5 V,+/-2 V,+/-1 V

Input bandwidth (-3dB) 540 kHz

Table 5.4: Analog output characteristics.

Number of channels 4ADC resolution 16 bits

Maximum sampling rate 336 kS/sRange +/-10 V

Slew rate (-3dB) 3.7 V/µs

Table 5.5: 3.3 V digital I/O

Number of DIO channels 28Input low voltage -0.3 V minimum; 0.8 V maximumInput high voltage 2 V minimum; 5.25 maximumOutput low voltage 0.0 V minimum; 0.4 V maximumOutput high voltage 2.4 V minimum; 3.45 V maximum

5.2.3 TMS320F2833xThe TMS320F28335 is a 32-bit floating point digital signal controller (DSC) which

is used in this work to implement the traveling wave-based transmission line relay. Thename DSC refers to the architecture composed of a DSP and embedded peripherals in asingle chip. Figure 5.7 depicts the block diagram regarding such a device. The DSC struc-ture is comprised of an internal and external bus system, a central processing unit (DSPcore), internal memory sections, control peripherals, communication channels (e.g., CAN,SCI and SPI interface), direct memory access controller (DMA), interrupt managementunit (PIE) and core time unit, real-time emulation interface.

This work does not address the internal structure of each unit of the DSC. Detailedinformation regarding the internal structure of each module can be found in its datasheet[Texas Instruments n.d.]. Instead, it is presented an introduction regarding the boardresources required for the relay design, i.e., information concerning the register settingsnecessary to configure the hardware device based on the project requirements.

Some features of TMS320F2833x (Figure 5.7) digital signal controllers are:

• high-performance static CMOS technology

– up to 150 MHz;


SectoredFlash

RAMBootROM

DMA6 Ch.

32-bitAuxiliaryRegisters

32x32 bitMultiplier

R-M-WAutomatic

ALU

FPU

Register Bus

PIEInterruptManager

332-bitTimers

Data Bus

Program Bus

XIN

TF

DMA Bus

CPU

Real-TimeJTAG

Emulation

ePWM

eCAP

eQEP

12-bit ADC

Watchdog

CAN 2.0B

I2C

SCI

SPI

McBSP

GPIO

A(19-0)

D(31-0)

Figure 5.7: TMS320F2833x block diagram.

• high-performance 32-bit CPU

– IEEE 754 Single-precision floating point unit;– 16x16 and 32x32 MAC operations;– 16x16 dual MAC operations;

• enhanced control peripherals

– up to 18 PWM outputs;

• 12-bit ADC, 16 channels

– 80 ns conversion rate;– 2x8 channel input multiplexer;– two sample-and-hold circuits;– single/simultaneous conversion;– internal and external reference;

• up to 88 individually programmable, multiplexed GPIO pins with input filtering.

The relays must receive the current waveforms (or voltages) of the simulated systemfrom the analog outputs of the sbRIO-9637 board, process such information based on thedetection and protection algorithms, and in case of a fault condition, send the trip signalsback to the simulator (commands for opening the circuit breakers). Considering the useof a single board (eZdsp F28335), a priori two analog inputs (ADC input lines) must beused to receive the signals from the simulation, as well as two digital outputs (GPIOs),must be used to send the trip signals.


Other necessary issue concerns the sampling frequency selection of the travelingwave-based transmission line relay. In this work, such frequency is controlled using afixed-width PWM signal generated using the PWM module of the DSC. Specifically, inthe rising edge event of that signal, an interrupt service is requested for sampling thecurrent waveforms at the analog channels (ADC inputs). Therefore, the hardware devicemust be configured to generate a PWM signal at a set frequency as well as generate aninterrupt service based on an event of the PWM signal. All these features are definedbased on setting the registers related to each module, i.e., setting the clock module reg-isters (e.g., to adjust the CPU clock), the PWM module registers, registers related to theADC module, GPIOs registers, etc.

The configuration steps of the registers are introduced later in the description stageof the traveling-wave relay implementation. In addition to the resources configurationaforementioned, other necessary control settings are also addressed.

5.3 Application SoftwareThe FPGAs are programmed using the hardware description language such as VHDL,

which means "VHSIC (very-high-speed integrated circuits) Hardware Description Lan-guage", or Verilog. The projects developed using these languages are implemented atthe levels of digital circuit components. An advantage of such an approach regards thedevelopment of specialized digital circuits and systems, computationally efficient. A dis-advantage of using these languages is due to the level of complexity and specializationrequired for developing projects. A methodology using a friendly programming languageis verified in this work to perform real-time simulations of power systems.

5.3.1 LabVIEWLabVIEW is the programming environment used to develop the codes regarding the

real-time simulator implementation. The algorithms are implemented using a graphicallanguage of LabVIEW, nevertheless considering the restraints of the FPGA architecture.The SbRIO-9637 controller board was developed to allow such type of integration, i.e.,the algorithms are implemented using LabVIEW environment, these files pass throughstages of translation until a format that can be accepted by the FPGA.

Xilinx Vivado tools are used in the synthesis and implementation of the programs tobe executed by the FPGA. All necessary steps in the translation process are managedautomatically in the LabVIEW environment.

5.3.2 Code Composer Studio - CCSThe traveling-wave-based transmission-line relay is implemented using the standard

ANSI C/C++ programming language. The hardware device used to implement such relayhave the supports for developing projects using CCS (code composer studio) environment.The description regarding the implementation of both relay prototype and the real-timesimulator using the highlighted programming environments is presented later.


5.4 Case StudyAs emphasized in the abstract of this work, the real-time simulator concept, and its

applications, is presented based on the modeling, implementation, and simulation of asystem used as a case study. Such a purpose is addressed based on the simulation of atransmission system suitable for validating a transmission line relay operating second atraveling-wave-based protection method. Beyond this purpose, it is intended to introduce,broadly, the main concepts regarding the EMT simulation of power systems.

Figure 5.8 depicts the transmission system used as a case study, which is the sameone covered in Chapter 3, however focusing on real-time implementation. Such a systemis comprised of voltage sources, lumped resistive-inductive branches, circuit breakers, afault branch and, a 400 km transmission line. The voltage source elements are representedby sinusoidal functions, one of these is taken from an actual signal generator, whereas theother is a shifted version of it implemented using a circular buffer logic, as will be de-scribed afterward. The voltage and current measurements are taken from the simulationbackward the circuit breakers and are assumed to be ideal once the CT and PT are consid-ered here ideal elements. This work focused on the transmission line real-time simulationand use of its results for the validation of a traveling wave-based relay. Furthermore, thecurrent hardware capability limits modeling such devices. Those models will be added tothe real-time implementation in future works.

The transmission line is represented using two smaller lines segments. Thus, a short-circuit can be applied at the node formed by the connection of those line sections (Figure5.8). Such a representation allows the simulation of faults at different locations since theBergeron model of transmission lines is a terminal model. The change of fault point isachieved by setting the fault distance and the transmission line length. The length of thefirst line section is the same value used for the fault distance. The second line sectionlength is set using the difference between line length and fault distance.

The first stage of the relay implementation regards a classical transmission line protec-tion scheme (distance protection with MHO characteristic) using the real-time processorof the sbRIO-9637 controller board, i.e., by using the inner processor and FPGA theimplementation is not in the context of hardware-in-the-loop. The second stage of im-plementation concerns a traveling-wave-based transmission-line relay using an externalDSP-based controller board, i.e., considering the concepts of hardware-in-the-loop.

5.4.1 Computational Model of the Power SystemFigure 5.9 depicts the discrete representation of the power system under study. VS,

LEM, SW, TLM, and FCM concerns the voltage source, lumped element model, switches,transmission line model, and fault circuit model, respectively. The computational form ofthe power system is composed by the discrete model of each element (Chapter 3). Thetransmission line model allows the network solution to be computed in parallel.


Figure 5.8: The power system used as case study.

TLM

FCM

S ystemubs

VS + LEM

SW SW

S ystemubs S ystemubs

Figure 5.9: Computational model of the power system

5.5 Goals and DemandsThe remainder of this chapter is committed to present the implementation steps re-

garding the real-time simulation of the power system used as the case study (Figure 5.8)as well as the implementation of the transmission line relays.

Some of the goals and demands to be addressed in the implementation steps are:

• The simulation in FPGA of EMTs taking place a transmission system due to con-trolled switching events. To accomplish such a purpose, it is necessary to implementan EMTP-type program for building the real-time simulation (Chapter 3).

• Implementation of a graphical interface, carried out in the real-time processor, formonitoring the simulated system. For achieving such a goal, it is necessary to opena communication link from the processor to FPGA, send the required parameters forthe simulation, and after this action close such channel. Moreover, it is necessary toestablish a communication link from the FPGA to the real-time processor to receivethe voltage and current data generated in the simulation.


• To implement a distance relay for the transmission line protection using the real-time processor. Such relay, which monitors in real-time the transmission line, mustbe placed in a closed-loop with the power system simulation. Thus, a commu-nication link must be established from the FPGA to the processor, for receivingthe current and voltage data, and another one from the processor to the FPGA, forsending the command to open the circuit breakers when a fault occurs (Chapter4).

• To implement a traveling-wave-based transmission-line relay in a DSP chip usingthe math presented in Chapter 4 [Costa et al. 2017]. Such a relay must receivecurrent/voltage data from the simulation carried out in the FPGA as well as sendthe trip signal to the FPGA which, recognizing the trip command, must emulate theopening event of the circuit breakers.

As illustrated later, the switching events concerning both closing and opening of thecircuit-breakers are carried out in the FPGA by selecting an admittance matrix corre-sponding to a particular power system configuration.

5.6 Numeric RepresentationThe numerical representation for the system variables is directly related to the simu-

lation accuracy and use of the available hardware resources. Generally, this issue boilsdown in choosing the fixed-point or floating point format. Using the same number of bitsfor the fixed point and floating point format, the last one allows the representation of alarger range of values. However, it can result in more hardware utilization. The fixed-point format precision is directly related to the programmer choice, i.e., accurate resultscan be obtained considering a suitable number of bits for data representation.

The FPGA chip of the sbRIO-9637 handles the necessary calculations using the single-precision floating-point numeric format. Such a representation is the one adopted to im-plement the power system under study. The standard 32-bit IEEE single-precision floatingpoint format is composed of a signal bit, 8 bits for the exponent representation, and 23mantissa bits. Figure 5.10 depicts such a standard. A number represented using thisstandard format can be presented as follows

X = (−1)S2(E−B)(1.M), (5.1)

where S, E, B and M are related to the signal, exponent, exponent-bias and mantissa,respectively.

sign exponent mantissa

131 232432bit

Figure 5.10: Standard 32-bit IEEE single-precision format.


5.7 Time-StepThe value of 50 µs is the time-step commonly used for the real-time simulation of

EMT in power systems [Faruque et al. 2015]. Taking into account that in this work it isintended to perform real-time simulations aiming to represent the traveling-waves takingplace transmission lines as well as be able to detect the first arrival of them at the lineterminals based on high-frequency information, a limit time-step of 11 µs (e.g., a valuesmaller than 50 µs) is fixed as the limit value which can be used for still achieving the real-time purposes. 20 µs is the time-step used in the real-time simulations illustrated in thenext chapter. Such a value is chosen also aiming to verify, based on the execution time-parameter, the hardware capability to handle real-time simulations using smaller than 50µs time steps.

5.8 General Programming ArchitectureFigure 5.11 depicts the real-time simulator programming structure. The processor

carries out a GUI, a precalculation stage, and a producer-consumer pattern. The FPGAcarries out a task to receive and save all the necessary parameters for the simulation aswell as the EMTP loop (i.e., the simulation loop). On the other hand, the DSP is thedevice in charge to handle the traveling-wave-based transmission-line relay. It carries outthe stages regarding the protection parameters settings, registers settings, data acquisition,detection method, protection scheme, and trip logic.

Most of the parameters defined from the GUI (e.g., terms regarding both the simula-tion and power system) are used in the precalculation stage to figure out all the necessarycoefficients concerning the models of the power system components. Such coefficientsare also used to build the admittance matrices regarding each system configuration.

The producer-loop (Figure 5.11), which is generally related to the structure producingdata, actually, is receiving the current and voltage waveforms from the FPGA. This loopis in synchronism with the simulation loop executing in FPGA, although running in alower frequency (currently at 1 kHz). Routines related to the phasor estimation technique,detection method, and protection algorithm are the algorithms implemented to representthis classical relay. The consumer-loop receives data from the producer-loop as well ashandles the strategies for updating the GUI.

The FPGA and processor communicate with each one using two different communi-cation links. The first concerns two DMA (direct memory access) channels and the othera point-to-point link. The first DMA channel is used at the precalculation step to sendto FPGA all the information required by the EMTP algorithm. The second DMA chan-nel is used by FGPA to stream in real-time the simulation results to the processor. Thepoint-to-point channel is used to send to FPGA manual commands such as the ones forapplying shorts-circuits, open the circuit breakers, disable the relays, as well as to sendthe trip signal from the distance relay to FPGA.


Figure 5.11: RTS programming structure.

The voltages at line terminals are provided from the FPGA to DSP using wires con-necting two analog outputs of the FPGA (DAC interface) to analog inputs of the DSP(ADC interface). The trip signals regarding the traveling-wave-based transmission-linerelays are sent from DSP to FPGA using two wires connecting GPIOs of the DSP todigital ports of the FPGA.


5.8.1 Graphical User InterfaceFigure 5.12 depicts the graphical user interface implemented for control and real-time

monitoring of the simulated power system. The numerical controls of the GUI, whichare employed to enter or display numeric data, are used to set the power system param-eters, such as the ones regarding the lumped elements (e.g., inductance and resistance),transmission line (e.g., resistance, inductance, capacitance, and length), fault circuit (e.g.,resistance, angle, location, and fault instant), distance protection (e.g., protected zone,loading, overload factor), and operation frequency, as well as the simulation parameters,such as the simulation time and integration time-step. One numerical control is used todisplay the execution time of the simulation, which is the time demanded by the FPGA tosolve the necessary equations and, thereby, generating one simulation result. It must beless than integration time-step for the simulation to be executed in real-time.

The GUI provides access to three enumerates controls (selection lists). Two of themare related to graphical indicators, which are used to display voltage and current wave-forms of the simulation. The first control allows the choose between display the phasor es-timation results of the distance relay (module and subsampled waveform of current) or thecurrents measured at the line terminals (without subsampling). The second control allowsthe choose among displaying the phasor estimation results of the distance relay (moduleand subsampled waveform of voltage) and nodal voltages of the power system (withoutsubsampling). The last one enumerate list allows selecting the type of transmission lineprotection, which can be provided by the distance relay, traveling-wave-based-relay orusing a manual command.

Three pushbuttons are also available on the GUI. Such controls allow applying a faultmanually, provide a manual relay trip (when the manual operation mode is selected) andstop the simulation, respectively.

Figure 5.12: RTS programming structure.


5.8.2 Pre-Calculation StageThe computational model of the power system, as depicted in Figure 5.8, is com-

posed of current sources and equivalent resistances. As highlighted in an earlier chapter,EMTP-type programs, which contains the logic to build the simulation of power systems,is formulated based on such an approach. The solver formulation starts offline in the pre-calculation stage (Figure 5.11), where it is performed the necessary calculations regardingthe model parameters, constant coefficients, and building of the admittance matrices re-garding each power system configuration.

Power system models

The equations (3.30), (3.31) are used to calculate the equivalent resistance and updatethe current sources of the resistive-inductive branches (Table 3.1), respectively. Suchequivalent resistance (Req) and a constant coefficient (C) of (3.31) are precalculated usingthe resistance (R), inductance (L), and ∆t (time-step) parameters sent via GUI. Table 5.6summarizes some operations performed in the pre-calculation stage related to the lumpedelements model. The indices RL1 and RL2 are used to specify the respective lumpedelement.

Table 5.6: Pre-calculation required for the Lumped elements model.

Terms regarding the lumped elements model EquationReq,RL1 RRL,1 +LRL,1/∆tReq,RL2 RRL,2 +LRL,2/∆tCRL1 (LRL,1/∆t)/Req,RL1CRL2 (LRL,2/∆t)/Req,RL2

The coefficients C and 1/Req are the ones sent to the FPGA to be used in the stepregarding updating the current sources of the resistance-inductance branch model. 1/Reqis a parameter used in the network solution formulation.

The equations (3.70), (3.72), and (3.73) are used to calculate the equivalent character-istic admittance (Ye) and update the current sources (IH) of the transmission line model,respectively. Such admittance (resistance dimension) as well as the constant coefficientsof (3.72) and (3.73) are pre-calculated using the transmission line parameters sent viaGUI, such as inductance (l), resistance (r), capacitance (c), length (d) and fault distance(dF ).

Table 5.7 summarizes some operations performed in the pre-calculation stage relatedto the transmission line model. The parameters R, Zc, τ, and h are the lumped resis-tance, characteristic impedance, traveling-wave propagation time, and a coefficient of thetransmission line model. The names sec1 and sec2 are used to specify the line section.

The coefficients h, (1+h)/2, (1−h)/2, and (1+h)Ye of equations (3.72) and (3.73),as well as the parameter bτ/∆te, are the ones sent to the FPGA to be used in the step ofupdating the current sources of the transmission line model. The operation be concerns thenearest value since τ must be an integer number. The errors regarding such approximation


Table 5.7: Pre-calculation required for the transmission line model.

Terms regarding the transmission line model EquationRsec1 rdFRsec2 r(d−dF)

Zc√

l/cτsec1 (

√lc)dF

τsec2 (√

lc)(d−dF)Ye,sec1 1/(Zc +Rsec1/4)Ye,sec2 1/(Zc +Rsec2/4)hsec1 (Zc−Rsec1/4)/(Zc +Rsec1/4)hsec2 (Zc−Rsec2/4)/(Zc +Rsec2/4)

can be reduced using small integration time-steps. Ye is a parameter used in the networksolution formulation.

Network solution

The network solution (Chapter 3) can be formulated by building an admittance matrixfor a power system configuration, a vector of injected currents, and solving the equation(3.78) for the unknown voltages. Depending on the used methodology, such an approachdemands to perform matrix operations for each power system setup, such as matrix re-duction as well as an inverse matrix calculation or the use of a decomposition method(e.g., LU) to solve (3.78). These methodologies demand a lot of hardware consuming forachieving real-time purposes.

In the real-time approach presented in this work, the power system is decoupled intothree smaller subsystems. The inverse matrices operation, when required, is performedoffline in the pre-calculation stage. These data are sent to FPGA via a DMA channel tobe used further in the network solution stage of EMTP loop, i.e., to solve equations in theform of (3.79).

Figure 5.13 depicts the possibilities of configuration for the subsystems illustrated inFigure 5.11. SW1, SW2, and SW f are parameters of the switches models representing thecircuit breakers and fault switch states, respectively. A fault takes place by setting SWf toon stage, whereas a circuit breaker operation is accounted identifying a trip signal fromthe relays and setting SW1 and SW2 to off state, i.e., the power system state is directlyrelated to the switching status.


S ystemubs 1 S ystemubs 2 S ystemubs 3

SW1: on SWf: off SW2: on

SW1: off SWf: on SW2: off

S ystemubs 1 S ystemubs 2 S ystemubs 3

Figure 5.13: Computational model of the power system

Simulation parameters

The samples related to the fault instant, fault angle, and simulation time are calculatedbased on integration time-step. All these data are sent to FPGA using a DMA channel.The sample regarding the fault angle (nφ,F ) is calculated by means of

nφ,F =

⌊φ

360 f ∆t

⌉, (5.2)

where φ, f , and ∆t are the fault angle, the operation frequency of the power system, andsimulation time-step.

Sending Simulation Parameters

Figure 5.14 depicts a diagram of one communication link established from the proces-sor to FPGA. This link is performed aiming to send all the necessary data to FPGA, suchas the coefficients of component models, information of the power system configuration,fault parameters, time-step, etc. Such a communication line is achieved using a DMAchannel (Table 5.2).

A FIFO (first-input-first-output) structure is configured (e.g., setting the length anddata-type) within the FPGA environment. A LabVIEW function (a FIFO method node)provides access to such elements for operations of writing or reading (Figure X). Onthe other way, the DMA channel is accessed within the processor environment using aninvoke method, a LabVIEW function (Figure 5.14), which allows sending to or receivingdata from the buffer created in FPGA.

Hence, a vector of parameters is sent to FPGA using a invoke method (configured towrite data to the FIFO) and received in FPGA using a FIFO method node (configured toread) as well as an algorithm to organized and save those data for be used later within thesimulation loop (Figure 5.11).


Figure 5.14: DMA channel.

5.8.3 Producer-LoopThe producer-loop handes the functions for receiving the voltage and current data (two

DMA channels) as well as the distance protection relay. The DMA channel provides thesynchronization between the producer-loop and EMTP-loop since the simulation data isread in blocks with a length defined as

Npdb = ( fs/1000)∗Nsdb, (5.3)

where fs is the simulation sampling-frequency, the number 1000 is related to the operatingfrequency of the producer-loop (fixed at 1 kHz), Npdb is the processor data block, and Nsdbconcerns the sequence of data inserted into the FIFO buffer concerning the simulation(e.g., a data block of node voltages).

Receiving Simulation Data

Figure 5.15 depicts a diagram of the DMA communication link established from theFPGA to the processor. Two channels using such type of communication are set up tostream in real-time the simulation data regarding voltage nodes and terminal currents tothe processor. As aforementioned, the block of node voltages is enqueued in a buffer inthe simulation loop and dequeued in the processor in blocks of length defined by (5.3),whereas a block of terminal currents is enqueued in another buffer in FPGA and dequeuedin the processor blocks of length also defined using (5.3).


Figure 5.15: DMA channel.

The received voltage and current are sent to the consumer-loop using a similar FIFOstructure. Figure 5.16 depicts such diagram. A queue structure is created and configuredin the processor. A block of simulation data is enqueued into the queue structure using anenqueue function, whereas a block of data is dequeued from the queue structure using adequeue function. Such an approach allows updating the GUI from the consumer-loop ina lower frequency (e.g., few units or decades of Hz).

Figure 5.16: Queue structure.


Sending Commands to Simulation

A bidirectional communication link is set up between the processor and FPGA, orrather, between the producer-loop and simulation-loop, using a read/write control func-tion. Figure 5.17 depicts such a structure. This channel is used to send commands viaGUI, such as the trip signal, apply a fault manually, stop the simulation, and informationregarding the selected protection method, as well as the distance relay trip. This samechannel is used to receive from FPGA the execution time of the simulation and the circuitbreakers status.

The circuit breakers can operate based on a command signal provided by a distancerelay, a manual button (from GUI) or the traveling-wave-based-transmission-line relay.These information are enabled according to the protected method selected via GUI.

Distance Relay

The distance relay is implemented from a sub-sampling stage, one-cycle Fourier pha-sor estimator and a distance protection algorithm. The parameters related to such a pro-tection method, such as protected zones in percent, loading, overload factor, are definedusing the GUI. The sub-sampling stage emulates the relay sampling step since the powersystem simulation and the distance relay are arranged into a single chip (Figure 5.6), i.e.,such device access the simulation samples. Therefore, at each iteration of the producer-loop, the relay selects a current and voltage samples within the data block (Figure 5.15).

Figure 5.17: Read/Write control function.

Figure 5.18 depicts a diagram of the phasor estimation unit concerning the estima-tion of module and phase of the fundamental component of current. This unit receives asample of current, updates a sliding window, performs the calculation regarding Fourierestimation, and outputs the module and phase of the estimated phasor. This informationis streamed to the consumer-loop using a queue structure for updating a graphic indicator(Figure 5.12). The phasor estimator runs based on a 20-sample per cycle sliding windowsince the relay sampling frequency is set up to 1 kHz.


Figure 5.18: Phasor Estimator.

Figure 5.19 depicts a simplified diagram of the distance method regarding the MHOcurve. Module and angle information of voltage and current are used to estimate thetransmission line relative impedance. A threshold of current (Isp) is used to detect anovercurrent event. The parameters (ZN) is the line impedance.

Figure 5.19: Distance Protection.

5.8.4 Consumer-LoopThe consumer-loop is the structure in charge of updating the graphical indicators of

the GUI. As depicted in Figure 5.16, it receives data from the producer-loop accessing aqueue structure, such as the power system terminal currents, node voltages, and phasorestimation results. These data are rearranged and provided to graphic indicators. Figure5.20 depicts a diagram of the updating stage of a graphic element. A list of the GUIcontrols the type of information to be displayed.

5.8.5 Receiving the Simulation ParametersAs depicted in Figure 5.14, the FPGA receives the simulation parameters, processed

in the precalculation stage, by accessing a FIFO structure. The data placed into this bufferare removed from it in the same order as was put, i.e., the first sequence of parametersinserted in the queue are the first ones to be taken.


Figure 5.20: Updating the graphic indicators.

Figure 5.21 depicts a diagram containing the logic implemented to receive the sim-ulation parameters. Considering two data sequences of length n1 and n2 related to twodifferent elements were put into a FIFO structure in the precalculation stage, if FIFOtime out is not flagged, i.e., there are elements inside the FIFO structure, a logic blockcomprised of a counter, logic elements and a binary to decimal converter, works to se-lect a case to save correctly the sequences of data into its respective variables. When thelast value is received and allocated, a boolean command is sent to a stop variable of thewhile-loop aiming to close the receiving data stage and proceed toward the simulationloop (Figure 5.11).

5.8.6 EMTP LoopThe EMTP loop contains the logic structure in charge of generating the simulation

results. For the current implementation, this structure is executed right after the receivingstage of the simulation parameters (Figure 5.11). Figure 5.22 depicts a diagram contain-ing the EMTP-type algorithm implemented in FPGA to handle the real-time simulationof the power system used as the case study. VSU, ATLU, LEU, NRU, TLU, NSU, CMU,TL, and FL are related to voltage source unit, auxiliary transmission line unit, lumpedelement unit, network reduction unit, transmission line, unit, network solution unit, cur-rent measurement unit, and trip logic selection and fault logic units, respectively. AI, AO,DIO, memory, and SR are related to analog inputs, analog outputs, digital input/output,RAM memory blocks, and shift-register elements, respectively.

The while structure, i.e., is a time-based loop which is set up to execute each inter-action based on the selected time-step via GUI. The internal implementation of each unitimplemented in it is detailed ahead.


Figure 5.21: Diagram illustrating the logic implemented to receive the simulation param-eters.

Voltage Source Unit (VSU)

The ideal voltage sources are emulated using an external voltage signal provided byan actual signal generator. Such an approach was adopted also aiming to verify the pos-sibility of connecting external signal sources to the simulation, e.g., a future connectionof a controlled current source tracking the behavior of an external system. The signalgenerator is set up to provide a 50 Hz, 1 V signal.

Figure 5.23 depicts the internal structure implemented for representing the ideal volt-age sources. AI (analog input) is related to a function provided in the development soft-ware to access the input data obtained right after the analog-to-digital conversion stage.A circular buffer is implemented using a fixed-size memory block (FPGA constraint) tostore a frame of samples of the input signal. The strategy used in such implementationallows for obtaining a shifted copy of the input voltage signal for any specified angle.Therefore, the outputs of the module VSU are samples of two voltage sources.

Considering the variable Tp is a time interval related to a signal period. The numberof samples per cycle (N) of such a signal can be obtained using

N =Tp

∆t, (5.4)

where ∆t and N are related to the time-step and number of samples contained in a cycleof the input signal, respectively. Thus, the sample (NS) related to an angle φ of the inputsignal can be computed using

NS =φ

360N. (5.5)


Figure 5.22: Diagram of an EMTP-type algorithm.

Figure 5.23: Voltage source unit.

Considering that pR and pW (Figure 5.23) are auxiliary variables which provide theaddresses to access the circular buffer for reading and writing operations, a copy of theinput signal, shifted φ, is achieved by accessing the information stored in the address pRof the circular buffer, since an input signal sample is written at index pW of this buffer ineach interaction of the simulation loop.

Both pR and PW are limited within the integer interval [0, NS]. The relationship of pRand pW is in the form of

pR = pW +1. (5.6)

Auxiliary Transmission Line Unit (ATLU)

The current sources calculation of the transmission line model (3.72,3.73) requiresaccessing samples of voltages and its past values at the time-step (k−NPT ) or (k−Nτ),


being NPT (Nτ) the sample related to the transmission-line propagation time. This integervalue is calculated using

Nτ =⌊

τ

∆t

⌉, (5.7)

where ∆t is the integration time-step.The auxiliary transmission line unit receives the newest samples of the line terminal

voltages and current sources, accessing such values stored in shift registers (SR), andprovides to the transmission line models the terminal voltages and current sources cal-culated at the time-step (k−Nτ). Figure 5.24 depicts a generic diagram of the auxiliarytransmission line unit. This module is implemented to handle information regarding twotransmission lines in parallel.

Figure 5.24: Auxiliary transmission line unit (ATLU).

Figure 5.25 depicts a diagram of one auxiliary module (Figure 5.24). This unit iscomposed of four circular buffers implemented in fixed-length memory blocks, which arerelated to the terminal voltages and current sources.

Transmission Line Unit (TLU)

The transmission line unit (TLU) is the module in charge of computing the currentsources of the transmission line model. Figure 5.26 depicts the diagram of the imple-mented TLU structure. This unit receives past information from the ATLU unit, updatesthe current sources of the transmission line model, and provide it for the network solutionunit (Figure 5.22). The TLU unit is implemented to handle calculations regarding twotransmission lines in parallel.

Figure 5.27 depicts the diagram regarding the internal structure of one transmissionline model (Figure 5.26). The terminal voltages and current sources calculated at thetime-step k−NPT (k−Nτ), as well as the coefficients stored in a variable concerning sucha unit, are used in the operations governed by the equations (3.72,3.73).


Figure 5.25: Auxiliary unit for one transmission line.

Figure 5.26: Transmission line unit (TLU).

Lumped Element Unit (LEU) / Network Reduction Unit (NRU)

The lumped element unit (LEU) is the unit in charge of computing the current sourcesregarding the linear lumped elements, whereas the network reduction unit (NRU) is themodule used to combine the lumped element model and the voltage sources in a Nortonequivalent circuit (Figure 5.9). The current sources of that circuit are the ones sent tonetwork solution unit.


Figure 5.27: Transmission line model.

Figure 5.28 depicts a diagram of the LEU and NRU modules. The LEU unit is com-posed of two parallel blocks, each one performing the calculation of the current sourcesof a linear lumped element. These blocks receive information of current and voltagesstored in shift registers, i.e., terminal voltages and currents flowing through the lumpedelement calculated at the previous time-step, and provides the current sources of its dis-crete model. The NRU unit receives these current sources, as well as the parameters ofthe lumped elements models and data from VSU unit, and send to the output the currentsources of a Norton equivalent circuit.

Figure 5.29 depicts the internal structure regarding one block of the LEU unit. Thisunit retrieves current and voltages data from shift registers, as well as the model coeffi-cients stored into a variable, and provides to the output the current source of its discretemodel.


Figure 5.28: Lumped Element Unit (LEU)/Network Reduction Unit (NRU).

Figure 5.29: Lumped Element Unit (LEU).

Network Solution Unit (NSU)

The network solution unit (NSU) receives the current sources from both TLU andLEU/NRU unit and provides to its output the nodal voltages of the power system understudy. Furthermore, it receives information regarding the switches status from LT and LFunits. Figure 5.30 depicts the general diagram of the NSU module. This unit is composedof three parallel blocks, each one carrying out the calculation concerning one subsystem(Figure 5.13). The calculated nodal voltages are sent to shift registers.


Figure 5.30: Network Solution Unit (NSU).

Figure 5.31 depicts a diagram regarding the internal structure of the subsystem 1.Circuit breaker 1 (CB1) allows selecting true or false case based on its status, i.e., inoperational conditions the circuit breaker status is closed (true case), whereas it will open(false case) based in a manual command or a relay trip signal.

For the CB1 opened, the nodal voltages V1(k) and V2(k) (nodes before and after CB1element) is calculated in the form of[

Vi(k)Vj(k)

]=

[a 00 b

][Ih,i(k)Ih, j(k)

].

For the CB1 closed, the nodal voltages V1(k) and V2(k) is calculated by using

Vi(k) =Vj(k) = c∗ (Ih,i(k)+ Ih, j(k)),

where a, b , and c the concerns the admittance matrices for circuit breaker in the opened(2x2 order) and closed states (1x1 order). Ih,i(k) and Ih, j(k) are the current sources con-nected to the nodes i and j. This block provides the nodal voltage V3(k) (fault node).

Figure 5.32 depicts a diagram regarding the internal structure of the subsystem 2. Afault switch allows selecting true or false case based on its status, i.e., in operationalconditions the switch status is opened (false case), whereas it will close (true case) basedin a manual command or based on fault requirements, which is set via GUI.

For the switch closed or opened, the nodal voltage V3(k) and is calculated by using

Vi(k) = a∗ (Ih,i(k)+ Ih, j(k)).


Figure 5.31: Subsystem 1.



Figure 5.33 depicts a diagram regarding the internal structure of the subsystem 3.Such an arrangement is similar to subsystem 1. This block provides the nodal voltagesV4(k) and V5(k) (nodes before and after CB2 element).


Trip Logic (TL) Selection Unit

The trip logic (TL) selection unit receives a value regarding the transmission-line pro-tection method selected via GUI. Based on it the unit selects a trip signal source, whichcan be a manual command (button of the GUI), a distance relay or the traveling-wave-based transmission-line protection. Figure 5.34 depicts the TL unit diagram. Such amodule provides trip commands to the NSU unit, which is used to updates the circuitbreakers state.

Figure 5.34: Trip logic selection unit.


Figure 5.35 depicts the internal structure of one TL unit diagram concerning one cir-cuit breaker. The I/O item is a function that is used to catch the trip command whichcomes from the traveling-wave-based relay (DSP-based board). When a trip command isdetected a counter starts it count until up to the delay related to the circuit breaker me-chanical operation, which opens when the local current waveform crosses the zero-edge(ZCD - zero crossing detection).

Figure 5.35: Trip logic selection unit.

Fault Logic (FL) Unit

The fault logic unit (FL) is the module that contains the logic for updating the switchstate of the fault circuit. A fault can be applied manually or by using a logic section thatconsiders the samples concerning fault time and angle. This one is implemented basedon an initially zero-crossing detection at the rising edge of the voltage at the fault point.A fault event is stated right after an internal counter achieves the sample the fault angle.Such an element is set up to zero when simulation reaches the fault sample and the zero-crossing detection is flagged.

Figure 5.36 depicts the internal structure of the FL unit. This module receives thevoltage samples at the fault point and information regarding the current simulation sam-ple. It provides to the network solution unit a command related to the switch status of thefault circuit.


Figure 5.36: Fault logic unit.

Current Measurement Unit (CMU)

The current measurement unit (CMU) is the module used to provide the terminalcurrents of the power system under study. This unit performs the calculations governedby equation 3.29, which represents the current flowing through the resistive-inductiveelements. Figure 5.37 depicts a diagram of the CMU unit. It receives the terminal voltagesand current sources regarding the resistive-inductive model.

Figure 5.37: Current measurement unit.


Sending the Simulation Data

The nodal voltages and terminal currents regarding the simulation of the power systemused as the case study are sent to the processor using two DMA channels (Figure 5.15.Moreover, these terminal currents are sent to DSP by means analog outputs (Figure 5.22),i.e., after a digital to analog conversion step.

5.8.7 Traveling-Wave-Based Transmission-Line RelayThe remainder of this chapter is engaged to introduce the implementation steps regard-

ing a traveling-wave-based transmission-line relay prototype in a DSP chip. As depictedin Figure 5.11, the DSP receives the simulation data from two analog inputs. Each inputline receives a terminal current of the power system under study. The current waveformsat that input lines of the DSP chip are discretized by the ADC conversion module and itssamples stored into registers of this same module. The relay prototype must catch thesedata and use it as input for the detection and protection method within each time-step.Furthermore, when a fault taking place the simulated transmission line, such a prototypemust send a trip signals back to the FPGA.

Figure 5.38 depicts the general diagram regarding the relay prototype implementation.This design is composed of stages regarding the protection system parameters definition,initialization routines, registers configuration, data acquisition, detection method, protec-tion scheme, trip logic, and GPIO setting. The system parameters definition is the codesection used to states the necessary global variables related to the implemented methods.The initialization and configuration registers stages are related to the hardware set upaccording to the protection system requirements. The acquiring data block is used to re-trieve the simulation currents stored in registers of the ADC module. This block providesthese data to the detection block. The detection and protection algorithms used in such animplementation are the ones presented in Chapter 4. The protection module receives thesamples related to the arrival time of the first wavefront at the transmission line terminalsand provides the trip state to the GIO setting block. This last unit provides to FPGA thesignal containing the relays trip state.

Protection System Parameters

Table 5.8 lists the main variables used in the relay implementation. x0, x1, x2, x3,and hψ are the variables used to store information of current, and 4 coefficients vectorregarding the used Wavelet filter. Limiar and kx are a threshold value for the Waveletcoefficients used to define a fault event occurrence and the variable used to store thearrival sample of wavefronts at the protection buses. fs, d, c, are related to relay samplingfrequency, transmission-line distance and speed of light, which are parameters used tocompute the protection parameter d fs_c (bd ∗ f s/cc). IsBloked is a flag used to controla count variable (Counter). The counter starts the counting when the first wavefront ofcurrent is detected (by the relay i or j) and stops when the other first wavefront is detected(relay i or j). The initial and final values of the counter are allocated to variables ki andk j.


Figure 5.38: General relay structure

Table 5.8: Protection System Parameters.

Classification General Relay i Relay jDetection method hψ, Limiar, Counter x0,i, x1,i, x2,i, x3,i, ki x0, j, x1, j, x2, j, x3, j, k jProtection scheme fs, d, c, d fs_c tripi trip j

Auxiliary Flag IsBlocked

Initialization Routines

A first step taken for the relay design is related to the registers settings of the DSP,such as ADC module registers, PWM module registers, interrupt services registers, CPU-timers registers, aiming to set up such device to operate according to the established pro-tection system requirements, e.g., the sampling frequency of ADC converters (in the orderof tens or hundreds of kHz). It is worth noting this frequency can be controlled using afixed-length PWM signal, i.e., for each rising edge of the PWM a signal (within one pe-riod) an event routine can be requested to retrieve the data stored into ADC registers. Thisapproach is set up for emulating the relay sampling frequency.

The section regarding the initialization routines (Figure 5.38) is used to call the func-tions containing codes concerning a DSP pre-configuration. These code sections are de-fined in external files and are related to ADC registers, device system, PIE control, PIEvector table, and CPU 32-bit timers. The device system file contains the functions toinitialize the CPU clock (150 MHz SYSCLKOUT) and its submultiples, such as the high-speed pre-scaler clock (HSPCLK) and low-speed pre-scaler clock (LSPCLK), which act


as clock sources for the peripherals. CPU 32-bit timers file includes the functions regard-ing CPU-timers, and the PIE (peripheral interrupt expansion) control and vector table filecontain the initialization codes regarding interrupt services.

Registers Configuration

The register configuration stage (Figure 5.38) contains the code lines used to callinternal functions implemented to set up the registers related to the GPIO, ADC and thePWM module to configure the ports for sending the trip signals, generate a controlledPWM signal, set up the ADC input lines, ADC sampling rate, and an ADC event routine,etc.

Table 5.9 lists the set of registers used to configure the DSP chip. The register GPx-MUXy is used to set up two GPIOs to work as general I/O ports and one GPIO port tooutput a fixed-length PWM signal. GPxDIR register is used to configure those two portsas output, which outputs the relay trip commands. Registers ADCTRL1, ADCTRL2, andADCTRL3 are used to enable, configure and request an interrupt service from a PWMtrigger as well as set ADC clock. This interrupt function is used to retrieve the data focurrent stored in registers. The registers ADCMAXCONV and ADCCHSELSEQ1 set upthe number of conversions and the ADC input lines, respectively. Two input lines areselected to receive the current waveforms from FPGA. The registers TBCTL, TBPRD,CMPA, and AQCTLA are used to set up a 100 kHz fixed-length PWM signal. The regis-ters ETPS and ETSEL are set up to generate a trigger to ADC module at each rising edgeof that PWM signal.

Table 5.9: Registers Configuration.

ADC module RegistersGPIOs GpioCtrlRegs.GPxMUXy

GpioCtrlRegs.GPxDIRADC AdcRegs.ADCTRLx

AdcRegs.ADCMAXCONVAdcRegs.ADCCHSELSEQ1

PWM EPwm2Regs.TBCTLEPwm2Regs.TBPRDEPwm2Regs.CMPA

EPwm2Regs.AQCTLAEPwm2Regs.ETPS

EPwm2Regs.ETSEL

Acquiring Data

The data acquisition stage (Figure 5.38) is implemented to retrieve the samples ofcurrent from a register at each 20 µs. This time-step is defined to represent a traveling-wave-based transmission-line relay operating at a sampling frequency of 50 kHz. Figure5.39 depicts a general diagram of acquiring data block. This module provides the samples


related to the power system terminal voltages to the detection module. The value storedin the ADCRESULT0 register is a value within the range [0-4095] which is representinga voltage signal from 0 to 3 V. The constant 3/4095 is used to convert that number storedin a register into data of voltage.

Figure 5.39: Acquiring Data

Detection Method

The detection block (Figure 5.38) receives the samples of voltages from acquiringdata block and provides to protection method block the information regarding the arrivaltime of the traveling-waves at the line terminals. Figure 5.40 depicts a general diagramof the detection method block. This module is composed of sub-blocks related to theWavelet coefficients calculation and a logic section to determine the samples representingthe first wavefronts arrival time. 4 coefficients Wavelet filter (hψ) is used to compute theWavelet coefficients wx regarding of the input signal. A 4-sample time window is updatedat each time-step and provided to Wavelet coefficients sub-block. Counter initial value isallocated to a kx variable related to the relay which first detecting the wavefront arrival.Such a variable counts up until the remote relay detects the wavefront arrival. Counterfinal value is allocated to a kx variable of this relay. The Counter is controlled by meansthe logic sections containing the boolean variable IsBlocked. IsBlocked is initiated astrue.

Protection Scheme and Trip Logic

The protection block (Figure 5.38) receives the kx and Aux_kx values from detectionblock and provides to the GPIOs settings block the trip state of the relays. Figure 5.41depicts the general diagram of the protection method block. Considering a relay locatednear the local bus i (transmission line terminal), the protection algorithm receive from thedetection block the sample (ki) concerning the arrival time fo the first wavefront at the busi and waits for the information (k j) from the remote relay regarding the arrival time of thefirst wavefront at the bus j (transmission line terminal). In the current implementation,the delays related to the communication devices and propagation channel are emulatedusing an auxiliar counter, i.e., the local relay receives the information from remote relayN samples after the traveling wave detection by the remote relay. E.g., the relay i recog-nizes the remote information by accessing the variable Aux_ki, which is equal k j howeveraccounted after N.


Figure 5.40: Detection Method

Figure 5.41: Protection method

GPIO Setting

The GPIO setting block (Figure 5.38) receives the tripi and trip j states from protec-tion block and setup the GPIO lines to high-state (3.3 V) if trip signal is true. Figure 5.42depicts a diagram of the GPIO setting block.


Figure 5.42: GPIO setting.

5.9 SummaryThis Chapter provided information regarding the implementation of a real-time simu-

lator for validation of traveling-wave-based transmission-line protection. It is comprisedof sections presenting the used hardware devices, the mounted physical structure and de-scription of the simulator design using a case study as reference. Furthermore, it providedthe implementation steps of a traveling wave-based transmission line relay prototype in aDSP chip as well as its integration with the simulation running in FPGA.

Chapter 6

Results

This Chapter provides the results regarding both the real-time simulation and thehardware-in-the-loop validation, which is achieved by means a closed-loop establishedbetween a traveling-wave based-transmission-line relay and the simulated power system.The real-time simulation is validated based on the time-step and execution-time parame-ters, as well as the voltage and current waveforms comparison with the ones obtained fromthe Matlab/Simulink environment. The hardware-in-the-loop setup is evaluated based onthe protection system results for case studies. Such cases concern the real-time interac-tion between the real-time simulation and the relay prototype for faults taking place thetransmission line in the protected, uncertainty, and unprotected zones.

6.1 Real-Time Simulation ValidationFigure 6.1 depicts the power system used in the real-time simulation validation. The

abbreviations VS, LE, CB are related to the voltage sources, lumped elements, and circuitbreakers. A fault event with resistance 0.1 Ω, inception angle of 60° is triggered 200 kmfar from Bus 1. Aiming to compare the simulation results for the transient- and steady-states, the circuit breakers are kept in the closed state. 20 µs is the time-step used for thiscase study, i.e., the sampling frequency is 50 kHz, which is much better than the typical20 kHz used in commercial real-time digital power system simulators.

As highlighted in Chapter 3, the power system used as a case study (Figure 6.1) is asingle-phase transmission system, which parameters were summarized in Table 3.3. Asdiscussed in that Chapter, Bergeron model is the distributed parameters transmission linemodel used in this work. Such a model is suitable for validating two-terminal travelingwave-based fault location and protection methods that use aerial mode waves.

Figure 6.1: Power system under study.

CHAPTER 6. RESULTS 104

Figure 6.2 depicts a general comparison (first view) regarding the current and volt-age waveforms obtained from the real-time simulation and the ones obtained from Mat-lab/Simulink. It also provides the error signal illustration, which measures the deviationbetween real-time results and offline simulation used as the benchmark. Figure 6.2-a)and 6.2-b) depicts the currents flowing through the circuit breakers 1 and 2 (Figure 6.1),whereas Figure 6.2-c) and 6.2-d) depicts the voltages at buses 1 and 2, respectively. Thecurrent waveforms generated from the real-time implementation agreed with the ones ob-tained offline in both transient- and steady- states since these signals overlap. This sameconclusion is valid for the voltage signals.

Figures 6.3 and 6.4 depict a zoom in the transient-state of currents and voltages il-lustrated in Figure 6.2. The spikes contained in the error signals during the transientsregime is due to a difference of amplitude in the arrival times of the wavefronts of thetraveling-waves. The cause of such an event is currently under investigation, however,this deviation in the magnitude of the traveling waves is probably because the EMTP al-gorithm considered in this work is implemented in its initial concept, i.e., without the useof additional techniques. Nevertheless, the time instants of the traveling waves, consider-ing all reflected wavefronts, which are requested by traveling wave-based fault locationsand protection, are exactly the same in both simulations.

The simulator lasts 11 µs (execution-time) to complete a cycle of the EMTP-loop, i.e.,to generate a set of output data, which was less than the adopted time-step of 20 µs. Thus,the integration time-step could be reduced to 11 µs to hold the simulation executing inreal-time (time-step ≥ execution-time).

6.2 Device UtilizationTable 6.1 describes the results regarding FPGA utilization. The implemented algo-

rithms to handle the power system simulation requires in percent 97.5 % of the slices,33.8 % slice registers, 84 % slice LUTs, 10% RAM blocks, and 22.3 % DSPs units. Theseresults are due to the level of parallelism adopted during the implementation steps. Theseresults also justify the use of the power system under study. For instance, counting withmore hardware resources a three-phase version of it, as well as the frequency-dependenttransmission line model, could be used in the real-time implementation. Thus, the simu-lator scalability can be achieved using another piece of hardware. Although those percentdata illustrate the high level of hardware utilization, actually, the number of logical re-sources, as well as the number of DSP and RAM blocks, of the used FPGA is limited ifcompared with the capabilities of modern FPGAs.

Table 6.1: Device Utilization.

FPGA Utilization Used Total PercentTotal Slices 12963 13300 97.5 %

Slice Registers 35989 106400 33.8%Slice LUTs 44676 53200 84 %

Block RAMs 14 140 10 %DSP48s 49 220 22.3 %


Figure 6.2: General results obtained from the real-time simulator and the ones obtainedfrom Matlab/Simulink. a) current at CB1. b) current at CB2. c) voltage at bus 1. d)voltage at bus 2.


Figure 6.3: A closer view of the results generated using the real-time simulator and theones obtained from Matlab/Simulink. a) current at CB1. b) current at CB2. c) voltage atbus 1. d) voltage at bus 2.


Figure 6.4: A closer view of the results generated using the real-time simulator and theones obtained from Matlab/Simulink. a) current at CB1. b) current at CB2. c) voltage atbus 1. d) voltage at bus 2.


6.3 Validation of the Real-Time Simulation with a Traveling-Wave-Based Transmission-lines Relay

The hardware-in-the-loop simulation is achieved by placing the relay prototype andthe simulated power system in a closed-loop. This configuration is tested considering fourcase study, where each one is related to a fault taking place the transmission line in theprotected, uncertainty, and unprotected zones.

The purposes related to this study is to evaluate the application of the real-time simu-lation platform to test, using a hardware-in-the-loop configuration, traveling-wave basedprotection systems. To accomplish this, a two-terminal traveling wave-based transmissionline method, which was proposed and widely validated in [Costa et al. 2017], is used as areference. Studies regarding the effect of the fault inception angle, fault resistance, errorsrelated to the traveling wave velocity estimation, and others of the sort are not consideredsince it already accomplished in [Costa et al. 2017]. Therefore, the hardware-in-the-loopconfiguration validation is tested for the case studies aforementioned.

6.3.1 Protection SettingsThe relay sampling frequency ( fs) is set up to 50 kHz. Considering a transmission

line with 400 km (d) and the light-velocity (c) 300000 km/s, the two-terminal travelingwave-based protection equation is in the form of [Costa et al. 2017]

|kF1− kF2|< bd fs/cc, (6.1)

which yields

|kF1− kF2|< 66, (6.2)

i.e., considering this case study, the traveling-wave unit trips when the difference of sam-ples related to the arrival time of the first wavefront at line terminals is less than 66. kF1is the sample in which the relay at bus 1 detects the arrival time of the first wavefront,whereas kF2 is the sample in which the remote relay detects the arrival time of the firstwavefront.

As described in Chapter 4, the samples related to the arrival time of the first wavefrontat the line terminals (kF1 and kF2) are determined based on the detection method. Waveletcoefficients, which were calculated using (4.19), are used to determine the arrival of atraveling-wave at the monitoring buses. Reference [Costa 2014] delimited a containmentregion of those for the steady-state condition, which is defined by

[W1,W2] = µw−4δw,µw +4δw, (6.3)

where W1,W2 are the steady-state thresholds, whereas µw, δw are the mean and standarddeviation of the coefficients wavelet, which are calculated in this work considering tencycles of the voltage signal in the steady-state, i.e., when a traveling wave arrives at thetransmission line terminals the detection method wavelet coefficients start to be out of therange delimited for those thresholds.


The equations concerning the protected, uncertainty and unprotected zones for thetwo-terminal traveling wave-based transmission line protection were presented in Chapter4. Using the capacitance (c = 7.9714e−9 F/km) and inductance (l = 0.0021 H/km) perunit of length parameters employed in the transmission line model, as well as the relaysampling frequency fs and line length d, in (4.15), (4.16), and (4.17) yields PZ = 79.43%,UZ = 1.22% and UPZ = 19.35%. Figure 6.5 depicts these zones for the case under study.Therefore, if the real-time simulation is correct,the implemented traveling-wave-basedrelays (TWbR) must trip for faults taking place in the assigned 318 km, may trip or notfor faults occurring in the sections of 2 km and must not trip for faults taking place in theassigned sections of 39 km.

Figure 6.5: Protected, uncertainty and unprotected zones.

A communication equipment delay (τCE), which is the required time for such equip-ment sending information from the remote relay and provide information to local relay, isconsidered being 0.712 ms ([Costa et al. 2017]). The communication channel propagationdelay (τCC) is accounted using τCC = d/(0.6414c). These delays are taken into accountin the relay implementation using a counter after the relays trip. The data are consideredsynchronized once the objective here is not to evaluate the presented traveling wave-basedprotection, which was validated in [Costa et al. 2017].

As illustrated further in the voltage signals at the relay input as well as the com-puted wavelet coefficients, the simulation signals evaluated in real-time by the relay pro-totype contains naturally a noise related to the physical connection established betweenthe FPGA and DSP.

6.3.2 Case 1: Fault Far 150 km from Bus 1The first test case concerns a fault taking place on the transmission line far 150 km

from bus 1 with 0.1 Ω resistance and 90° fault inception angle. Such a fault condition wasset up to simplify the wavefronts detection of the traveling waves since additional circuitsto handle the noise level contained in the input signal of the relay prototypes (DSP inputlines) were not considered. A lower SNR level (signal-noise ratio) can mask the travelingwave detection once this ration affects the wavelet coefficients calculation. As illustratedin Figure 6.5, the fault occurs inside the protected zone. Thus the traveling-wave-basedrelays shall clear this fault sending the trip commands to FPGA. The simulation shallrecognize such trip signals, and opens the circuit breakers two cycles after the trip andwhen the current waveforms cross the zero in order to emulate the mechanical time delayof the circuit breakers.


Figure 6.6 depicts the results obtained from the implemented real-time platform. Thevoltages related to the buses 1 and 2 of the simulated power system are the informationsent from FPGA to DSP chip. Figure 6.6-a) depicts these waveforms, which are recordedautomatically using an oscilloscope. This illustration lists a set of events occurring ina time-window considering a scale of ms. The first event concerns the fault inceptiontime at the fault point. As illustrated in Figure 6.6-c), a fault takes place on the trans-mission line at 100.66 ms (kF = 5033). The second and third event concern wavefrontsdetection. As illustrated in Figure 6.6-b), the relay 1 detects the arrival time of the firstwavefront at 101.28 ms (kF1 = 5064), whereas the relay 2 detects the arrival time of thefirst wavefront at 101.68 ms (kF2 = 5084). During steady-state, the wavelet coefficientsfall below thresholds calculated using (6.3). The value assumed by those in the steady-state is related to the level of noise contained in the voltage signals, which are used asinput information for the traveling wave-based relays. When the first wavefront arrivesat the transmission line terminals, the amplitude wavelet coefficients exceeds the detec-tion thresholds [Costa 2014], i.e., the fault is easily detected. The fourth and fifth eventsconcern the trip commands issued by the traveling wave-based relays. As illustrated inFigure 6.6-c), relay 1 sends a trip command to its related circuit breaker at 102.42 ms(sample 5121), whereas relay 2 issues a command trip at 102.04 ms (sample 5102). Thus,considering the fault inception time (6.6-c)) and added delays (regarding the communica-tion equipment and communication channel) the relays 1 and 2 last respectively 1.76 msand 1.38 ms to provide the trip signals to its related circuit breakers, which is a very fastprotection operation in a transmission line of 400 km if compared to conventional lineprotection which takes about one cycle (20 ms) to operate. The sixth and seventh eventsconcern the circuit breaker operation delay. This work considers a delay of 2 cycles forsuch elements as aforementioned. In addition, the simulation waits for the current crosseszero to perform the opening operation. As illustrated in Figure 6.6-d), the fault is cleared501.12 ms (48.74 ms + 1.38 ms) after the fault occurrence.

The hardware-in-the-loop as well as the performance of the traveling wave-based relayare is validated using the two-terminal traveling wave-based fault location formula, whichis in the form of [Lopes et al. 2018]

dF = 0.5[d +(tF1− tF2)v], (6.4)

where dF , d, tF1, tF2, and v are the fault distance, transmission line length, arrival time ofthe first wavefront at the bus 1 and 2, the traveling-wave velocity.

Considering the traveling-wave velocity for a lossless transmission line (vt = 1/√

lc),the fault location is estimated at 151.1175 km, which is a value close to the real faultlocation of 150 km. The fault location estimation in 151.1175 km is quite acceptableand validates the results since two-terminal traveling wave-based fault location presentsan error up to vt / fs = 4.8882 km due to the effects of the sampling frequency [Costaet al. 2017].


Figure 6.6: Results obtained from the implemented hardware-in-the-loop setup consider-ing a fault taking place the transmission line far 150 km from bus 1.

6.3.3 Case 2: Fault Far 41 km from Bus 1The second test case concerns a fault taking place on the transmission line far 41 km

from bus 1 with 0.1 Ω resistance and 90° fault angle. As illustrated in Figure 6.5, thisfault occurs inside the uncertainty zone, and the relay can or cannot trip in this case asaddressed in [Costa et al. 2017]. If the traveling wave-based protection did not trip, otherprotection functions would trip in a practical application.


Figure 6.7 depicts the results obtained from the implemented real-time platform. Fig-ure 6.7-a) depicts the voltages related to buses 1 and 2 of the simulated power system.This illustration lists a set of events occurring in a time-window considering a scale ofms. The first event concerns the fault instant. As illustrated in Figure 6.7-c), a fault takesplace the transmission line at 100.20 ms (kF = 5010). The second and third event concernwavefronts detection. As illustrated in Figure 6.7-b), the relay 1 detect the arrival time ofthe first wavefront at 100.36 ms (kF1 = 5018), whereas the relay 2 detects the arrival timeof the first wavefront at 101.66 ms (kF2 = 5083). The fourth and fifth events concern thetrip commands issued by the traveling wave-based relays. As illustrated in Figure 6.7-c),relay 1 sends a trip command to its related circuit breaker at 102.42 ms (sample 5121),whereas relay 2 issues a command trip at 101.70 ms (sample 5085). Thus, consideringthe fault inception time (6.7-c)) and added delays (regarding the communication equip-ment and communication channel) the relays 1 and 2 last respectively 2.22 ms and 1.5ms to provide the trip signals to its related circuit breakers. The sixth and seventh eventsconcern the circuit breaker operation. As illustrated in Figure 6.7-d), the fault is cleared50.06 ms (48.56 ms + 1.50 ms) after the fault occurrence.

Considering the traveling-wave velocity for a lossless transmission line, the locationformula returns a fault located at 41.1320 km which is a value close to 41 km.

6.3.4 Case 3: Fault Far 40 km from Bus 1The third test case concerns a fault taking place on the transmission line far 40 km

from bus 1 with 0.1 Ω resistance and 90° fault angle. As illustrated in Figure 6.5, thisfault also occurs inside the uncertainty zone, where the protection can or cannot trip.

Figure 6.8 depicts the results obtained from the implemented real-time platform. Fig-ure 6.8-a) depicts the voltages related to buses 1 and 2 of the simulated power system.This illustration lists a set of events occurring in a time-window considering a scale ofms. The first event concerns the fault instant. As illustrated in Figure 6.8-c), a fault takesplace the transmission line at 97.96 ms (kF = 4898). The second and third event concernwavefronts detection. As illustrated in Figure 6.8-b), the relay 1 detect the arrival timeof the first wavefront at 98.12 ms (kF1 = 4906), whereas the relay 2 detects the arrivaltime of the first wavefront at 99.44 ms (kF2 = 4972). As illustrated in Figure 6.8-c), therelays provide no trip command to the circuit breakers, even though the detection methoddetects the traveling-wave arrival time (6.8-b)). This result is in accordance with the pro-tection settings since the fault occurs inside the uncertainty zone. As illustrated earlier,the implemented traveling-wave unit is defined for the condition |kF1− kF2|< 66. In thiscase |kF1− kF2| = 66. As illustrated in Figure 6.8-d), the fault is not cleared since thecircuit breaker did nor receive any command signal from the relays.

Considering the traveling-wave velocity for a lossless transmission line, the locationformula returns a fault located at 38.6879 km which is a value around the actual value of40 km.



6.3.5 Case 4: Fault Far 20 km from Bus 1The fourth test case concerns a fault taking place on the transmission line far 20 km

from bus 1 with 0.1 Ω resistance and 90° fault angle. As illustrated in Figure 6.5, thisfault also occurs inside the unprotected zone.


Figure 6.9 depicts the results obtained from the implemented real-time platform. Fig-ure 6.9-a) depicts the voltages related to buses 1 and 2 of the simulated power system.This illustration lists a set of events occurring in a time-window considering a scale ofms. The first event concerns the fault instant. As illustrated in Figure 6.9-c), a fault takesplace the transmission line at 97.72 ms (kF = 4886). The second and third event concernthe wavefronts detection. As illustrated in Figure 6.9-b), the relay 1 detects the arrivaltime of the first wavefront at 97.80 ms (kF1 = 4890), whereas the relay 2 detects the ar-rival time of the first wavefront at 99.28 ms (kF2 = 4964). As illustrated in Figure 6.9-c),the relays provide no trip command to the circuit breakers, even though the detectionmethod detects the traveling-wave arrival time (6.9-b)). This result is in accordance withthe protection settings since the fault occurs inside the unprotected zone. As illustratedearlier, the implemented traveling-wave unit is defined for the condition |kF1−kF2|< 66.In this case |kF1− kF2|= 74. As illustrated in Figure 6.9-d), the fault is not cleared sincethe circuit breaker did nor receive any command signal from the relays.

Considering the traveling-wave velocity for a lossless transmission line, the locationformula returns a fault located at 19.1349 km which is a value close to 20 km.

6.4 SummaryThis chapter provided the results regarding the implemented real-time simulator. This

implementation was validated comparing the real-time results with the ones obtained fromSimulink/Matlab as the benchmark. As illustrated, the simulation results have agreedsboth in steady-state and transient regime. This chapter also provided information regard-ing the hardware utilization. The scalability of the presented platform can be achievedusing another hardware device. The hardware-in-the-loop was validated using a two-terminal traveling wave-based transmission line protection as a reference and a fault lo-cation method. The presented tool can work with a two-terminal traveling wave-basedtransmission line relay. Furthermore, it has the potential for developing and evaluation ofnew protection functions, especially when the hardware capability is increases and three-phase transmission lines, TC, and TP models were included in the real-time platform.

Chapter 7

Conclusion

7.1 General ConclusionsThis dissertation has presented the development of a real-time simulation platform

suitable to perform hardware-in-the-loop tests such as the ones for validating traveling-wave-based transmission-line relays. One of the main advantages of this work concernthe range of information covered in a unique document. Initially, it provides both a reviewand state-of-the-art regarding the power system real-time simulation. Then, it introducesthe fundamental models used in EMTP-type programs as well as the necessary steps forgenerating the power system simulation. This theory is presented based on illustrationsobtained from an offline simulation platform. It also addressed the internal structure ofdigital relays as well as an approach regarding the traveling-waves-based transmission-line relays. Such a presentation was supported by means of offline results. Then, the usedhardware architectures were introduced as well as the physical setup achieved in the real-time implementation. The implementation stages, from the graphical interface until theEMTP-loop programming, were detailed based on a power system used as a case study.Moreover, the chapter provides details regarding the implementation of a traveling-wave-based-relay using DSP-based hardware, and the integration between such a prototype andthe real-time simulation executed in an FPGA-based platform. The real-time simulationswere validated using results obtained from an offline platform. The hardware-in-the-loopconfiguration was validated using the standard performance of such type of protection aswell as using the information of a fault location method.

The validation possibility of traveling wave-based relays is a novelty addressed by thepower system real-time simulators of today, where several FPGAs with strong capacitiesare necessary. However, the developed platform, even with just one FPGA with low ca-pacity, could properly perform real-time simulations of a simplified transmission systemwith hardware-in-the-loop connections with traveling wave-based relays. A sampling fre-quency of 50 kHz could be used, which is higher than the sampling frequency of 20 kHzof most commercial real-time power system simulators.

CHAPTER 7. CONCLUSION 118

7.2 Future WorksAs a continuation of the studies accomplished in this master’s dissertation, the follow-

ing future work proposals are suggested:

• Investigation of the cause of the spikes contained in the error signal obtained bycomparing the real-time and offline results in the arrival time of the traveling waves(Chapter 6).

• To verify closely if the implementations could be made more efficiently in orderto increase simulator scalability adding new models without the need to expandcurrent hardware resources. Otherwise, increase the hardware capability of thecurrent real-time setup.

• Perform the simulation of power systems also comprised of non-linear elements.• Add the frequency-dependent transmission-line model into the implemented real-

time platform.• Include the CT and PT models into the real-time implementation.• Add a real communication system (hardware), develop an emulator of the commu-

nication channel as well as of the synchronization systems.

7.2.1 PublicationsAt this moment, this work resulted in the following papers:

Table 7.1: Publications.

Event Title Authors

3rd Workshop on Communi-cation Networks and PowerSystems (WCNPS), 2018Brasília

Methodology to PerformReal-Time Simulation ofPower Systems Using aFPGA-based Platform

M. S. R. Leal, L. D. Simões,F. B. Costa, R. L. S. França,M. M. leal, F. E. Taveiros.

VII Simpósio Brasileiro deSistemas Elétricos (SBSE),2018 Niterói

Graphical Interface to Aid inDevelopment of Travelling-Wave-Based Line Protectionand Fault Location Tech-niques

S. S. B. Azevedo, F. B.Costa, M. S. R. Leal, R. L.S. Franca

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