Development of Baseline Lead-free Rework and Assembly Processes forLarge Printed Circuit Assemblies

Patrick Roubaud1, Jerry Gleason2, Charlie Reynolds3, Ken Lyjak4, Matt Kelly5, Jasbir Bath6

1Hewlett Packard, Grenoble, France2Hewlett Packard, Palo Alto, California USA

3IBM, East-Fishkill, New York USA4IBM, Research Triangle Park, North Carolina USA

5Celestica Inc., Toronto, Canada6Solectron , Milpitas, California USA

AbstractA cross-company workgroup was formed to develop a baseline lead-free manufacturing process using the NEMI tin-Silver-Copper (Sn3.9Ag0.6Cu) alloy for medium to high-end computer products. The primary attachment assemblyand rework processes investigated by this group are illustrated in this paper along with a presentation of thereliability qualification test plan.

IntroductionIn 1999 the prospective of a legal ban on lead inelectronic goods prompted the National ElectronicManufacturing Initiative (NEMI) to recommend thelead-free alloy Sn3.9Ag0.6Cu as the best availableoption for surface-mount reflow applications [1].Several NEMI projects were launched to help developthe capability to manufacture lead-free Printed CircuitAssemblies (PCAs) [2].

Those studies brought a good level of confidenceregarding the reliability of the lead-free solder jointsformed with surface mount and wave solderingtechnologies. However the rework operations stillrepresent a major technical difficulty [3] because ofthe relatively high temperature applied to the printedcircuit boards and the components. This issue is evenmore critical when working with relatively thickboards and multiple thermal excursions.

A trans-company NEMI workgroup was created tocontinue to develop and verify a baseline reworkprocess for large and thick lead-free PCAs which arecharacterized by components with a wide range ofthermal masses on large high thermal masse cards.The workgroup is formed by 19 companies of theelectronic industry and 1 university. The groupstarted activities in 2002.

The overall project was divided in 3 phases. Phases 1and 2, the lead-free assembly and rework processdevelopment studies, were finished toward the end ofQ3 2003. Test boards for the process qualification(phase 3) have been assembled. The acceleratedthermal cycling experiments are in progress at thetime of the publication of this paper.

High Tg Laminate MaterialThe laminate material used for our study is a fairlynew material, designed to sustain the high

temperatures characteristic of the lead-free assemblyand rework operations. It has a glass transitiontemperature (Tg) of 180°C and a decompositiontemperature of 327°C.

It was important to verify as early as possible in thestudy if this new laminate material was compatiblewith the high temperatures imposed by the lead-freeassembly process and the lead-free rework process.The specification is for this material to withstand atleast 6 thermal excursions to 260°C. To answer thisquestion, we thermally stressed 7 test coupons byhaving an electrical current running thought a daisychain. The coupons were 93 mils thick. The resultshowed that this material can resist to more than 6thermal excursions to 260°C. This laminate material(at this time) is therefore believed to be compatiblewith the temperature used by our processes.

Process development and test vehiclesTwo different kinds of boards were used to developand qualify assembly and rework processes. The firstone was used during phases 1 and 2. The second onewas used for the process qualification build (phase 3).Those board designs are based on existing industrialboards used for process development andqualification. They are used to work on thechallenges encountered when dealing with fairly largeand thick boards carrying a variety of componenttypes including SMT and PTH components, bigarray packages, leaded packages, small and largepassives and various kind of connectors. During thecourse of the overall study a total of about 900boards have been built. Table 1 summarizes some oftheir characteristics and a picture of the qualificationboard can be seen in Figure 1.

Figure 1 – Top and bottom sides of the processqualification board.

Table 1 – Some characteristics of the boards usedfor this studyDevelopment

boardQualification

boardThickness 2.3 mm 2.3 and 3.4 mmDimensions 330 x 254 mm 432 x 178 mmNumber ofcopper layers

2 14

Tg 180°C 180°CDecompositiontemperature

327°C 327°C

Surface finish OSP andENIG

Electrolytic Ni-Au and

immersion Ag

Each site of the qualification board has copper tracesthat follow a daisy chain pattern to enable electricalcontinuity inspection when daisy chainedcomponents are used.

Assembly process (phase 1)Both Surface Mount Technology (SMT) and wavesoldering processes were investigated by the NEMIworkgroup.

SMT ProcessThe SMT process was developed with the mainobjective to determine the process window for thereflow temperature that yields acceptable lead-freejoint formation. A constraint the group gave to itselfwas to use in-line processing configurations andprocess time windows compatible with industrialthroughputs. An additional goal was to minimize thetemperature gradient across the second level assemblyduring the SMT reflow process. As with previouswork [4], component temperatures (body and joint),along with temperature gradient information werecommunicated to JEDEC to assist in updating thespecification J-STD-02B. The process was finalizedat manufacturing locations to ensure that a robust

assembly process has been achieved before the buildof the test boards.

The lead-free SMT process developed gave a yieldclose to 95% which was comparable with the yieldobtained with the Sn-Pb paste. The peak temperatureswere recorded at 248ºC for the 3.4 mm thick boardsand 243ºC for the 2.3 mm thick board. Forcomparison, the peak temperatures recorded for theSn-Pb process were 210 and 211ºC respectively. Thetemperature gradient across the board was 14ºC andmost of it was due to the presence of ceramicpackages.The biggest challenge was to minimize thetemperature gradient across the board while keepingthe process time at a reasonable level. For the lead-free 3.4 mm thick board, the time above liquidus wasbetween 90 and 120 seconds. The overall cycle timewas 8 minutes. The thermal profile can be seen onFigure 2.

Figure 2 – SMT thermal profile, Qualificationboard, 3.4 mm thick, top side, lead-free.

Wave soldering processGiven the small amount of data available regardingthe lead-free wave soldering process, gainingknowledge on the process fundamentals was theprimary focus here. Both conventional and selectivewave soldering processes were investigated. Theobjectives were to define and optimize the processwindow by determining acceptable temperature rangesfor the lead-free wave solder process. As with theSMT process, the impact of differences betweensurface finish and board thickness were quantified.

The defects recorded on PTH components by visualinspection were:- solder skips- Insufficient solder- solder bridging- lifted connectors

Rework Process (phase 2)The rework process was performed at productionsites, using production rework tools.

Reworking large lead-free BGAs on thick boards isdifficult because of the high temperatures involved.The solder joint time over reflow (217°C) must bebetween 45 and 90 seconds. Practically, we found anecessity to have a minimum solder joint temperatureof 230-235°C to ensure good wetting. The current J-STD-020B standard is calling for a maximum bodytemperature of 245-250°C for the larger components.The margin of error to maintain a lead-free minimumsolder joint temperature of 230-235°C with a bodytemperature of 245-250°C is very tight. Forcomparison, when using the Sn-Pb paste the thermalwindow is two times larger with a temperaturehaving to be somewhere between 200 and 240°C.

It was found that increasing the bottom side boardpreheat was effective in reducing the temperaturegradient between the solder joint and the componentbody. Figure 3 shows a schematic of the apparatusused. The thermal profile used for the CBGA ispresented in Figure 4. Figure 5 illustrates CBGAsolder joints after the rework operation.

Figure 3 - Rework setup used to minimize thetemperature gradient between the solder joint andcomponent body. Courtesy: Gowda et al. (SUNY-

Binghamton, Universal Instruments) [3]

Figure 4 – Thermal profile for the rework of thelead-free CBGA on a 3.4 mm thick board. Time

above liquidus: 66 seconds. Solder jointtemperature: 235°C. Top of the package

temperature: 238°C

Figures 5 – PBGA solder joints after rework. Topview: Sn-Pb solder joints. Bottom view: Sn-Ag-Cu

solder joints.

Another difficulty was the excessive temperaturereached by components adjacent to the rework area. Insome cases it was not possible to avoid a partialreflow of some adjacent solder joints. For example, itwas noticed that a CBGA seems to undergo partialdouble reflow during the rework of an adjacent micro-BGA. As one can see on Table 2, the issue of highadjacent temperatures is more acute with the lead-freerework process and with the thicker boards. Theimpact on the reliability will be evaluated andpresented in a future paper.

Table 2 – recorded rework cycle length andtemperatures for the 544 PBGA

Sn-Pb2.3mm

Sn-Pb3.4mm

Pb-free2.3 mm

Pb-free3.4 mm

Thermalprofile timelength

340 sec 360 sec 432 sec 468 sec

Minimumpeak solderjointtemperature

202ºC 201ºC 234ºC 233ºC

Componenttoptemperature

217ºC 217ºC 245ºC 245ºC

Adjacent Component

Nozzle

Pick-upTool

Bottom Heater

Air Flow

ThermocoupleLocations

PCB

Temperatureat 3.8 mmfrom thePBGA

217ºC 227ºC 217ºC 227ºC

Reliability qualification phase (phase 3)The goal of the qualification phase is to evaluate theimpact of:- the solder paste alloy (Sn-Pb or Sn-Ag-Cu),- the rework operation,- the PCB thickness,- the nature of the PCB surface finish,on the reliability of the solder joints.

The reliability evaluation phase is organized around 2tests: an accelerated thermal test (ATC) and amechanical bend test. The ATC was selected becauseit is a test widely used among the industry tocharacterize the solder joint resistance to thermalfatigue. In addition some ATC studies [5] [6] [7] onlarge lead-free array packages similar to ours alreadyhave been published and provide comparison points.The bend test enables a qualitative comparison of themechanical resistance of the lead-free and tin-leadBGA packages. It was selected over other mechanicaltests because some experience was already gathered inthe previous NEMI lead-free study.100 test boards were assembled for the reliabilityexperiments. Three parameters were varied in thesetest vehicles:- Solder paste alloy (Sn-Ag-Cu and Sn-Pb).- Thickness of the PCB: 2.3 mm or 3.4 mm.- PCB surface finishes: electrolytic Ni-Au orimmersion Ag.

50 boards were sent thought the rework process. Acertain number of boards were cross-sectioned toassess the microstructure of the joints and theremainder was sorted between the ATC and the bendtest experiments. The Table 3 shows the dispositionsof the boards between the various cells.

The test board is carrying a number of differentcomponents; for this study the team elected to focuson the components listed in Table 4.The main goal is to cover a broad variety of solderjoints (balls, leads, through-hole pins). Another goalis to include large array packages as they are oftenfound on this kind of board and are challenging toassemble and to rework.

Table 3 – disposition of the 100 test boardsAs

assembledReworked Total

Micrographicstudy

10 10 20

ATC 28 28 56Bend test 12 12 24

Total 50 50 100

Table 4 – Components selected for the reliabilitystudy

Component CharacteristicCBGA 32.5 x 32.5 mm , 937 I/O ,

1 mm pitchTSOP 48 I/O

Micro BGA 17 x 17 mm , 256 I/O , 1mm pitch

PBGA 35 x 35 mm , 544 I/O , 1.27mm pitch

DIP 16 I/O2512 resistor

DIMM Connector 278 pins , 1 mm pitch

ATCThe ATC experiment is following the JEDECJESD22-A104B recommendations. As shown inFigure 6, the actual thermal profile maximum andminimum temperatures were recorded at 104ºC and -6ºC. Each cycle is 42 minutes long.

Figure 6 - ATC thermal profile for the testchamber carrying the “as-assembled” boards

The 56 test boards are divided in 10 cells. The Table5 shows the various cells parameters.

Table 5 – Design of the ATC experimentCell Paste Thickness

(mm)Rework Surface

finish# of

boards1 Sn-Pb 3.4 No Ni-Au 4

2 Sn-Pb 3.4 Yes Ni-Au 4

3 Sn-Pb 2.3 No Ni-Au 4

4 Sn-Pb 2.3 Yes Ni-Au 4

5 SAC 3.4 No Ni-Au 8

6 SAC 3.4 Yes Ni-Au 8

7 SAC 2.3 No Ni-Au 8

8 SAC 2.3 Yes Ni-Au 8

9 SAC 2.3 No Imm-Ag 4

10 SAC 2.3 Yes Imm-Ag 4

Total 56

Two Thermotron thermal chambers with 1 cubicmeter capacity and equipped with HP data acquisitionsystems were used for the ATC experiment. The firstchamber is for the “as assembled” condition and thesecond one for the “after rework” condition. Picturesof a chamber can be seen in Figure 7. At the time ofthe writing of this paper, the tests are on-going andwill be stopped after 6000 cycles. As of early May2004, the “as assembled” boards have been cycled

Time(Minutes)

Temperature(Degree Celsius)

42

104

- 6

4500 times and the “after rework” ones have beencycled 2000 times.

Figure 7 – ATC experimental setting. Top view: thetwo thermal chamber used for the experiment.

Bottom view: inside one of the chambers. A total of952 (2 x 476) components were individually

monitored.

The component types monitored are the CBGA 937,the PBGA 544, the micro BGA 256, the TSOP 48and the DIP 16. In total, the electrical resistances of952 components are individually and continuouslymonitored by the data acquisition systems. After thecompletion of the 6000 cycles, the boards will bepulled out of the chamber and the components willbe cross-sectioned to assess the failure modes.

There are different criteria one can use to declare acomponent as failed. As fatigue cracks propagatethrough a solder joint, the electrical resistance of thejoint will increase. Eventually the crack will go allthe way through and the electrical connection will becut out.A component can be declared “failed” as soon as theelectrical resistance starts to increase or when theopen occurs or following another criterion forexample a 50% increase of the electrical resistance. Inthe first case, N1 will be recorded as the number ofcycles to failure (see Figure 8) and N2 will berecorded if the “first open” criteria is elected. Wefound that this choice can have a significant impact

on the results. For example, for the CBGAcomponent (as assembled condition) N2 is on average110% the value of N1 if assembled with Sn-Pbsolder paste but 130% if assembled with lead-freesolder paste. So if N2 is selected, the relativeperformance of the CBGA assembled with lead-freepaste will appear to be better than if N1 is selected.More investigations will be carried to determine ifthis effect can be generalized to other components.

Number of cycles

First open

Slope Change

Electrical resistance

N1 N2Number of cycles

First open

Slope Change

Electrical resistance

N1 N2

Figure 8 – evolution of the electrical resistanceversus the number of cycles. Depending on the

criteria chosen (“slope change” or” first open”),the number of cycles to failure will vary.

Bend TestThe aim of the bend test is to compare themechanical resistance of the solder joints for theCBGA and the PBGA components. We want tocompare the components assembled using the lead-free paste against the one assembled with Sn-Pb andthe reworked components against the as assembled.The design of this experiment is provided in Table 6.

Table 6 – Design of the bend test experimentCell Paste Thickness

(mm)Rework Surface

finish# of

boards1 Sn-Pb 3.4 No Ni-Au 3

2 Sn-Pb 3.4 Yes Ni-Au 3

3 Sn-Pb 2.3 No Ni-Au 3

4 Sn-Pb 2.3 Yes Ni-Au 3

5 SAC 3.4 No Ni-Au 3

6 SAC 3.4 Yes Ni-Au 3

7 SAC 2.3 No Ni-Au 3

8 SAC 2.3 Yes Ni-Au 3

Total 24

A schematic of the bend test experiment is shown inFigure 9. The PCB is cut around the PBGA and theCBGA to make the test coupon. Surrounding partsaround those components will be mechanically

removed for the bend test machine to have a safe gripon the coupon.

Figure 9 – Schematic of the bend test experiment

A 4-point bend test was preferred to a 3-point bendtest in order to have a constant curvature radius acrossthe length of the test coupon and a uniform load onthe tested component. The experiment will be run atroom temperature. As of early May 2004, the bendtest experiment is on-going.

ConclusionAn assembly and rework process for medium to high-end lead-free computer products has been developedby a cross-company NEMI workgroup. Close to 900PCAs have been assembled, including 100qualification boards, using existing industrialequipment and procedures. The temperatures rangesrequested by the JEDEC J-STD-02B standard wererespected.The initial lead-free SMT process gave acceptableyields but more development needs to be done for thewave solder process.During the rework development it was found thatincreasing the bottom side board preheat was helpfulin keeping the temperature gradients under controlduring the rework operations. The many challengesthat face lead-free rework include process tool thermalstability and operational capability. Much learning isstill required to improve the manufacturability andreduce the cost associated with inspection and yieldloss.The NEMI workgroup is now conducting a reliabilityqualification experiment with the aim to quantify theimpact of the solder type, the rework, the boardthickness and the board surface finish. As of earlyMay 2004, 952 components are currently tested forthermal fatigue resistance as part of thisinvestigation. A study on the mechanical resistanceof large CBGA and PBGA is underway.

AcknowledgmentsThe authors would like to gratefully thank all theparticipants of the NEMI lead-free assembly andrework project. The authors wish to acknowledge themanagement support provided by Agilent, Celestica,ChipPAC, Cisco, CMAP, Cookson, Dell, Delphi,EIT, HP, IBM, Intel, Jabil, Lace, Nortel, Sanmina-SCI, Solectron, Teradyne, T.I. and Vitronics-Soltec.

References

[1] “Research update: Lead-Free Solder Alternatives”,Jasbir Bath , Carol Handwerker , Edwin Bradley,Circuit Assembly, May 2000, pp 31-40

[2] “Are Lead-Free Solder Joints Reliable?”, John E.Sohn, Circuit Assembly, June 2002, pp32-35

[3] “Lead-free rework process for chip scalepackages”, A. Gowda, K. Srihari, A. Primavera,Advanced Packaging Technologies in the ElectronicsIndustry Conference, Boston, Massachusetts, June2001, pp.99-106

[4] “Component Temperature Study On Tin-Lead andLead-Free Assemblies”, Matthew Kelly, DuilioColnago, Vittorio Sirtori, Jasbir Bath, Suan KeeTan, Lai Hook Teo, Curtis Grosskopf, Ken Lykak,Charles Ravenelle, Eddie Kobeda, SMTAI 2002

[5] “Board level reliability of lead free packages”,Swaminath Prasad , Flynn Carson , G.S. Kim , J.S.Lee , Patrick Roubaud , Gregory Henshall , Robertherber , Ronald Bullwith, SMTAI sept 26-28 2000Chicago

[6] “Thermomechanical Fatigue Behavior of SelectedLead-Free Solders”, James Bartelo et al, APEX 2001,LF2-1

[7] “Thermo-Mechanical Fatigue Reliability of Lead-free Ceramic Ball Grid Arrays: Experimental Dataand Lifetime Prediction Modeling.”, Mukta Farooq ,Lewis Goldman , Gregory Martin , CharlesGoldsmith , Christian Bergeron, ECTC May 2003New Orleans, pp 827-833

Total Load

Deflection

Monitoring