development of novel r/o electronics for lar detectors 6.10.2006 max hess controller adc data...
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![Page 1: Development of novel R/O electronics for LAr detectors 6.10.2006 Max Hess Controller ADC Data Reduction Ethernet 10/100Mbit Host Detector typical block](https://reader036.vdocuments.net/reader036/viewer/2022062715/56649d775503460f94a59ee7/html5/thumbnails/1.jpg)
Development of novel R/O electronics for LAr detectors
6.10.2006 Max Hess
ControllerADCData
Reduction
Ethernet 10/100Mbit
HostDetector
typical block diagram for R/O electronics
Amplifier
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Preamplifier for Dark Matter Experiment (ETHZ)
Detector: 2 stages LEM ( Large Electron Multiplier )
LEM Gain = 100 / stage
1 electron produce a Q nom = 104 1.6 10-19 C = 1.6 fC
Gain = 40 mV / fC
Charge amplifier
4 FET‘s in parallel
Shaper
VADC
ADC
CF = 1 pF
CD
RD
RI
+-CI
RF = 470 MRD CD = 1.8 s
RI CI = 0.6 s Noise = 2.1 mV rms
VADC input signal: 200 nA 50 ns = 10 fC
6.10.2006 Max Hess
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Argon Tube
Signal pulse width & charge in one pad in function from the trace angle
p = 10 mm
trace
d
pad
s
pulse width: tp = d / vdrift = p / (vdrift cot )
signal charge: QS = Qnom p s = Qnom p / cos
vdrift
signal current: IS = QS / tp
Pad dimensions: 10 mm x 10 mm
vdrift = 2 mm/µs @ Edrift = 1 kV/cm
LEM Gain = 100
1 MIP produces 6000 e- /mm in LAr
Qnom = 100 6000 1.6 10-19 C = 100 fC/mm
6.10.2006 Max Hess
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Values for simulation
d
[mm]
s
[mm]tp
[s]
QS
[pC]
IS
[nA]
* 0° 0 10.0 50•10- 3 1.00 20•103
30° 5.7 11.5 2.85 1.15 403
45° 10.0 14.1 5.00 1.41 282
60° 17.3 20.0 8.65 2.00 231
89° 600.0 600.1 300.00 60.01 200
* theoretical: tp 0 and IS ∞
p = 10 mm
trace
d
pad
s
vdrift
6.10.2006 Max Hess
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Preamplifier for Argon Tube
Transimpedance Amplifier
1 FET
Amplifier with lo- and hi-pass filter
VADC
ADC
CF = 0.1pF
CD
RD
RI
+-CI
RF = 1 M
Gain = 5.3 mV / nA
RI CI = 0.7 s
RD CD = 1 ms
Noise = 400 V rms
input signal: 2 uA / 50 ns
input signal: 20 nA / 10 s
VADC
VADC
6.10.2006 Max Hess
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Preamplifier for Argon Tube with Op Amp
Op Amp AD8655
Linear Amplifierwith BW limiting
CF = 2.2pF
C2
R2
R1
+-C1
RF = 330 kR1 C2 = 0.7 s
R2 C2 = 0.7 s
+-
Transimpedance Amplifier
VADC
ADC
Noise = 860 V rms
Gain = 3.5 mV / nA
input signal: 2 uA / 50 ns
input signal: 20 nA / 10 s
VADC
VADC
6.10.2006 Max Hess
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DAQ box
8 front-end boards
19“ case
Block diagram for R/O electronics
Ethernet 10/100Mbit
Host
other DAQ subsystems
Flat cables from detector
shortest possible:- cable capacitance- noise from outside
25
6 c
ha
nn
els
8 Serial linkslength max. 10 meter
Embeded
PCADC Data
Reduction
32 channels
ADC
ADC
MUX
6.10.2006 Max Hess
Clock module
one for all DAQ systemelectrically isolated
System ground inside the detector
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DS92LV16
Front-end board
ADC 1 SHIFT REG
REG
MUX
12
1 SHIFT REG
REG
Preamplifier modulesinterchangeable for LArDM, ArgonTube, etc.
CODER SERIALIZER16
DE-SERIALIZER
CONTROL LOGIC
rclk: 2
sclk
CS* (16)
CODER: create DC-balanced signal code ( 3 4B5B-code)
MUX: 32 ADC channels + 1 channel for status
(12)
to DAQ
from DAQ
720 Mb/s
electrically isolated
CS*: ADC conversion start (1MS/s)
sclk: sample clock = 20 MHz
rclk: Readout clock = 40 MHz
32 channels
12
12
12
12
FPGAAltera EP1C3T144C8
ADC
6.10.2006 Max Hess
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Front-end board
Ethernet connectorserial link to DAQ board
32 ADC‘sADC121S101
Resolution: 12 bit
Sample rate: 1 MS/s
Full scale: 3.2 V
2 amplifier / print
100 mm
input connector for 32 channels(68 pole flat cable)
Serializer/DeserializerNS DS92LV16
MultiplexerFPGA AlteraEP1C3T144C8
6.10.2006 Max Hess
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Front-end case
input connector
for 32 channels(68 pole flat cable)
8 Front-End modules
= 256 channels / case
3 HE = 133 mm
6.10.2006 Max Hess
Ethernet connectorserial link to DAQ board
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DS92LV16
Data reduction
EXTERNALCLOCK
MODULE
one for all DAQ system
INPUTFIFO
rclk: Readout clock = 2 x ADC clock
CS*: ADC conversion start
DE-SERIALIZER
16
SERIALIZER
rclk
CS*
circular buffer logicfor input memory
signal comparator
data reduction logicfrom input memory to output FIFO
watch for time stamp generation
to Front-end
from Front-end
720 Mb/s
rclk
INPUTMEMORY
OUTPUTFIFO
ext. trigger in
signal detect out
FPGA
watch clock
16 16
slow control
BUS to Embeded PC and other data reduction boards
6.10.2006 Max Hess
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Block diagram for data reduction (draft)
INPUTBUFFER(SRAM)
DATAREDUCTION
LOGICOUTPUT
FIFO(DRAM)
SIGNAL DET. OUT
1618
DATA16
MEMORYCONTROLLER
addr
INPUTFIFO
WRITEADDRESSCOUNTER
READADDRESSCOUNTER
TRIGGERADDRESS
FIFO
I / OCONTROLLER
MUX
16
: Altera Cyclone FPGA family
with tacc < 12ns it‘s possible to write 32 words and read 48 words in 1µs
DELAYFIFO
A-BA
B
COMP
TRIGGERDELAY
COUNTER
WATCH(resolution 1us)
THRESHOLD
EXTERN TRIGGER INPUT
each channel use 1 circular buffer with 2 sectors = 2 x 4096 x 16 bit total used memory = 4 Mb
CLOCK80 MHz
16
bu
s to
em
be
de
d P
C
fro
m s
eria
l lin
k
to serial link,slow control
6.10.2006 Max Hess
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Organisation of input buffer
pre
tri
gg
er
tim
e
SD
writeaddress pointer
readaddresspointer
SD: signal detectedone independend circular buffer for each channel with two sectors = 2 x 4096 x 16 bit
sector A
sector B
6.10.2006 Max Hess
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Data reduction by frame building
npostnpre
Frame 1
npre
Frame 2
npost
digitalcomparatorthreshold
6.10.2006 Max Hess
t1
registration of possible data during 4095 s = 4095 samples
n samples over threshold
absolute time t2
npostnpre
npre npost
digitalcomparatorthreshold
t3
Frame
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Summary
Ethernet 10/100Mbitdata reduction
Front-end modul
amplifier
ADC
serial link
serial link
6.10.2006 Max Hess
- ASIC Amplifier Higher number of channels per board
Lower power consumption
Lower price per channel up to 100‘000
- The system is adaptable for different event rates, variable number of data reduction boards per embeded PC
Future design:
- ADC with higher sample rate Better time resolution (if needed)
- Optical link Longer possible distance from the detector to the DAQ electronic
Higher bandwidth
- High flexibility for signal conditioning
- Optimized for development time to price per channel (for small systems)
Actual design:
- DAQ Logic Data reduction logic and embeded processor in the same FPGA ( Altera Stratix, Cyclone familly)
DAQ box
embeded PC