Development of Readout ASICDevelopment of Readout ASICfor Pair-monitor with SOIfor Pair-monitor with SOI

Yutaro SatoTohoku Univ.21 Oct. 2009

Pair-monitor is a silicon pixel detectorto measure the beam profile at IP.

• The distribution of the pair B.G. is used.– The same charges with respect to the

oncoming beam are scattered with large angle.– The scattered particles have information on beam shape.

• The location will be in front of the BeamCal.

Pair-monitorPair-monitor2

e-

e+

IP e+ beame- beam

LumiCalBeamCal

Pair-monitor

IP

Distribution of pair B.G.

X [cm]

Y [

cm]

Y [

cm]

X [cm]

1σx (nominal) 2 σx

BeamCal

SOI (Silicon On Insulator) pixel detector• The sensor and electronics are integrated in the SOI substrate.

Monolithic device, high speed, low power, thin device, low material

→ Monolithic device allows the elimination of bump-bonding process.

Development of Pair-monitor with SOI technologyDevelopment of Pair-monitor with SOI technology3

sensor

electronicsSiO2

We started to develop the pair-monitor with SOI technology.As the first step, only the readout electronics was produced.

Pair-monitor• Pixel size : 400 x 400 μm2

• Radius : 10 cm• Total number of pixel : ~200,000

Development of the readout ASICDevelopment of the readout ASICDesign concept of readout ASIC• Pair-monitor measures the hit distribution of the pair B.G..• Measurement is done for 16 parts in one train

for the time-dependent measurement.− 16 hit counts are stored at each part.− Count rate : < 2.5 MHz / (400μm x 400μm)− Information of the energy deposit is not necessary.

• Data is read out during inter-train gaps. ( ~ 200 msec )

4

………………… ……

1 msec 200 msec

[ [ [1 2 16

1 train = 2625 bunches

~~

Beam structure

The prototype readout ASIC was designed to satisfy these concepts.

Design of readout ASIC• 9 (3x3) readout pixels

– Amplifier

– comparator

– 8-bit counter to count the number of hits

– 16 count-registers to store hit counts

• Shift-register to select a pixel from 9 pixels

Design of readout ASICDesign of readout ASIC5

comparatorAmplifier

Input

Readout pixel

Layout of prototype ASIC

8-bit counter

…

Count-register 2Count-register 1

Count-register 16

Output

The prototype of the SOI chip was developed.

Prototype chip• FD-SOI CMOS 0.2 μm process• Chip size : 2.5 x 2.5mm2

• # of pixel : 9 ( = 3x3 )• Only the readout ASIC was fabricated.• Package : QFP80

Prototype of SOI chipPrototype of SOI chip6

The production of the readout ASIC was done in Aug. 2009.

Packaged ASIC

The operation test was performed.

Test system• GNV-250 module was used for the operation and readout .

– KEK-VME 6U module

• The test-sequence by GPIO is controlled by a PC.

Test systemTest system7

Operation signals

GPIOTest-board

Readout ASIC

FIFOFPGA

Hit count

PC

Hit count

Operation Signals

Response of shift-registerResponse of shift-registerThe response of the shift-register was checked.

• The select signal rose at the third clock signal.

8

Clock Sig.

Select Sig.

Gate Sig.Cell

XCK

YC

K

The shift-register works correctly.

SelectedCellSELECT

SEL

EC

T

Response of pre-amplifierResponse of pre-amplifier

The output of the pre-amplifier was checked.

9

Readout pixel

Pre-amp.Shaping-amp.

Comparator8-bit

CounterConunt-

register x16

TP timing

Output from pre-amp.

TP timing

Output from pre-amp.

Feedback capacitance : 0.1 [pF] Feedback capacitance : 0.05 [pF]

The output from pre-amplifier was observed.As expected, the gain was larger for smaller feedback capacitance.

Response of shaping-amplifierResponse of shaping-amplifier

The output of the shaping-amplifier was checked.

10

Readout pixel

Pre-amp.Shaping-amp.

Comparator8-bit

CounterConunt-

register x16

TP timing

Output from shaping-amp.

TP timing

Output from shaping-amp.

Pole-zero cancellation OFF Pole-zero cancellation ON

The pole-zero cancellation works correctly.

Response of counter blockResponse of counter block

The response of the 8-bit counter was checked.

• Gray code is used. two successive values differ

in only one bit.

11

Readout pixel

Pre-amp.Shaping-amp.

Comparator8-bit

CounterConunt-

register x16

TP timing

Q1

Q2

Q3

000001011010110

000001010011100

Gray-codeBinary-code

The counter block works correctly.

Readout of hit counts was checked.• The hit count was stored at 4 MHz hit rate/ (400μm x 400μm)

and read out from the count registers.

Readout of hit countsReadout of hit counts12

# of input TP

@ 4MHz# of

rea

dou

t h

it c

oun

ts

No bit-lost!

Readout pixel

Counter Count-register 1

Amplifier

Count-register 2

Count-register 16

…

Input

The correct hit counts were read out from count-register.

Threshold scan was performed.

• Fit to error function (S-curve)

• Threshold : 6.886 ± 0.009 [mV]

• Noise : 0.7152 ± 0.0128 [mV]

The gain was estimated to convert the noise into equivalent noise electrons.

• Gain : 16.94 [mV/fC]

Noise characteristic (1)Noise characteristic (1)13

Noise

Threshold

Error function

Cou

nt e

ffic

ienc

y

Threshold voltage [mV]

Slope → gain

Injected charge [fC]

Thr

esho

ld [

mV

]

Noise : ~260 electrons

(Injected charge 5.88 [fC])

The noise level was checked as a function of the detector capacitance.

• Each cell have different detector capacitance.

→ The noise level is 250 ~ 700 electrons.

Noise characteristic (2)Noise characteristic (2)14

Detector capacitance [pF]

Noi

se [

e]

TSpice Sim.

Exp.

Noise is much smaller than typical signal level (~20,000 [e])

The stability of the noise was checked.• The noise was evaluated in adjusting the time constant of amplifier circuits.

Stability of noiseStability of noise15

Noi

se [

e]

VGGP [mV]

( VGGS = 80[mV] )

Noi

se [

e]

VGGS [mV]

( VGGP = -200[mV] )

The noise level is stable (does not changed greatly).

Design value Design value

Time constant of pre-amp.(VGGP)

Time constant of shaping-amp.(VGGS)

Pair-monitor for Belle II ?Pair-monitor for Belle II ?The availability of the pair-monitor for B-physics experiment @KEK

(Belle II) was studied.

Simulation Setup• Tools

– CAIN (Pair-background generator)

– Jupiter (Tracking emulator)

• Virtual detector 1.1 m away from IP.

16

Pair-monitorand BeamCal

Virtual detector

IP

ILC Belle II

Beam energy 250 GeV 7.5 / 4.0 GeV

Crossing angle 14 mrad 80 mrad

Bunch size(σx, σy, σz)

(639nm, 5.7nm, 300μm) ( 6.2 μm, 23.7 nm, 3 mm)(10.6 μm, 26.9 nm, 3 mm)

Magnetic field 3.5 T + anti-DID 1.5 T

Hit distribution of pair background Hit distribution of pair background The hit distribution of the pair-background was checked (@200bunches).

→ The total number of hits (Nall) has information of σy.

17

Beam pipe

e+

e-

1/Nall v.s. σyHit distribution

Principle demonstration of the pair-monitor seems to be possible.To be more precisely studied.

SummarySummary• Pair-monitor is a silicon pixel detector

to measure the beam profile at IP.

• The development of the pair-monitor with SOI technology was started. The first prototype which is only readout ASIC was produce. The operation test was performed.

• All the ASIC components work correctly.

• The noise level is much smaller than typical signal level.

• The availability of the pair-monitor for Belle II was checked.

Principle demonstration of the pair-monitor seems to be possible.

To be more precisely studied.

• The irradiation test will be performed next month.

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PlanPlan

Thank you for listening!Thank you for listening!

BackupBackup

• Large crossing angle leads to high momentum (px).

Crossing angleCrossing angle21

e- beam e+ beam

Small crossing angle Large crossing angle

Nominal eNominal e++ee-- hit hit22

14[mrad] 30[mrad]

50[mrad] 80[mrad]

Crossing angle

Total number of hitsTotal number of hits23

1/Nall v.s. σy 1/Nall v.s. σx