developments in low-temperature metal-based packaging · 2011-12-15 · • project & research...
TRANSCRIPT
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
Jiyoung Chang and Liwei LinPh.D. Candidate, Department of Mechanical Engineering
University of California at Berkeley
Developments in low-temperature metal-based packaging
2011. 12.14
11
22
Contents
• Project & Research goals• Low temperature metal packaging
– Dry thermocompression– Rapid Thermal process– Solder pre-reflow– Insertion of thin metal layer
• Summary
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
33
Research goals
– Flux-less bonding
– Short bonding time & Low bonding temp.
– Sub-100m width bonding ring→ Photolithography definable & Electroplating
– Hermetic sealing→ Low permeability required
– CMOS compatible process
Center for Micro/Nano Scaling Induced Physics (MiNaSIP) in U.C.Berkeley- Subgroup research with Freescale™ semiconductor
44
Material selection
• Material Selection Criteria– Temperature– Deposition & bonding method– Permeability – Mechanical properties
*Glass Frit : Popular in MEMS packaging Deposition : Screen-printing (min.w≈150µm)
Temperature : 450 ˚C
Time :15-30 minutes
Mechanical : Brittle
→ Metal bonding Silicon
MEMSGlass frit
cap
F
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
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Dry Thermo-Compression (SnCu-Cu)
• 227 > Tbond > 232
• Results:– No bond or Solder reflowed
• Low process controllability – Non-planar surface issue– Surface oxidation may prevent
inter-diffusion
t=5m
T
t
F
Temperature profile Applied force profile
t=13m
t=13mt=5m
t
Bond viewed through pyrex cap
500 µm
200 µm
< Flipchip bonding parameters >
66
Sn Reflow Bonding via RTP
Silicon
MEMSCMOS Cu
capSn
Sn
Silicon
MEMSCMOS Cu
cap
• RTP (Rapid Thermal Process)• Short bonding time with high
temperature ramping up speed to prevent solder’s squeezing out
• Solder reflow benefitsLess sensitive to surface non-uniformitiesLow force
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
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77
Cap wafer fabrication Process Flow
Metallization(Ti 250Å / Ni 2000Å)
Lithography
Electroplate(Sn : 4-6m)
Etchback
Cap Wafer
Cap Wafer
Sn
Photoresist
Sn
metallization
88
Device substrate
Photoresist
metallizationMetallization(Ti 250Å / Ni 2000Å)
Lithography
Electroplating(Cu alloy, 4-8 µm)
Strip resist &Etch back
Substrate wafer fabrication Process Flow
Cu
Cu
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
99
RTP Bonds – Minimal Thermal Budget
• Thermal budgeting compared to glass frit– Time reduction – 10-50X – Temperature reduction – 1.5-2X
200 µm
Temp.
Timehold
ramp
Tmax =250-300 ˚Cramp = 10 secondshold = 10 seconds
1010
Mechanical strength comparable with glass frit
Pull-Test Setup
InstronArm
package
F (measured)
pull-tested bond
Material System Bond Strength(MPa)
Glass frit (thermo-compression)
8.5
Solder reflow (RTP) 7.5
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
1111
Leak & Autoclave Test• Dyed-IPA leak test
– Gross-leak detection– Small surface tension of IPA allows quick permeation
through voids
• 12-hour Autoclave test failed : 125ºC & 24psi
Dyed-IPA
Bonding ring
Sealed,No dyed-IPA
1212
Why hermetic test failed??
- Formation of leakage pass-through due to…• Void formation
– Gas trapping during bonding process– Metal oxide on surface prevents reflow of solder
• Non-uniform bonding along the bonding ring– Lack of uniform pressure applied during bonding
→ Pre-reflow process approach
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
1313
Pre-Reflow process
♦ Purpose of Pre-reflow process• Break the surface oxide layer and reflow fresh solder• To minimize gas trapping which causes void formation in bonding
area
Without Pre-Reflow With Pre-Reflow
Gas Trapping! Small initialcontact area!
1414
Pre-reflow bonding concept
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
1515
Device fabrication
1616
Pre-reflow profile optimization
• Process parameters in typical solder ball reflow process– Temperature gradient in preheat zone
– Soak temperature and time when using Flux
– Temperature gradient from soak to maximum temperature
– Maximum peak temperature
– Cooling gradient in cooling zone
– Total heating time
• Current solder reflow profile is optimized for solder ball to form sphere shape not for square line form solder
→ Reflow profile needs to be modified for line shape bonding
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
1717
Typical solder ball reflow profile
• Typical solder ball reflow profile– SnAgCu & SnPb case– ≈ 20ºC~30ºC higher peak temperature than melting temperature– ≈ 40sec of time above melting temperature– Total of 3~5min of process
• Denis Barbini et al. “Process Considerations for optimizing a reflow profile”, SMT/July 2005, www.smtmag.com
1818
SnAg solder with Pre-reflow test
• Electroplated Sn(96.5)Ag(3.5) eutectic solder• Bonding ring dimension: Width ≈200m, Height ≈6m
Before reflow After reflow
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
1919
SnCu eutectic solder with Pre-reflow test
• Electroplated Sn(99.3)Cu(0.7) eutectic solder• Bonding ring dimension: Width ≈ 200m, Height ≈5m
Before reflow After reflow
2020
SnCu solder with multiple reflow processes
2nd Reflow 3rd Reflow
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
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• Electroplated 10m and 20m width bonding ring • Width to Height ratio - 1.5:1~2:1
Low Width to Height ratio bonding ring
Electroplated SnAgwith 10m width bonding ring
Electroplated SnCuwith 20m width bonding ring
2222
SnCu reflow test results
• Reflow profile modification• Formed half-cylinder after reflow• Partially non-uniform clogging surfaces observed
Electroplated SnCuwith 20m bonding ring
After reflow
Reflow
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
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2323
SnAg 10m width ring pre-reflow results
• Reflow profile optimized in RTP• Uniform half-cylinder shape achieved• No clogging or solder gathering was observed
Electroplated SnAgwith 10m width bonding ring After optimized reflow
Reflow
2424
SnAg 10m width ring pre-reflow obtimization
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
2525
SEM image of SnAg bonding ring after pre-reflow
Reflow
2626
SnAg reflow results
• Surface profile measurement by micro profiler(ASIQ®)• Half-cylinder shape formation after reflow
0
2
4
6
8
10
35 40 45 50 55 60 65 70
Before Reflow
After Reflow
0
2
4
6
8
10
35 40 45 50 55 60 65 70
Before Reflow
After Reflow
Relative bonding ring position (m)
Hei
gh
t (
m)
SnAg solder reflow results plot
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
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2727
Height uniformity measurement
2
3
4
5
6
7
8
9
1 3 5 7 9 11 13 15
2828
Flipchip bonding result
• Optimized reflow profile in pre-reflow was applied in Flipchip
• Z-height control to push the solder after pre-reflow
material Width Height
Substrate SnAg solder ≈10m ≈7~8m
Cap Ni 150m ≈200nm
Substrate
Cap1. Heating
2. Solder pre-reflow
3. Bonding with z-control
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
2929
Leak test result
Dyed IPA
Dyed IPADeviceArea
Bondingring
Dyed IPA
DeviceArea
Bondingring
Destructive evaluationof interface
Cap wafer
Substrate wafer
DeviceArea
A
B
C
3030
Hermeticity test• 12-hour Autoclave test failed
Cap
Substrate
• Why failed?-Too small bonding ring overlap-Mis-alignment and parallel adjustment problem in Flipchip
Destructive evaluation
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
3131
Thin metal layer insertion approach
• Alloy formation b/w bonding metal (Al)
• Stronger bonding than pure Al-Al bondingat same bonding condition
Metal #1
Metal #1
Metal #1
Metal #1
Thin metal #2
Substrate
Metal #1Thin metal #2
Thermo-compression bonding
3232
Temperature/pressure condition
60 70130 930 1000
100ºC
350ºC
1.5Kg
60 1000
Time(sec)
Time(sec)
Temperature
Pressure
• Lower bonding pressure (15MPa)
• Lower bonding temperature(350ºC, Tm(Al)=660ºC)
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
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3333
Pull Test results
< Al to Al bonding > <Al+Sn20nm to Al bonding>
Adhesion layer on wafer (same color)
Bottom top Bottom top
-Same bonding parameter was applied for both cases
-Strong bonding at the contact interface for <Al+Sn20nm to Al bonding>
- No strong bond was made for Al to Al bonding case
Width : 50m
3434
Summary• Proof-of-Concept : Metal bonding for possible replacement of glass-frit
– CMOS-integrated process
– Compatible mechanical strength with glass-frit
• Rapid Thermal bonding result(no pre-reflow)– Successful leak-test for 200m bonding ring
– Failed 12hr hermetic test
• Solder reflow profile optimization for sub-100m metal bonding solution– Reflow profile optimization for 10mm SnAg boding ring
– Uniform half-cylinder shape reflow results
• Solder pre-reflow bonding of SnAg 10m bonding ring using Flipchip– Optimized reflow profile used for bonding
– Possibility of sub-100m bonding ring in MEMS packaging
• Metal insertion approach– Al-Sn-Al approach showed better bonding quality than pure Al-Al bonding
– Lower temperature and pressure
IEEE Santa Clara Valley Chapter, Components, Packaging and Manufacturing Technology Society
December 14, 2011
www.cpmt.org/scv
3535
Acknowledgement
• IEEE-CPMT
• Prof. Liwei Lin
• Mr. Kedar Shah
• Sponsor– Freescale™ semiconductor
– DARPA
Thank you!!