8/17/2019 Device and Circuit Modeling using Novel 3-State Quantum Dot Gate FETs.pdf

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  ISDRS 2007, December 12-14, 2007, College Park, MD, USA

ISDRS 2007 – http://www.ece.umd.edu/ISDRS

Device and Circuit Modeling using Novel 3-State Quantum Dot Gate FETs

F. C. Jain, E. Heller*, S. Karmakar, and J. Chandy 

Department of Electrical and Computer Engineering, University of Connecticut,

Storrs, CT 06269; * RSoft Design Group, Ossinings, NY 10562 

Abstract: This paper presents simulation of three-state behavior recently reported in quantum dotgate field-effect transistor (FET) structures. The model self-consistently solves Schrödinger andPoisson equations with built-in transfer of carriers from the inversion channel to two layers ofcladded SiOx-Si quantum dots (QDs) forming the gate, predicting the “intermediate state” in thetransfer Id-Vg characteristic. Circuit model and simulations for a 3-bit ADC are also presented.  

I. Introduction: Quantum dot (QD) gate memories have been fabricated in a number of wayssince the first reporting by Tiwari et al. [1]. During the fabrication of self-assembled quantum dotgate nonvolatile memories, it was observed that certain FET structures exhibit a novelintermediate state in the transfer (drain current Id-gate voltage Vg) as well as output (Id-Vd)characteristics, not observed in conventional FETs. That is, the transfer characteristics showthree stable states ("0", "1" and "i"), where the low-current saturation state "i" is manifested overa range of gate voltages which can be utilized for various circuit applications. These novel bistable characteristics provide new versatility in designing multiple-valued logic [2] CMOS

circuits with significantly reduced FET counts as well as advanced analog circuit building blockssuch as comparators for designing analog-to-digital converters (ADCs).

II. FET structure with two layers of SiOx-cladded Si quantum dots: Fig. 1(a) shows a typicalQD FET structure consisting of two layers of self-assembled SiOx-Si quantum dots between thesource and drain regions above the p-doped channel hosting the inversion electron channel [3].Figure 1(b) shows the three energy band diagrams at different gate voltages and a plot ofinversion layer carrier concentration as a function of gate voltage. Note that the carriers are firsttransferred to the second quantum dot layer near the gate (see Fig. 1b top right), and as the gatevoltage is further increased, the charge is located in the first quantum dot layer near the inversion

channel (see Fig. 1b bottom left).  The tunneling transition rate from the channel to thequantum dot layers is expressed by Hamiltonian in Eq.1 following Chuang et al. [4].

( ) ( )2

,

4w d d t w w d d w

w d 

 P H f f E E π 

ψ ψ δ →   = − −∑h

  (1) 

 p-Si

n+ Source n+ Drain

Two layers of SiOx-coated Si quantum dots

L

GateSource Contact Drain Contact

Gate Insultaor 

Field

Oxide

 

-10 2

124

0.84

1.2 Volts/Div0

ID

VG

OFF

Intermediate state "i"

(Low-Current Saturation)

ON "High-Current

Saturation"

Gate Voltage

Drain

Current

(a)

(b)

Fig. 1. (a) Cross-sectional schematic of a SiOx-Si quantum dot gate FET with transfer characteristicsshown in inset. (b) Simulated energy band diagrams and transfer (Id-Vg) characteristic.

978-1-4244-1892-3/07/$25.00 ©2007 IEEE

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  ISDRS 2007, December 12-14, 2007, College Park, MD, USA

ISDRS 2007 – http://www.ece.umd.edu/ISDRS

In quantum dot gate FETs, the gate insulator charge is composed of discrete values asexpressed in Eq. 2 (the conventional interface charge Qox at SiOx-Si interface is not shownas it does not relate to bistability). Thus, the threshold voltage increases in the gate voltagerange exhibiting the intermediate state ‘i’, keeping the drain current constant.

( )∫   ∑∑

⎥⎥⎦

⎤

⎢⎢⎣

⎡+−=−=Δ=Δ

 g  x

 g 

QDQD

 g 

QDQD

ox g ox

TH  FB x

 N n x

 x

 N n x

C 

qdx

 x

 x x

C 

qV V 

0

222111 ρ    (2) 

III. Circuit Model and 3-Bit ADC Simulation:

We have developed an empirical model for the QDFET that accounts for the intermediatestate ‘i’ in the range of gate voltages (Vg1  and Vg2). The effective threshold voltage isdivided into three ranges corresponding to the three regions of the transfer characteristics(see Fig. 1(a) bottom): region 1, intermediate state ‘i’, and the regular saturation part.

Using this model we have simulated a 3-bit ADC circuit in which the comparators arecomprised of a 3-state QDFET, an adjustable threshold QD gate FET, and a conventional p-MOS. The ADC schematic is shown in Fig. 2(a) and the CADENCE simulation results

are shown in Fig. 2(b). The QDFET parameters are: L=600 nm and W=15 μm with aW/L ratio ~ 24. The crossover voltage range of the comparator can be increased byadjusting the threshold voltage of the adjustable threshold QDFET. 

Fig. 2. Cadence simulation of 3-bit ADC: (a) Circuit block diagram with comparator comprised of3-state QDFET and adjustable threshold QD FET, and a p-MOS ; and (b). ADC output waveform.

This work is supported by ONR Contracts N00014-02-1-0883 and N00014-06-1-0016, and NSF-Grant ECS 0622068. Discussions with Dr. D. Purdy (ONR) and Dr. R. Khosla (NSF), andtechnical assistance in processing by Dr. R. Velampati and Dr. A. Rodriguez are gratefullyacknowledged.

[1] S. Tiwari, F. Rana, K. Chan, H, Hanafi, W. Chan and D. Buchanan, “Volatile and non-volatilememories in silicon with nano-crystal storage,” IEDM, pp. 521-525, Dec. 1995.[2] T. Hanyu, M. Kameyama, “A 200 MHz pipelined multiplier using 1.5 V-supply multiple valued MOScurrent-mode circuits with dual-rail source-coupled logic”,  IEEE Journal of Solid-State Circuits vol. 30,

no. 11, (1995).[3] F. Jain, R. Velampati, A. Rodriguez, E. Heller, E-S. Hasaneen, J. Chandy, B. I. Miller, F.Papadimitrakopoulos, Quantum dot gate 3-state field-effect transistors and nonvolatile memory devices formillimeter wave circuits, Int. J. Millimeter Waves and Infrared (submitted).[4] S. Chuang, N. Holonyak, “Efficient quantum well to quantum dot tunneling: Analyticalsolutions,” Appl. Phys. Lett., 2002; 80: 1270-1272.

(b)

(2N-1)

to N

encoder 

Over

Range

VinQD CMOS Inverter 

Ndigital

outputs

A 3-bit flash ADC with Tri-state CMOS inverters replacing

Comparators and Reference resistors

Priortity Encoder (PE)

P-MOS N-MOS

 NAND

Gate 1VDD

Vout2

P-MOS N-MOS(to NAND

gate)

VDD

Vout3

CLK 

Vin

P-MOS N-MOS

VDD

Vout1

20

21

2n

(1, i)

(1, i,

0)

QDM

VTH-1

VTH-1

QDMVTH-2

QDMVTH-3

WL-3

WL-1

WL-2

(a)