device driver - pudn.comread.pudn.com/.../726045/mtk_device_driver_2007.pdf · touch panel msdc uid...
TRANSCRIPT
Device Driver
2
AgendaOverviewBoot up and InitializationEMI CustomizationFlashAudio Relative settingsGPIOUEM configurationHW Default SettingADC Scheduler BMTCharging Parameter
EINTAux TaskUSBKeypadTouch PanelMSDCUIDLCDCamera
3
Overview
Layer 1Device Driver
BluetoothBluetooth
IrDAIrDA
SD/SD/MMMCMC
USBUSBAudioIn/Out
AudioCodec
Synthe-sizer
RF PMIC ModuleBaseband Chipset
LCDLCDDisplayDisplay
LCDLCDDisplayDisplay
MediaMediaICIC
CameraCameraTouchTouchPanelPanel
MMI
L4
Bluetoothheadset
USB data cable
Accessories:
CSR : BC3.0
4
GSM Solution Block Diagram
5
1MbRAM
GPRS Solution Block Diagram
6
GPRS Phone Block Diagram
7
GPRS Phone Block Diagram
2MbRAM
LCD
JPEG MP4
IPE
GIF
2D
ISP
UID
SBC
I2S
DSP91MHz
MT6226/6626M/6227 Baseband
8
GPRS Phone Block Diagram
384Kb RAM576Kb TCM
LCD
JPEG MP4
IPE
GIF
2D
ISP
UID
DSP104MHz
MT6225 Baseband
ARM7EJ104MHz
SBC
I2S
SDIO
9
GPRS Phone Block Diagram
Bus Architecture
10
Boot remapping
BOOTROM
MT6226
MCPMCP
Chip Select 0 (\CS0) to Flash
Chip Select 1 (\CS1) to SRAM or PSRAM
RemappingHardware setting (@reset)
iBoot tied to low ⇒ Boot from BOOTROMiBoot tied to high ⇒ Boot from \CS0
Bank0 (Flash) Bank1 (SRAM) 11
Bank1 (SRAM) Bank0 (Flash) 10
Bank0 (Flash) Bank1 (SRAM) 01
Bank1 (SRAM) Boot Code 00
Address 800 0000h Address 0000 0000h RM[1:0]
11
MCU_26M, MCU_52M,MCU_104M
MCU_13M, MCU_26M
MCU ClockMCU_CLOCK
EXT_13M, EXT_26MEXT_13M, EXT_26M
External PLL
EXT_CLOCK
MT6205B MT6218 and Later
ChipsetDescriptionNotation
MCU Clock
\make\ $(CUSTOM)_$(PROJECT).mak
12
Boot up and Initialization
\init\src\bootarm.s\init\src\init.c
Receiving start-up pattern via UART1
within 150ms?
Boot fromBOOTROM
RESET NO Switch PC to ExternalDevice Bank #0
YES
META Mode
Assign Supervisor Mode SP
If abnormal resetIs detected?
NO
YES Response theabnormal reset
Configure EMI
Data copy from flash to SRAM
Assign SP to various operation modes defined by ARM CPU.
Application initialization
Receiving start-up pattern via UART1
within 150ms?
Boot fromBOOTROM
RESET NO Switch PC to ExternalDevice Bank #0
YES
META Mode
Assign Supervisor Mode SP
If abnormal resetIs detected?
NO
YESException handler
Configure EMI
Data copy from flash to SRAM
Assign SP to various operation modes defined by ARM CPU.
Application initialization
Remapping?
NO
Setting 2 read waitstate to \CS0 and
\CS1
Copy exception handler
Remapping
YES
13
EMI Customization8 external chip selects (\CS0 to \CS7)Features
Deep address range up to 64MBFixed start addressPage mode supportable
Available page size are 8, 16, 32 or 64 Bytes.
8-bits or 16-bits device supportableRich of fine-tune items
Read set-up timeWrite set-up timeWrite hold time
14
RLT = Read Wait StatesC2RS = Chip Select to Read Strobe Setup TimeTotal read latency = RLT + 1Be careful that, [ (RLT+1) – C2RS ] meets the requirement
ECLK
RLT+1EA
ECSn#
C2RSERD#
ED
EADV
RLT=4, C2RS=2
READ
EMI Read Timing
15
WST = Write Wait States C2WH = Chip Select to Write Strobe Hold TimeC2WS = Chip Select to Write Strobe Setup TimeTotal write latency = WST + C2WH + 2Be careful that, [ (WST+C2WH+2) – C2WS – (C2WH+1) ] meets the requirement
ECLK
WST+C2WH+2EA
ECSn#
C2WS C2WH+1EWR#
ED
EADV
WST=3, C2WS=2, C2WH=1
WRITE
EMI Write Timing
16
Take S71PL064JA0BAW as example
FlashPage size: 16Bytes Random access: 55ns/65nsPage access 20ns
PSRAMPage size: 16BytesRandom access: 60ns/70nsPage access: 20ns
[ (RLT+1) – C2RS ] > tOE
[ (WST+C2WH+2) – C2WS – (C2WH+1) ] > tWP
All About EMI Setting
17
pSRAM read operation AC char.
18
[70ns, 1000ns]
[ x , 40ns]
RLT= 4TRLT= 4T
C2RS=1
C2RS=1
tOE (Output Enable to Output Delay)Time from \OE asserted to data ready, must not shorter than the upper bound
Total read latency = [ RLT + 1 ]= (4T+1T) x 19.2ns = 96ns > 70ns
tOE = [ (RLT+1) – C2RS ] =5T – 1T = 76.8ns > 40ns ( tOE MAX )
How if C2RS=3T and RLT=4T? tOE = 5T – 3T = 38.4ns (Too margin!)
[ x , 60ns]
52MHz
PSRAM Read Waveform
19
pSRAM write operation AC char.
20
tWP (Write Pulse Width)The minimal requirement of \WE must be kept low, must not shorter than the lower bound
Write latency = (3T+0T+2T) x 19.2ns = 96nstWP = [ (WST+C2WH+2) – C2WS – (C2WH+1) ] = 5T - 1T – 1T = 57.6ns > 45ns (tWP Min)
How if C2WS=3T and WST=3T? tWP = 5T– 3T– 1T = 19.2ns (Very dangerous!)How if C2WS=C2WH=1T and WST=3T? tWP = 5T–1T– 2T= 38.4ns (Dangerous!)
[70ns, 1000ns]
[45ns, X]
C2WS=1
C2WS=1
C2WH=0
C2WH=0
WST= 3TWST= 3T
52MHz
PSRAM Write Waveform
21
[25ns, X]
Page read latency tPC = (1T+1T) x 19.2ns = 38.4nsMore safety, assign PRLT = 2T
tPC = (2T+1T) x 19.2ns = 57.6ns
PRLT= 1TPRLT= 1T
52MHz
Flash Read Waveform
22
EMI
Take S71PL064JA0BAW as example again!Flash
C2WS=1T, C2WH=0, C2RS=1T, ADV=1, PLRT=1T, Page mode, WST=3T, PSIZE=16B, RLT=4T#define NOR_CS_1_Setting 0x44854324
PSRAMC2WS=1T, C2WH=0, C2RS=1T, ADV=1, PLRT=1T, Burst mode, WST=3T, PSIZE=16B, RLT=4T#define RAM_CS_Setting 0x44864324
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0x00E00000
0x00FFFFFF
64KBytes (31)64KBytes (31)
0x00000000
0x00E00000
Region1Block Size : 0x10000Block Count : 31
Region2Block Size : 0x2000Block Count : 8
Flash
NOR flash
Step3.
Set RegionInfo[]
Step4.
Set TOTAL_BLOCKS 39
Step5.
Set PARTITION_SECTORS 1024 Step1.FLASH_BASE_ADDRESS 0x00e00000 (Bytes)
Step2.
ALLOCATED_FAT_SPACE = 0x200000 (Bytes)
0x01000000
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Flash
NOR flash
25
EMI Auto-generation
CustomerInput
Custom_emi.cCustom_emi.h
Global compile Options
(-D)
Input
Output
Database(.XLS File)
SoftwareBuild
Process
Remain flexibility at customer
site!
custom_emi.hand custom_emi.c
existed?
YES
Pass
“New” Process
NOSoftware builder retrievesthe “device” part ID and
search through thedatabase
ID found?YES
NO
Build Error!
Generate two files,custom_emi.h and
Custom_emi.c accordingly!
Pass
26
EMI Auto-generation
Generation“custom\system\projectname_BB\custom_emi.c&custom_emi.h”Standalone generate EMI and MCP configuration
make [project name] [gsm/gprs] emigen
Eliminate custom_emi.c and custom_emi.hmake [project name] [gsm/gprs] emiclean
Data setting“mcu\\tools\MemoryDeviceList\MemoryDeviceList.xls”
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EMI Auto-generation
NOR + SRAM MCP
__INTEL_TYPE_NOR_FLASH____RENESAS_TYPE_NOR_FLASH_
_LOW_COST_SINGLE_BANK_FLASH_
__PAGE_BUFFER_PROGRAM__
28
EMI Auto-generation
custom_MemoryDevice.hMEMORY_DEVICE_TYPE
NOR-flash and SRAM/PSRAM MCPCS0_PART_NUMBER = CS1_PART_NUMBER
LPSDRAM NFBAlways specify the part number at CS0_PART_NUMBER
/*****************************************************************************Step 1: Specify memory device type and its complete part number
Possible memory device type: NOR_RAM_MCP, LPSDRAM*****************************************************************************/#define MEMORY_DEVICE_TYPE NOR_RAM_MCP#define CS0_PART_NUMBER LRS1828C#define CS1_PART_NUMBER LRS1828C
#define MEMORY_DEVICE_TYPE LPSDRAM#define CS0_PART_NUMBER HYB18L256160BF_MT6228EVB
29
EMI Auto-generationAdditional partition on NOR-flash disk, in terms of sector (512Bytes)
/*****************************************************************************Step 4: Define the first partition size on NOR-flash FAT; if no additional
partition on NOR-flash disk, it should be 0.
It is special for NOR-flash disk which has two partitions, thefirst leading is user drive, visible on USB disk, the second may besystem drive, and invisible from USB disk.
[VERY IMPORTANT NOTICE]=======================Please assign the exact value in terms of sectors (one sector equalto 512Bytes).MUST NOT assign as(TOTAL_FAT_SIZE - SIZE_OF_SYSTEM_DRIVE), because system will keepsome spaces for disk management.
*****************************************************************************/#define PARTITION_SECTORS 1536
30
EMI Auto-generationAdditional partition on NAND-flash disk
SYSTEM_DRIVE_ON_NANDNAND_FLASH_BOOTING
/***************************************************************************Step 5: Define the first partition size on NAND-flash FAT; if no additional
partition on NAND-flash disk, it should be 0.
It is special for NAND-flash disk which has two partitions, thefirst leading is user drive, visible on USB disk, the second may besystem drive or user drive.[VERY IMPORTANT NOTICE]=======================Please assign the exact value in terms of sectors (one srctor equalto 512Bytes).MUST NOT assign as(TOTAL_FAT_SIZE - SIZE_OF_SYSTEM_DRIVE), because system will keepsome spaces for disk management.
************************************************************************/#if ( defined(__FS_SYSDRV_ON_NAND__) || defined( _NAND_FLASH_BOOTING_) )#define PARTITION_SIZE (180000)#else#define PARTITION_SIZE (0)#endif
31
EMI Auto-generationSpecific for NFB only, used to specify start address and space of FAT area!
Parameter is unnecessary for SYSTEM_DRIVE_ON_NAND
/***************************************************************************Step 6: This is an optional step special for NFB (NAND-flash Booting)
system only.[VERY IMPORTANT NOTICE]=======================The spare area is excluding from the FAT SPACE!!!
**************************************************************************/#ifdef _NAND_FLASH_BOOTING_/************** Step 6.a. **************/#define FLASH_BASE_ADDRESS 0x02000000 // 32MB
/************** Step 6.b. **************/#define ALLOCATED_FAT_SPACE 0x06000000 // 96MB
#endif /* _NAND_FLASH_BOOTING_ */
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Audio
L1SP_BUFFER_ST
L1SP_BUFFER_1
L1SP_LNA_0
L1SP_LNA_1
FM Radio Chip
(MT6189)L1SP_BUFFER_0
33
Audio
Play/Record Events
MMI
MED
NVRAM L1 Audio HISR
MDI API
L1 Audio API
Flash DSP
Read/Write audio coefficients
Analog gain
Digital gain
Set volume level, (EM)Set audio coefficients, Play/Record audio
34
Audio
Audio modes and volume levelsaudio mode = normal, volume type = AUD_VOLUME_MEDIA, volume level = 2gain = volume_gain[0][6][2] = 32
MED
255212172134624816Handfree mode
2121721326448203Headset mode
1901601205432161Normal mode
6543210
Volume level
Audio mode
type = 0
type = 6
Volume gain is 0 ~ 255
35
Audio\custom\audio\[PRJ]\afe.c
Step1. Set the proper GPIO Pin for Loud Speaker –Function:–AFE_SwitchExtAmplifier
Step2. Set Differential mode/ Single ended for Speaker–Function:–AFE_Initialize
36
Audio\custom\audio\[PRJ]\audcoeff.c
Normal mode Microphone path
Headset mode Microphone Path
Normal mode Speaker path
Headset mode speaker path
Loud speaker pathStereo output path
L1SP_BUFFER_1L1SP_BUFFER_ST
L1SP_BUFFER_1
L1SP_BUFFER_0
L1SP_LNA_0
L1SP_LNA_1
37
Audio
AUD_VOLUME_CTN (0)call waiting tone, error tone, warning tone
AUD_VOLUME_KEY (1)keypad tone
AUD_VOLUME_MIC (2)microphone input
AUD_VOLUME_FMR (3)FM radio sound
AUD_VOLUME_SPH (4)speech sound (during phone call)
AUD_VOLUME_SID (5)side tone (sound loop-back)
AUD_VOLUME_MEDIA (6)music
0) Tone_SetOutputVolume1) KT_SetOutputVolume2) L1SP_SetMicrophoneVolume3) FMR_SetOutputVolume4) L1SP_SetSpeechVolume5) L1SP_SetSidetoneVolume6) Media_SetOutputVolume
MEDL1 Audio API
\custom\audio\[PRJ]\nvram_default_audio.c
38
GPIO\custom\drv\misc_drv\[PRJ]\gpio_drv.c
These GPIOs and GPOs are also multiplexed with other functionalities.
GPIO InitializationNot be changed once the hardware is finalizedRefer to Base band chip datasheet and HW layout
39
GPIO\custom\drv\misc_drv\[PRJ]\custom_equipment.c
40
HW Default Setting\custom\audio\[PRJ]\nvram_user_config.c
Set PWM1, PWM2, Alter Level.–LCD backlight, keypad backlight, flashlight.–Data structure
41
HW Default Setting\custom\audio\[PRJ]\nvram_user_config.c
LCD default contrast setting
Battery Level setting
42
ADC
A channel used by auxiliary deviceBattery monitoringCharger controlPeripheral device detectionTemperature measurement
One physical channel may have many logical owners
Auto measureTDMA timer trigger
ADC Channel
ADC User 1 ADC User 2 ADC User 3
43
ADCcustomize
\custom\drv\misc_drv\[PRJ]\adc_channel.c5 ADC channels in MT6205B, 7 in MT6218B & MT6219Customized ADC channel definitions
44
BMT
Software architecture
BMT Task
ADC driver
NVRAMPMICdriver
MMI AUX task
ADC scheduler
Charging Algorithm
45
BMTLi-Ion battery Charging Diagram
46
BMT
g. Check ADC fail,
h Safety timer timeout (6hr)
i. Charger plugged out
Prechargestate
Chargecomplete
state
Fast (CC)charge
state
Top-off (CV)charge state
Init state
Any state
Charger detected
Vbat_off > 3.4V
Vbat_off > 4.1V
ICHG < 60mA
Talk/Pausestate
Vbat_off>4.05V and in talking mode
Vbat_off < 3.8V or in stand by
mode
Vbat_off < 4.1VVbat_off>4.05V and in talking mode
Vbat_off>4.05V and in talking mode
ADC check for abnormal condition
a. Vbat > 4.5V Battery over voltage
b. Vchg> 6.5 or Vchg< 4.5 Invalid charger
c. BATEMP < 0oC or BATEMP > 45oC Battery temp. too cold or over heat
d. BATID N.A.
e. ICHGon> 750mA or ICHGon< 20mA Invalid charger or battery
f. ICHGoff> 50mA Charger fail
Charge Error/end
state
Init safety timer
Vbat_off>4.05V and in talking mode
j. Bad contact of Charger
All boundary values above can be customized
47
BMT
Battery/charge ParametersParameter Description
Typical_LI_BATTYPE Battery id voltage to check LI battery or NI battery. If phone doesn’t support Li and NI-MH battery together, this value may be useless. (unit: uV For example, “the value = 4000000” means “voltage = 4V”).
Typical_NI_BATTYPE Battery id voltage to check LI battery or NI battery. If phone doesn’t support Li and NI-MH battery together, this value may be useless. (unit: uV)
ICHARGE_TBD If measured charge current achieves this value, “over charge current” event is issued. (unit: uA)
BATTMP_0C The voltage value when battery temperature is 0℃. (unit: uV)
BATTMP_45C The voltage value when battery temperature is 45℃. (unit: uV)
MAX_VBAT_LI If measured battery(LI) voltage in charge mode archives this value, “over voltage protect ” event is issued. (unit: uV)
MAX_VBAT_NI If measured battery(NIMH) voltage in charge mode achieves this value, “over voltage protect ” event is issued. (unit: uV)
CVPROTECT_HIGH If measured battery(LI) voltage in charge mode achieves this value, and phone is in talk mode, the charge action will automatically stop to protect the battery. (unit: uV)
CVPROTECT_LOW If measured battery(LI) voltage in charge mode achieves this value, and phone is in talk mode, the charge action will automatically start again. (unit: uV)
48
Charging Parameter\custom\drv\misc_drv\[PRJ]\chr_parameter.c
Step 1. Calibration (6217 *7, 6205B *5 adcchannels)
49
Charging Parameter\custom\drv\misc_drv\[PRJ]\chr_parameter.c
–Step 2. GPIO configuration for charging control , battery detection and vibrator.–Step 3.Charging parameter
Warning! Bad Contact -Charger!
Warning! Low Battery Temperature!
50
Battery level SettingHW level table
\custom\drv\misc_drv\[project]\custom_hw_default.c and located atNVRAM_EF_CUST_HW_LEVEL_TBL_DEFAULT
Modify accordinglyLevel 4------------------ 3.88VLevel 3------------------ 3.74VLevel 2------------------ 3.60VLevel 1------------------ 3.55VLow Battery ------------------ 3.40VMo Limit------------------ 3.39VPower Off
51
EINT\custom\drv\misc_drv\[PRJ]\eint_def.cExternal Interrupt channel assignment
Channel assignment.De-bounce time delay setting.Example:
52
EINT
Step 1 : Register ISR function for EINT
Step 2 : Implement ISR
Step 3 : Reverse polarity of external interrupt
53
AUX task
Plug-in Detection
Ext_ISR Aux TaskMSG_ID_AUX_PLUGIN
BMT Task
aux_read_adc_channel(aux_adc_logic_id);
(MSG_ID_BMT_ADC_ADD_ITEM_REQ)
UEM Task
MSG_ID_AUX_ID
MSG_ID_BMT_ADC_MEASURE_DONE_CONF
12
3
4
5
According the return adcvalue to decide what is plug in
54
AUX task
Plug- out Detection
Ext_ISR Aux TaskMSG_ID_AUX_PLUGOUT
BMT Task
aux_remove_adc_channel(kal_uint8 logic_id)(
(MSG_ID_BMT_ADC_REMOVE_ITEM_REQ)
UEM Task
MSG_ID_AUX_ID
1
3
2
55
AUX task
Send Key Detection
1.Ring 2.Hook up
Aux start to poll ADC value
Aux stop turn on microphone bias and keep polling ADC value
3.Hang-up
Aux stop to poll ADC value
Time
56
AUX task
\custom\drv\misc_drv\[PRJ]\aux_main.cAUX Task is to
Detect earphone, UART plug-in and plug-out Detect PTT-key press Support ADC report in Engineer mode
57
AUX taskGeneric Drivers\interface\hwdrv\eint.h :External declaration and constant definitions for external INT.
Customization\custom\drv\misc_drv\ [PRJ] \aux_main.c : AUX Task to
To detect earphone, uart plug-in and plug out To detect send_end key press Support ADC report in Engineer mode
\custom\drv\misc_drv\ [PRJ]\eint_def.c :Definition and query APIs for external INT channels,
e.g. AUX_EINT_NO = 0;CHRDET_EINT_NO = 1;CLAMDET_EINT_NO=2;
58
AUX task
\custom\drv\misc_drv\[PRJ]\auxmain.cAUX Task is to
Detect Clam on/off (Clam shell project only)Step 1 Set the clam_state as the open level
kal_bool clam_state = LEVEL_HIGH;
Step 2 Set the proper Clam Close LevelIn function void CLAM_EINT_HISR(void)
Set CLAM_CLOSE level
59
USB
Software architecture
60
USB
Event Flow
61
USB
62
USBMass Storage Disk Mount
63
Keypad
Keypad ISR (Kbd_LISR)
Keypad Task&decoder (kbd_task_main)
KBD.event
Keypad-scanner Hardware
Key pressed Key Released
UEM Task
Keypad bufferMSG_ID_DRVUEM_KEYPAD_IND
Kbd_GetKeyData
64
Keypad
Keypad– Detect one or two5X5 matrix in MT6205B7X6 matrix in MT6218B and Later
65
Keypad
\custom\drv\misc_drv\[PRJ]\keypad_def.cKeypad mapping definition
5X5 matrix in MT6205B7X6 matrix in MT6218B,MT6219
66
Touch Panel
Touch panel event flow(driver)
HISR
Down
Up
67
Touch Panel\custom\drv\misc_drv \[PRJ]\eint_def.c
Step 1. Define EINT in eint_def.c
\custom\drv\misc_drv \[PRJ]\ touch_panel_spi.hStep 2. Define GPIO
\custom\drv\misc_drv \[PRJ]\ touch_panel_spi.cStep 3. Implement serial interface
68
Touch Panel\custom\drv\misc_drv\[PRJ]\ touch_panel_custom.c
Step 4. Set ADC and coordinate calibration
69
MSDC
Software ArchitectureFile system
File system Interface Layer (Sd_drv.c)
Memory Card Driver(Sd.c)
Memory Card Host Controller Driver(msdc.c)
Memory Card Host Controller
Memory Card
Card Driver
FAT
Hardware
70
MSDC
Type 1: MCINS connect to VSS define __MSDC_NOT_SUPPORT_HOT_PLUG__ in
makefile
71
MSDC
Type 2: MCINS connect to VSS define __MSDC_NO_WRITE_PROTECT__ in makefile
72
MSDC
\custom\drv\misc_drv\[PRJ]\msdc_custom.cStep 1. Config driving current
73
UID
Compile OptionUID_SUPPORT
Supported H/W VersionMT6226, MT6226M, MT6227, MT6228, MT6229 and later chips.
Supported S/W VersionLoad Version
Main-trunk / 05C from w05.49
FlashTool / Multiple Download ToolFrom v2.7.1011
74
Chip A
SE Load
Encryption A
NOR/NAND
UID A
Load
Encryption AWrite to flash
Chip B
SE
UID B
Load
Encryption B
NOR/NAND
Load
Encryption BWrite to flash
DALoad
UID
Camera Driver Porting
76
Outline
IntroductionBase band Camera featureMT6217/18+BackendMT6219/MT622X+Sensor
77
CameraBase band feature(MT6217)
Jpeg DecoderHas to decode full imageDestination has to be sequential
Multi-layer 4 layers
LCD ControllerNeed an extra Camera Backend
OSDJpeg DecoderLCD ControllerSensorImage ProcessorJpeg Encoder
78
CameraBase band feature(MT6219,MT622X)
Jpeg Decoder/EncoderMay decode partial image
Mpeg 4 Decoder/EncoderMulti-layer
4 layers
LCD ControllerImage ProcessorNeed an extra Sensor
Support up to 1.3 Mega Pixel (MT6219,Bayer Only)Support up to 0.3 Mega Pixel (MT6225,YUV Only)Support up to 0.3 Mega Pixel (MT6226)Support up to 1.3 Mega Pixel (MT6226M)Support up to 2.0 Mega Pixel (MT6227)Support up to 3.0 Mega Pixel (MT6228)
79
Camera
Camera MT6217 Slave backend
MT6217
PAP1301 (PixelArt)
LCMBase band
Camera Backend
Sensor
80
Camera
CameraMT6217 Master Backend
MT6217
VC0558(ViMicro)
LCM
Base band
Camera Backend
Sensor
81
Camera
Camera MT6219 structure
MT6219
LCM
Base bandSensor
82
Camera Software ArchitectureMMI Task
Camera ApplicationLogic, Interrupt handling
MDI_CameraAPI interface to use camera features
GDIMulti-layer (frame buffer) management
Media TaskInterface to access camera driverCamera Driver
Control Camera backend
LCD InterfaceControl LCM
MMI Task
MDI Camera GDI
LCD InterfaceCamera Driver
HW- (LCM, ISP, MT6218, MT6219...)
MEDIA Task
Camera MMI
83
Camera
Slave backend
MMI Task
MDI Camera GDI
LCD InterfaceCamera Driver
MEDIA Task
Camera MMI
LCMAIT103
Layer 0
MT6218B
Layer 1
Layer 2
84
Camera
Master backendMMI Task
MDI Camera GDI
LCD InterfaceCamera Driver
MEDIA Task
Camera MMI
LCM
Layer 0
Layer 1
MT6218B
Layer 0Layer 1
AIT700
Intermediate Buffer
AIT700 OSD Buffer
85
Camera
MMI Task
MDI Camera GDI
LCD InterfaceCamera Driver
MEDIA Task
Camera MMI
LCM
ISP
Layer 0blt_layer_flag == LAYER 0 | LAYER 1 | LAYER 2
preview_layer_flag == LAYER 0
Layer 1
Layer 2
MT6219
Layer 0Layer 1Layer 2
86
Camera (MT6217)
Files:\custom\drv\cam_module\[prj]\cam_module.c\custom\drv\cam_module\[prj]\cam_module.h
Function:Function:
87
Camera (MT6219)
Camera TaskISP
isp_if.c.h,ae_awb.c.h,
Driverimage_sensor.c.h
BoardCamera_hw.c
Tuningcamera_para.cCamera_info.c
AE AWB
6219 ISP
control tuning
88
Camera (MT6219)Preview
ISP/Sensor CLK setting.Mode/Resolution configurationActive window configuration
CaptureAll you did in “Preview”Mode switching
VGA/SXGAzoom<2x and 2x<=zoom<=4x.
Set ShutterControl the exposure time precisely.Depends on sensor characteristic.
89
HW Interface
Signal Bus
VSYNC
HSYNC
SCLK
SDATA
XCLK
PCLK
8 or 10
DATA
PWDN
POWER
6219ISP
Sensor
90
Sensor&ISP timing
Valid Frame
VSYNC Valid Frame
SENSOR_PERIOD_PIXELSHSYNC
HBLANKING
VBLANKING
91
AE/AWB Algorithm
AE/AWB Window
AE “Window size”, “region” and “weighting” are configurable, and reports the luminance.AWB window reports the R, G, B accumulation.
w1 w2 w3
w4 w5 w6
w7 w8 w9
92
AE/AWB Algorithm
AE Process(FW)AE banding factor.
Base-shutter should be at lease 1/2f.Base-shutter=PIXEL_CLK/(2f*SENSOR_PERIOD_PIXELS)
VSYNC ValidFrame
SENSOR_PERIOD_PIXELSHSYNC
93
AE/AWB Algorithm
AE Process(FW)AE computation.
Exposure time(shutter), pre-gain.Linear interpolation.
avg_lum = weighted average of 9 windows.
Exposure time
Luminance
Y1
Y2Yt
T2 T1Tt
Desired Luminance
Exposure time 和 Luminance 不是线性的,要逐次计算AE逼近
LCM Driver Porting
95
Outline
Hardware ArchitectureLCD software ArchitectureFiles related to LCD driverLCM driver porting procedure
96
LCM
Hardware Architecture
MT 62XX
LCDDMA Controller
Parallel Accelerator
Serial Accelerator
EMI/NFI8080
LCD DATA
LCD CLK
LCD CS0/1LCD A0
Main-PanelLCDModule
Sub-PanelLCDModule (Opt.)
97
Hardware Architecture
D 7 D 5 D 3D 4D 6 D 2 D 1 D 0 D 0
C L K
D A T A
C S
A 0
A 0 D 6 D 4D 5D 7 D 3 D 2 D 1 D 0
CL K
D A TA
CS
9-bit SPI Interface
8-bit SPI Interface
98
Hardware Architecture
8080-Series MPU Interface
6800-Series MPU Interface
99
LCM
LCM software Architecture
MMI
LCD InterfaceFunctionpointer
GDI
get_lcd_frame_buffer_address()
UEM
DRV_RGB_TO_HW(R,G,B)DRV_LCD_SET_BUFFER_PIXELDRV_LCD_GET_BUFFER_PIXEL
RGB LEDBacklightControl
LCM Driver n
LCM Driver 2
LCM Driver 1
100
LCD interface
Parallel LCDInterface
Serial LCDInterface
External MemoryInterface
LPCE0#LPCE1#LRST#LRD#LWR#LPA0#
NLD[7:0]
LSCE0#LSCE1#
LSDALSA0#LSCLK
EA[25:0]ED[15:0]EC[7:0]ERD#EWR#
SYSRAM
Layer0 Controller
Layer1 Controller
Layer2 Controller
Layer3 Controller
LUT0
LUT1
Overlay
LCD AHBMaster1
LCD AHBMaster0
MT6219
101
MT6205B→1 layerMT6218B and Later→4 layers
Layer0
(x0, y0) Layer1
(x1, y1)
Layer2
(x2, y2)
Layer3
(x3, y3)
ROI
Opacity
rotation
Offset
Start Address
Size
LCD
102
Files related
.\custom\drv\Lcd\XXXX_lcmlcd.clcd_hw.hlcd_sw.hlcd_sw_inc.h
.\custom\drv\misc_drv\XXXX_bbcustom_hw_default.c…
103
custom_hw_default.cOpen \custom\drv\misc_drv\[project]\custom_hw_default.c
Contrast level
104
LCD_if.h
105
Members Description
Normal Mode
Init LCD initialize function
PWRON LCD power on/off function
BrightLevel Adjust LCD brightness
SCREENON LCD screen on
BlockWrite Block data write to LCD driver IC
GetSize Obtain the size of the LCD panel
SleepIn LCD enter sleep mode
SleepOut LCD exit sleep mode
Engineering Mode
get_param_number Obtain the parameter number of the function
set_bias Configure LCD bais
set_contrast Configure LCD constrast
set_linerate Configure LCD frame-refresh rate
set_temp_compensate Configure LCD temperature compensation parameter
106
Image Size
For 05A&05B, define in MI_featuresPLUTO.h
For 05C, define in MakfileMAIN_LCD_SIZE = 176X220
107
CASE STUDY
Baseband : MT6219LCM : HD66773 8Bit InterfaceCodebase :T6219Main LCD : 128 X 160
108
CASE STUDY
Step1:Define the colour & panel option in [project name]_GPRS.makCOM_DEFS_FOR_XXXX_LCM =
COLOR_LCD MAIN LCDCOLOR_SUBLCD SUB LCDDUAL_LCD TWO LCDS
109
CASE STUDY
Step2:Turn on the LCD_CMD_DMA_MODE option in LCD_SW.H
110
CASE STUDYStep3: Define main/sub LCD command/data address according to hardware LCD interface configuration in LCD_SW.H
111
LCM driver porting procedureStep3(2): Define main/sub LCD command/data address according to hardware LCD interface configuration in LCD_SW.H
112
MT6218B LCM driver porting procedure
Step4: Define main/sub LCD output format in LCD_SW.H
113
CASE STUDY
Step4:Define main/sub LCD output format in LCD_SW.H
114
CASE STUDYStep5: Implement
LCD_CtrlWrite_HD66773R(_data) LCD_DataWrite_HD66773R(_data)LCD_RAMWrite_HD66773R (_data)
in LCD_SW.H
Transfer upper 8 bits first
115
LCM driver porting procedureStep6: Declare LCD_Funcs variable for MainLCD, SubLCD
116
CASE STUDYStep6(2): Declare LCD_Funcs variable for MainLCD
117
CASE STUDY
Step7: Configure in LCD_FunConfig() in LCD.C
118
CASE STUDYStep8: Config LCD data bus & Gamma table in init_lcd_interface() LCD.C
MT6219 : 8 bit onlyMT6217 : 8/16 bitMT6226 and above : 8/9/16/18 bit
119
CASE STUDY
Step9: Config NFI interface in LCD.C
120
CASE STUDY
121
CASE STUDY
25ns25ns
100ns
SET_LCD_PARALLEL_CE2WR_SETUP_TIME(2); SET_LCD_PARALLEL_CE2WR_HOLD_TIME(2);
SET_LCD_PARALLEL_WRITE_WAIT_STATE(7);
122
CASE STUDY
Step10: ImplementLCD_Init_HD66773R() LCD_BlockWrite_HD66773R()
First, then you can see something on the LCD
123
CASE STUDY
Step10.1: LCD_Init_HD66773R() You can ask LCD module supplier for initial code
124
CASE STUDYStep10.2: LCD_Set_Y_Addr_HD66773R()
And LCD_Set_X_Addr_HD66773R()
125
CASE STUDY
126
CASE STUDYStep10.3: LCD_BlockWrite_HD66773R()
RAM Write Data Mask (R20h)RAM Address Set (R21h)
127
Reference
“GSM_GPRS system configuration V1.70-PS1 part.doc”“Device Driver”, Liu Yong“LCD Driver Programming(T)”, Ether Sheu
128
Reference
Customer_BB_Driver_Customization_V0.1Memory & EMI presentation, Terry HuangDevice Driver,Liu yongThe Introduction of ChipUID Feature.ppt
129
Q&A
Thank You !!