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ECE 3120 Microelectronics II Dr. Suketu Naik
Chapter 8
Differential
and
Multistage
Amplifiers
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ECE 3120 Microelectronics II Dr. Suketu Naik
Operational Amplifier Circuit Components
1. Ch 7: Current Mirrors and Biasing
2. Ch 9: Frequency Response
3. Ch 8: Active-Loaded Differential Pair
4. Ch 10: Feedback
5. Ch 11: Output Stages
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ECE 3120 Microelectronics II Dr. Suketu Naik
Active-Loaded Differential Pair
Two Stage
Op Amp
(MOSFET)
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ECE 3120 Microelectronics II Dr. Suketu Naik
Learning Objectives
1) MOS and the bipolar differential amplifiers: how
they reject common-mode noise or interference and
amplify differential signals
2) The analysis and design of MOS and BJT differential
amplifiers: utilizing passive resistive loads, current-
source loads, and cascodes
3) The structure, analysis, and design of amplifiers
composed of two or more stages in cascade
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ECE 3120 Microelectronics II Dr. Suketu Naik
Why Differential?
0) What is a differential signal?
1) Differential circuits are less sensitive to noise and
interference
2) Differential configuration enables biasing the amplifier and
coupling of amplifier stages without bypass and coupling
capacitors
3) Useful in IC design because of good matching between the
transistors
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ECE 3120 Microelectronics II Dr. Suketu Naik
MOS Differential Pair
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.1. The MOS Differential Pair
Differential Pair
Two matched transistors (Q1 and Q2) joined and biased by a constant current source I
FETs should not enter
triode region
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ECE 3120 Microelectronics II Dr. Suketu Naik
Input Common Mode Range
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.1.1. Operation with a Common-Mode Input Voltage
Suppose that two gate terminals are joinedtogether and connected to a common-mode voltage(VCM)
vG1 = vG2 = VCM
Q1 and Q2 are matched
Current I will divide equally between the two transistors.
ID1 = ID2 = I/2,
VS = VCM – VGS; where VGS is the gate-to-source voltage.
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ECE 3120 Microelectronics II Dr. Suketu Naik
Equations (8.2) through (8.8)
describe this circuit (channel-
length modulation is neglected)
Note the range (max and min)
of input common-mode voltage
(VCM): beyond this range the
diff pair leaves saturation
2
2
1 2
1 2 2
1 2 2
2
2
(8.2)
(8.3)
(8.4)
(8.5)
(8.6)
(8.7)
(8.8)
n GS t
OV GS t
n OV
OV
n
D D DD D
CM t DD D
CM SS CS t OV
I Wk V V
LV V V
I Wk V
L
I WV
k L
Iv v V R
IV V V R
V V V V V
max
min
8.1.1. Operation with a Common-Mode Input Voltage
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.1.2. Operation with a Differential Input Voltage
vid is applied to Q1 and Q2 is grounded:
vid = vGS1 – vGS2 > 0
iD1 > iD2
The opposite applies if Q1is grounded
The differential pair responds to a difference-mode or differential input signals.
The diff pair provides corresponding differential output signal between the two drains
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ECE 3120 Microelectronics II Dr. Suketu Naik
Differential Input Voltage
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ECE 3120 Microelectronics II Dr. Suketu Naik
Two input terminals
connected to a differntial
signal vid
Bias current I of a perfectly
symmetrical differential pair
divides equally
To steer the current
completely to one side of the
pair, a difference input voltage
vid of at least √2VOV is needed.
8.1.2. Operation with a Differential Input Voltage
1
1
1
2
1
(8.9
(
1
2
8. 2 / /
2
2
9)
(
)
(8.10
(
8.9)
8.
10)
)
n GS t
GS
GS
id
t n
t OV
id GS S
OV
v
WI k v V
L
v V I k W L
V V
v V v
v V
max
max
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ECE 3120 Microelectronics II Dr. Suketu Naik
Large Signal Operation
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.1.3 Large-Signal Operation
Objective: derive expressions for drain current iD1 and iD2 in terms of differential signal vid = vG1 – vG2
Assumptions:
Perfectly matched transistors
Channel-length modulation is neglected
Load independence is present
Saturation region
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ECE 3120 Microelectronics II Dr. Suketu Naik
Step #1: Expression drain
currents for Q1 and Q2.
Step #2: Take the square roots
of both sides of both (8.11)
and (8.12)
Step #3: Subtract (8.14) from
(8.15) and perform appropriate
substitution.
Step #4: Note the constant-
current bias constraint.
2
1 1
2
2 2
1 1
2 2
1 2 1 2
1(8.11)
(8.12)
(8.13)
(8.14)
(8.15
21
2
1
2
1
2
)
D n GS t
D n GS t
D n GS t
D n GS t
GS GS G G id
Wi k v V
LW
i k v VL
Wi k v V
L
Wi k v V
L
v v v v v
8.1.3 Large-Signal Operation
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ECE 3120 Microelectronics II Dr. Suketu Naik
Step #5: Simplify
(8.15).
Step #6: Incorporate
the constant-current
bias.
Step #7: Solve (8.16)
and (8.17) for the two
unknowns – iD1 and iD2.
1 2
21 2
2
1
2
2
1 2
2
/2 1
2 2
/2
(8.17)
(8.17)
(8.23)
(8.24) 12 2
D D
D D n id
id idD
OV OV
id idD
OV OV
i i I
Wi i I k v
L
v vI Ii
V V
v vI Ii
V V
8.1.3 Large-Signal Operation
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ECE 3120 Microelectronics II Dr. Suketu Naik
Transfer characteristics of (8.23)
and (8.24) are nonlinear.
Linear amplification is desirable
and vid will be as small as possible.
For a given value of VOV, the only
option is to keep vid/2 much
smaller than VOV.
small-signal approximation
1
2
(8.25)
(8.2
2 2
6)
(8.
2 2
2
27)
idD
OV
idD
OV
idd
OV
vI Ii
V
vI Ii
V
vIi
V
8.1.3 Large-Signal Operation
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ECE 3120 Microelectronics II Dr. Suketu Naik
Figure 8.7: The linear range of operation of the MOS differential pair can be extended
by operating the transistor at a higher value of VOV .
8.1.3 Large-Signal Operation
VOV increases (smaller W/L): Gain will decrease, Linearity will increase
VOV decreases (larger W/L): Gain will increase, Linearity will decrease
Can increase the bias current to increase gm and gain
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ECE 3120 Microelectronics II Dr. Suketu Naik
Small-signal Operation
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.2 Small-Signal Operation of the MOS Differential Pair
Virtual ground at the source
- Elimintates need for large
bypass capacitor
VCM = bias voltage at the gate
vid = differential small signal
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ECE 3120 Microelectronics II Dr. Suketu Naik
For MOS pair, each device
operates with drain current
I/2 and corresponding
overdrive voltage (VOV).
gm = I/VOV
ro = |VA|/(I/2).
8.2.1 Differential Gain
1
2
1
2
1
21
2
2 2( /2)
2
(8.28)
(8.29)
(8.30)
(8.31
2
)
(8.32)
(8.3 5)
G CM id
G CM id
Dm
OV OV OV
ido m D
ido m D
odd m D
id
v V v
v V v
I I Ig
V V V
vv g R
vv g R
vA g R
v
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.2.1 Differential Gain
vi1 = VCM + vid/2 and vi2 = VCM – vid/2 causes a virtual signal ground to appear on the common-source (common-emitter) connection
Current in Q1 increases by gmvid/2 and the current in Q2 decreases by gmvid/2
Voltage amplitudes of gm(RD||ro)vid/2 develop at the two drains
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.2.2. The Differential Half-Circuit
Figure 8.9 (right): The
equivalent differential half-
circuit of the differential
amplifier of Figure 8.8
Here Q1 is biased at I/2 and
is operating at VOV
This circuit may be used to
determine the differential
voltage gain of the
differential amplifier Ad =
vod/vid.
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.2.3 The Differential Amplifier with Current-Source Loads
To obtain higher gain, the passive resistances (RD) can be
replaced with current sources.
Ad = gm1(ro1||ro3)
Figure 8.11: (a) Differential amplifier
with current-source loads formed by
Q3 and Q4. (b) Differential half-circuit
of the amplifier in (a).
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.2.4 Cascode Differential Amplifier
Gain can be increased via cascode configuration –discussed in Section 7.3
Ad = gm1(Ron||Rop)
Ron = (gm3ro3)ro1
Rop = (gm5ro5)ro7
Figure 8.12: (a) Cascode differential
amplifier; and (b) its differential half
circuit.
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ECE 3120 Microelectronics II Dr. Suketu Naik
Common Mode Rejection Ratio (CMRR)
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR)
a) vin = VCM (DC common-mode signal) + vicm (common-mode noise
or interference)
b) current source with fininte output resistance RSS
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR)
c) T model without ro
d) common-mode half circuit
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR)
Equation (8.43) describes effect of common-mode signal (vicm) on vo1 and vo2.
1 2
1 2
2 1
(8.41)
(8.42)
(8.43)
(8.44)
(8.45
2
1/ 2
1/ 2
2
0)
icm SS
m
icm
m SS
Do o icm
m SS
icm Do o
SS
od o o
iv iR
g
vi
g R
Rv v v
g R
v Rv v
R
v v v
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ECE 3120 Microelectronics II Dr. Suketu Naik
When the output is taken single-ended, magnitude of common-mode gain is defined in (8.46) and (8.47)
Taking the output differentiallyresults in the perfectly matched case, in zero Acm (infinite CMRR)
Mismatches between the drain resistances make Acm finite even when the output is taken differentially.
CMRR is the ratio of differential gain over common-mode gain
's aremismatched
1
2
2 1
(8.46)
(8.
2
2
2
47)
(8.48)
(8.49) 2 2
Do icm
SS
D Do icm
SS
Dod o o icm
SS
od D D Dcm
icm SS
RD
SS D
Rv v
R
R Rv v
R
Rv v v v
R
v R R RA
v R R R
( 8.50) d
cm
ACMRR
A
8.2.5 Common-Mode Gain and Common-Mode Rejection ratio (CMRR)
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.4.1 Input Offset Voltage
Apply a small voltage of opposite polarity to cancel the offset
Device mismatches cause a finite dc voltage at the output
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ECE 3120 Microelectronics II Dr. Suketu Naik
BJT Differential Pair
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.3 The BJT Differential Pair
Figure 8.15 shows the basic
BJT differential-pair
configuration
It is similar to the MOSFET
circuit – composed of two
matched transistors biased
by a constant-current source
– and is modeled by similar
expressions.
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.3.1 Basic Operation
Suppose that the two bases joined together and connected to a common-
mode voltage VCM
Since Q1 and Q2 are matched, and assuming an ideal bias current I with
infinite output resistance, this current will flow equally through both
transistors.
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ECE 3120 Microelectronics II Dr. Suketu Naik
Input Common Mode Range
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.3.2 Input Common-Mode Range
The allowable range of VCM
is determined at the upper
end by Q1 and Q2 leaving
the active mode and
entering saturation.
Equations (8.66) and (8.67)
define the minimum and
maximum common-mode
input voltages.
0.4(8.66)
(8.67)
0.42
CM C CC C
CM EE CS BE
IV V V R
V V V V
max
min
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ECE 3120 Microelectronics II Dr. Suketu Naik
Large Signal Operation
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.3.3 Large Signal Operation
(1) Note that the linear
range of BJT diff pair
is smaller than the
MOS diff pair
(2) It can be used for
fast switching (ECL
logic) by current
steering: e.g. current
flows entirely in one
branch then switches
to the other branch;
requires only 4VT
(3) The difference
input signal, vid should
be less than VT/2 to
linear amplification
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ECE 3120 Microelectronics II Dr. Suketu Naik
How to increase the linear range?
Figure 8.18 The transfer characteristics of the BJT differential pair (a) can be linearized (b)
(i.e., the linear range of operation can be extended) by including resistances in the emitters.
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ECE 3120 Microelectronics II Dr. Suketu Naik
Small Signal Operation
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.3.4 Small Signal Operation
)83.8....(2222 e
ide
idm
id
T
cr
vi
vg
v
V
Ii
)80.8......(2 TT
Cm
V
I
V
Ig
Bias voltage
(DC)
+ small
signal (ac)
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.3.4 Small Signal Operation: half-circuit
)95.8)......(||( oCmd rRgA
Virtual
Ground
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.3.4 Small Signal Operation: single-ended input
Note that we can apply
signal in the MOS diff
pair in similar fashion
(1) Emitter voltage is no longer at virtual
ground.
(2) Voltage at the emitters is appx.
Vid /2
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.3.5 Common-mode gain and CMRR
)99.8(),98.8......(22
C
C
EE
C
eEE
Ccm
R
R
R
R
rR
RA
)100.8......(2
C
CEEm
cm R
RRg
A
ACMRR d
CMRR is the ratio of differential gain over common-mode gain
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ECE 3120 Microelectronics II Dr. Suketu Naik
8.4.2 Input Offset Voltage
Apply a small voltage of opposite polarity to cancel the offset
Device mismatches cause a finite dc voltage at the output
VOS smaller than
MOS diff pair
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ECE 3120 Microelectronics II Dr. Suketu Naik
List of Problems
MOS Diff Pair
p8.2: input common mode range of PMOS differential amplifier
ex8.4 MOS diff pair: differential gain
ex8.7 (simulate and verify) MOS diff pair: CMRR
p8.15: design of MOS differential amplifier
BJT Diff Pair
p8.34: input common mode range of npn differential amplifier
ex8.13: BJT diff pair: differential gain, CMRR
p8.49 (simulate): design of BJT differential amplifier
p8.62 (simulation only): npn differential amplifier