diffrential amplifiers

7/28/2019 Diffrential Amplifiers

1/85

Chapter 6

Differential and Multistage Amplifiers

The most widely used circuit building block in analog integrated

circuits.

Use BJTs, MOSFETS and MESFETs (metal semiconductor FET

read 5.12Gallium Arsenide-GaAs Device).


2/85

Differential pair circuits are one of the most

widely used circuit building blocks. The

input stage of every op amp is a differential

amplifier

Basic Characteristics

Two matched transistors with emitters

shorted together and connected to a

current source

Devices must always be in active mode

Amplifies the difference between the

two input voltages, but there is also a

common mode amplification in the non-

ideal case

Lets first understand how this circuit

works.


3/85

Assume the inputs are shorted together to a commonvoltage, vCM, called the common mode voltage

equal currents flow through Q1 and Q2 emitter voltages equal and at v

CM

-0.7 in orderfor the devices to be in active mode

collector currents are equal and so collectorvoltages are also equal for equal load resistors

difference between collector voltages = 0

What happens when we vary vCM?

As long as devices in active mode, equalcurrents flow through Q1 and Q2

Note: current through Q1 and Q2 always add uptoI, current through the current source

So, collector voltages do not change and

difference is still zero. Differential pair circuits thus reject common

mode signals


4/85

Q2 base grounded and Q1 base at +1 V

All current flows through Q1

No current flows through Q2

Emitter voltage at 0.3V and Q2s EBJ not FB

vC1 = VCC-aIRC

vC2= VCC

Q2 base grounded and Q1 base at -1 V

All current flows through Q2

No current flows through Q1 Emitter voltage at -0.7V and Q1s EBJ not

FB

vC2 = VCC-aIRC

vC1 = VCC


5/85

Apply a small signal vi

Causes a small positiveDIto flow in Q1 Requires small negativeDIin Q2

sinceIE1+IE2 =I

Can be used as a linear amplifier for smallsignals (DIis a function ofvi)

Differential pair responds to differences in theinput voltage

Can entirely steer current from one side ofthe diff pair to the other with a relativelysmall voltage

Lets now take a quantitative look at the large-

signal operation of the differential pair


6/85

Large-Signal Operation

First look at the emitter currents when the emitters are tied together

Some manipulations can lead to the following equations

and there is the constraint:

Given the exponential relationship, small differences in vB1,2can cause all of the

current to flow through one side

T

EBVVv

SE e

Ii

1

1a

T

EB

V

Vv

SE e

Ii

2

2a

T

BB

Vvv

E

E ei

i 21

2

1

T

BB

V

vv

EE

E

eii

i12

1

121

1

T

BB

V

vv

EE

E

eii

i21

1

121

2

Iii EE 21

T

BB

V

vvE

e

Ii

12

1

1

T

BB

V

vvE

e

Ii

21

1

2


7/85

Notice vB1-vB2 ~= 4VT enough to switch all of current from one side tothe other

For small-signal analysis, we are interested in the region we can

approximate to be linear

small-signal condition: vB1-vB2 < VT/2


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Small-Signal Operation

Look at the small-signal operation: small

differential signal vd

is applied

expand the exponential and keep the

first two terms

T

d

V

vC

e

Ii

1

1

adBB vvv 21

T

d

T

d

T

d

V

v

V

v

V

v

C

ee

Iei

22

2

1

a

2222121

211

d

TTdTd

TdC

v

V

II

VvVv

VvIi

aaa

222

2d

T

C

v

V

IIi

aa

22

d

T

c

v

V

Ii

a

TT

Cm

V

I

V

Ig

2a

2dmc vgi

multiply topand bottom

byT

d

V

v

e2


9/85

Differential Voltage Gain

For small differential input signals, vd


10/85

Differential Half Circuit

We can break apart the differential pair circuit into two half circuitswhich

then looks like two common emitter circuits driven by +vd/2 andvd/2


11/85

We can then analyze the small-signal operation with the half

circuit, but must remember

parameters rp,gm, and ro are biased at I/2

input signal to the differential half circuit is vd/2

voltage gain of the differential amplifier (output taken

differentially) is equal to the voltage gain of the half circuit

oCmd

cd rRg

v

vA

2

1

vd/2 rp vp

gm

vpr RC

vc1


12/85

Common-Mode Gain

When we drive the differential pair with a common-mode signal,

vCM, the incremental resistance of the bias current effects circuitoperation and results in some gain (assumed to be 0 when R

was infinite)

R

Rv

rR

Rvv CCM

e

CCMC

221

aa

R

Rvv CCMC 22

a


13/85

If the output is taken differentially, the output is zero since both sides movetogether. However, if taken of the single circuit, the common-mode gain is finite

If we look at the differential gain of the circuit, we get

Then, the common rejection ratio (CMRR) will be

which is often expressed in dB

R

RA Ccm

2

a

Cmd RgA

RgA

ACMRR m

cm

d

2

1

cm

d

A

ACMRR 10log20


14/85

CM and Differential Gain Equation

Input signals to a differential pair usually consists of two

components: common mode (vCM) and differential(vd)

Thus, the differential output signal will be in general

2

21 vvvCM

21 vvvd

2

2121

vvAvvAv cmdo


15/85

The BJT Differential Pair

Use CD

Implemented by a

transistor circuit

Connection to RC not

essential to the operation

Essential that Q1

and Q2 never enter

saturation


16/85

Different Modes of Operation

Differential pair with a common-mode input

Common voltage

I/2

vE = vCM-VBE

vC1 = VCC( ) a I RC

vC2 = VCC( ) a I RC

vC1vC2 = ?

Vary vCM (what happens?)

Rejects common-mode


17/85

Differential pair with a large differential input


vB1 = +1

Q1

Q2

vE = 0.3

Keeps Q2 off

vC1 = VCC - a I RC

vC2 = VCC


18/85

Differential pair with a large differential input o opposite polarity

To that of (b)



19/85

Differential pair with a small differential input



20/85

Exercise 6.1

5 0.71

4. 3 vE 0.7

vC2 5 4.31 vC2 0.7

vC1 5


21/85

Large-Signal Operation of the BJT Differential Pair

Equations

iE1IS

ae

vB1 vE( )

VT

iE2IS

ae

vB2 vE( )

VT

iE1

iE2e

vB1 vB2( )

VT

iE1

iE1 iE2

1

1 e

vB2 vB1( )

VT

iE2

iE1 iE2

1

1 e

vB1 vB2( )

VT

iE11

1 e

vB2 vB1( )VT

iE21

1 e

vB1 vB2( )

VT

Which can be manipulated to yield

iE1 iE2 I

I

I

The collector

currents

can be obtained by

multiplying the

emitter currents by

Alfa, which is ver

close to unity


22/85

Large-Signal Operation of the BJT Differential Pair

Relatively small

difference voltage vB1

vB2 will cause the

current I to flow almost

entirely in one of the two

transistors.

4.VT (~100mV) is

sufficient to switch the

current to one side of the

pair.


23/85

Small-Signal Operation

The Collector Currents When vdis applied

vd vB1 vB2

iC1a I

1 e

vd

VT

iC2a I

1 e

vd

VT iC1

a I e

vd

2 VT

e

vd

2 VTe

vd

2 VT

vd

2 VT

iC1

a I 1vd

2 VT

1vd

2 VT 1

vd

2 VT

iC1

a I 1vd

2 VT

1vd

2 VT 1

vd

2 VT

~

iC2a I

2

a I2 VT

vd

2 iC1 a

I2

a I2 VT

vd

2

vBQ1 VBEvd

2 vBQ2 VBE

vd

2 gm

IC

VT

a I

2

VT

ic

Multiplying by

Assuming vd


24/85

An Alternative Viewpoint

reVT

IE

VT

I

2

ievd

2 re

Assume I to be idealits incremental resistance will be infinite and vd appears across a total

resistance 2.re.

ic a iea vd

2 re gmvd

2

A simple technique for

determining the signal currentsin a differential amplifier

excited by a differential voltage

signal vd; dc quantities are not

shown.


25/85

If emitter resistors are included

A differential amplifier with emitter resistances. Only signal quantities are shown (on color).


26/85

Input Differential Resistance

ibie

1

vd

2 re

1

Ridvd

ib 1 2 re 2 r p

This is the resistance-reflection rule; the resistance seen between the two bases is

equal to the total resistance in the emitter circuit multiplied by the beta+1


27/85


28/85

Differential Voltage Gain

iC1 IC gm

vd

2 iC2 IC gmvd

2 ICa I

2

vC1 VCC IC RC( ) gm RCvd

2

vC2 VCC IC RC( ) gm RCvd

2

Advc1 vc2

vdgm RC

Ada 2RC( )

2 re 2 RE( )

RC

re REAd

a 2RC( )

2 re 2 RE( )

RC

re RE

The voltage gain is equal to the

ratio of the total resistance in the

collector circuit (2RC) to the total

resistance in the emitter circuit

(2re+2RE)

~


29/85

Equivalence of the differential amplifier (a) to the two common-emitter amplifiers in (b). Thisequivalence applies only for differential input signals. Either of the two common-emitter

amplifiers in (b) can be used to evaluate the differential gain, input differential resistance,

frequency response, and so on, of the differential amplifier.

Equivalence of the Differential Amp. To a Common-Emitter Amp.

Differential amplifier fed in a

complementary manner

(push-pull or balanced)

Base of Q1 raised

Based of Q2 lowered


30/85

Equivalent Circuit Model of a Differential Half-Circuit

Ad gmRC ro

RC ro


31/85

Common-Mode Gain

vc1 vCMa RC

2 R re

vCMa RC

2 R

vc2 vCMa RC

2 R

Acma RC

2 R

Ad1

2

gm RC

CMRRAd

Acm

Assuming symmetry

AcmRC

2 R

RC

RC vCM

v1 v2

2

vo Ad v1 v2( ) Acm v1 v22

If output is taken single-endedly

Acm and the differential gain AdWe can define CMRR

CMRR gm R a 1

Common-mode

half-circuits

Assuming non-symmetry


32/85

Input Common-Mode Resistance

vCM ro

Ricm =

Ricm

2 . Ricm

vCM

Equivalent common-mode half-circuit

Since the input common-mode resistance

is usually very large, its value will be

affected by the transistor resistancesR0 and rm


33/85

Example 6.1Class Discussion


34/85

Example 6.3

I 1 VCC 15 RC 10 a 1

vB1 t( ) 5 0.005sin 2 p 1000 t

vB2 t( ) 5 0.005sin 2 p 1000 t vBE 0.7 at 1mA

a) vE b) gm c) iC d) vC e) vc1-vc2 f) gain at 1000H


35/85

a )

VBE 0 .7 0 .0 25ln0. 5

1

VBE 0.683

vE 5 VBE vE 4. 317

b )

gmIC

VT gm 20

c )

iC1 t( ) 0. 5 gm 0. 005sin 2 p 1000 t iC2 t( ) 0. 5 gm 0. 005sin 2 p 1000 t

0 0.001 0.002 0.003 0.004 0.0050.3

0.4

0.5

0.6

iC1 t( )

iC2 t( )

t


36/85


37/85


38/85

Exercise 6.4

100

Delta_RC 0.02 Delta_IS 0.1 Delta_ 0.1 I 100 mA

From Eq. 6.55

VOS VTDelta_RC

RC

2Delta_IS

IS

2

VOS 25 0.02( )2

0.12

VOS 2.55

IB

I

2 1 I B 0. 495 mA

IOS IBDelta_

I OS 4. 95 104

50nA


39/85


40/85

Exercise 6.5

R incremental = r p // (1/gm) // ro

Rinc

rp1

gm

rp1

gm

ro

rp1

gm

rp1

gm

ro

rp

1ro

rp

1ro

re ro

re ror Rinc

25

0. 5

Rinc 5 0


41/85

The Current Mirror

Io

IO

1IE IREF

2

1 I

IO

IREF

2

1

12

I O

I REF

12

1V O V EE V BE

VA

Finite Beta and Early Effect

For what value of would

current mirror have a gain error

1%, 0.1 %

Imperfection due to base

current diverted from reference

current IREF


42/85

Exercise 6.6

IO5 1 .0 73 1 0

3

IO5 IO5 4.3( )

RoutVO 5at

IO 9.80 4 104

IO

IREF

12

VO 4. 3VO VEE VBEVO VBat

Rout 1 10

5

Rout100

IREF

Rout roVA

IREF

IREF 0.001 10 0VBE 0. 7VEE 5


43/85

A Simple Current Source

I REF

V CC V BE

R

VCC

VBE

Neglecting the effect of finite beta and

Dependence of Io and Vo, the output

current Io will be equal IREF

IoIREF


44/85

Exercise 6.7

I

O

I

REF

I

REF

0.001 VCC

5 VBE

0.7

neglect the effects ro and f inite Beta 100 VA 50

roVA

IREF

ro 5 104

R

VCC VBE

IREF

R 4.3 103

at VO 3 IO

I

REF

12

V

O

V

BE

ro IO 1.026 10 3


45/85


46/85

Exercise 6.9


47/85

Comparison With MOS Circuits

1 - The MOS mirror does not suffer from the finite Beta

2Ability to operate close to the power supply is an important issue on IC design

3 - Current Transfer: BJTs ~ relative areas; MOS ~ W/L4 - VA lower for MOS

Improved Current-Source Circuits IREF

1

2

1 2

IE

IO

1IE

IO

IREF

1

12

2

1

12

2

IREF

VCC VEB1 VBE3

R


48/85

The Wilson Current Mirror

Output resistance equal

A factor greater the then simple

Current source

Disadvantage: reduced output swing.

Observe that the voltage at the collector at

Q3 has to be greater than the negative

supply voltage by

(vBB1 = VCEsat-3), which is about a volt.

ro

2


49/85

Exercise 6.10

I I

I E

1

I E

1

2 I E

1

I E

1 I E

1

2

1I

2

1 2

I

2

1

2I

~

IREF 1 2 1

2

IE

IO 2

1 2IE

IO

IREF

2

2 2

IO

IREF

1

12

2


50/85

Widlar Current SourceIt differs from the basic current mirror in an

important way: a resistor RE is included in

the emitter lead of Q2. Neglecting the base

current we can write:

VB1 VT lnIREF

IS

VB2 VT lnIO

IS

VB1 VB2 VT lnIREF

IO

VB1 VB2 IO RE

IO RE VT lnIREF

IO


51/85

Example 6.2

E ample 6 3


52/85

Example 6.3

Example 6 3


53/85

Example 6.3

Multistage AmplifiersExample 6.4pg. 552


54/85

Current sources for biasing amplifying stages

g p

Calculating 1st stage gain

-- Assuming 100

Model Eqs. on Pg. 263

er

In the same manor

W

k

rRi

05.5)25101(2

)1(22 p

542 pp rrRi

W krrRid 2.2021 pp

W

krrr e

1.10100*101))(1(21 pp

W10025.

25

21 E

T

I

V

ee rr

)()()(

1

pE

T

C

T

m I

V

I

V

gr



55/85

g p

Calculating 1st stage gain

V

V

kk

rr

RRR

RI

RI

v

v

ee

i

RTotalEE

RTotalCC

id

oA

4.22

200

40||05.5

)||(

1

21

212

__

__1

WWW

1

Ri2

Total emitter resistance

Total collector resistance



56/85

g p

Calculating 2nd stage gain

VVkk

rrRR

ee

iA 2.59508.234||3||

2 54

33

W WW

Ri3

re4 and re5 calc. before

Potential gain is halved b/c converting to single-ended output

))(1( 743 ei rRR

W 251

257 C

T

I

V

er

WWW

kkRi

8.234)253.2(1013



57/85

Calculating 3rd stage gain

Purpose is to allow amplified

signal to swing negatively

Ri4

W 55

258er

W

k

RrR ei

5.303)30005(101

))(1( 684

VV

k

kk

Rr

RR

v

v

e

i

o

oA 24.6325.2

5.303||7.15||

3 47

45

2

3 WWW



58/85

Calculating 3rd stage gain

V

V

Rr

R

v

v

eo

oA

998.30053000

4 68

6

3

Overall Gain

VV

v

vAAAAA

id

o 85134321

W

152)(||186

5

R

eo

rRROutput Resistance


59/85

The BJT Differential Amplifier With Active Load

vo gm vd Ro

Ro

ro2 ro4

ro2 ro4ro2 ro4 ro

Ro

ro

2vo gm vd

ro

2

v

ovd

g

m

r

o

2

gm

IC

VT

ro

VA

IC

ICI

2

gm ro

VA

VT

constant for a given transito

Ri 2 rp Gm gm

I

2

VT


60/85

The Cascode Configuration


61/85

The Cascode Configuration


62/85

BJT Single Stage Common-Emitter Amplifier
http://jas2.eng.buffalo.edu/applets/education/ckt/comEmitAmp/index.htmlhttp://jas2.eng.buffalo.edu/applets/education/ckt/comEmitAmp/index.htmlhttp://jas2.eng.buffalo.edu/applets/education/ckt/comEmitAmp/index.htmlhttp://jas2.eng.buffalo.edu/applets/education/ckt/comEmitAmp/index.html


63/85

MOSFET Operation

MOS Diff i l A lifi MOS Diff i l P i
http://jas2.eng.buffalo.edu/applets/education/mos/mosfet/mosfet.htmlhttp://jas2.eng.buffalo.edu/applets/education/mos/mosfet/mosfet.html


64/85

MOS Differential AmplifiersMOS Differential Pair

MOS Differential Amplifiers Offset Voltage


65/85

MOS Differential AmplifiersOffset Voltage

MOS Differential Amplifiers Current Mirrors


66/85

MOS Differential AmplifiersCurrent Mirrors

Problem 6 1


67/85

Problem 6.1

RC 3000 vBE 0. 7 iC 0. 001 vCM 2 VCC 5 10

at iC 0 .0 00 5 v BE 0 .7 0 .0 25ln0. 5

1

v BE 0 .6 83

vE vCM vBE vE 2.683

iC1

1

iC iC1 4. 95 104

vC1 VC C iC1 RC v C1 3 .5 15

Problem 6 15


68/85

Problem 6.15

Ad 40Advc2 vc1

vd

vc2 2vc2 ie RCvc1 2vc1 ie RC

iE2 6 10

4

iE2 IE ie

iE1 1.4 103

iE1 IE ie

ie 4 104

ievd

2 re RE( )

RC 500I E 0.001RE 100re 25vd 0.1


69/85

BJT Differential Amplifier Laboratory

Purpose

The purpose of this lab is to investigate the behavior of a BJT difference amplifier. The circuits behavior needs to be

modeled with theoretical equations and a computer simulation. Comparison of laboratory results with theoretical and

simulated results is required for the relative validity of the models.

This lab also investigates the variation of differential and common mode gains using a Monte Carlo analysis.

Procedure

Construct the circuit in Figure 1 on PSpice and a Jameco JE26 Breadboard using a Hewlett-Packard 6205 Dual DC Power

Supply as the voltage sources and an MPQ2222 Bipolar Junction Transistor (Q2N2222).

Using a Keithley 169 Digital Multi-Meter measure the voltages across the resistors to determine the transistor base current

and collector current. From these current values calculate .

Figure 1) Circuit for testing transistor value


70/85

Next construct the amplifier

circuit shown in Figure 2.

All transistors are

MPQ2222 Bipolar Junction

Transistors. Use PSpice toconstruct the circuit.

Measure the DC values at the

collector of Q1 and Q2. Do

the measured values agree

with theoretical ones.

Measure the DC value at the

emitter of Q1 and Q2. Do

the measured value agree

with the theoretical one.

Indicate the inverting and non-

inverting output.

Input an AC signal into Q1 of

your circuit at frequencies .

What is the single voltage

gain of your circuit?

Figure 2


71/85

Both inputs (Vin1 and Vin2) should be then grounded in order to determine the DC

operating point of the amplifier. Bias point voltages are measured and then compared to

the bias points produced by the PSpice simulation. Record DC bias point data.

Use a Wavetek 190 Function Generator with a sinusoidal input voltage of amplitude 0.031 V

and apply to one of the input terminals and the other terminal remained grounded, as shown

in figure 2. Use a Tektronix TDS 360 Digital Oscilloscope and a Fluke 1900A Multi-Meter the

output of the amplifier to observe input signal frequencies. Determine the corner frequency

(3-dB point) of the output and compared with the corner frequency generated with an AC

sweep in PSpice. Plot the PSpice AC sweep simulation.

Next calculate the differential mode voltage gain, AV-dm, from the laboratory data andcompare to the AV-dm predicted by the PSpice simulation and theoretical equations. Both

inputs are tied together to create a common mode signal on the input terminals. The output

voltage is then used to calculate the common mode voltage gain, AV-cm, and then compared

to the AV-cm predicted by the PSpice simulation and theoretical equations. From these

values the common mode rejection ratio (CMRR) should be calculated for each case.

Finally, PSpice should be used to perform a Monte Carlo analysis of the circuit. The

resistors were all given standard unbridged values and were allowed to vary uniformly

within 5% of the nominal resistor value. The transistors should be given a nominal value

(say 175) and allowed to vary uniformly to +/- 100. The variations of differential and

common mode gains should be graphed on two histograms.


72/85

Analysis / Questions

What are the values of for the first transistor?

(typical values of range from approximately 125 to 225)

With the exception of the Monte Carlo analysis, all transistors were assumed to have this value in the

PSpice simulations. All four transistors were contained within one integrated circuit so that hopefully there

would be little change in values from one transistor to the next, making the previous assumption

reasonably valid.

How close are the measured DC bias points of the circuit to those predicted by the PSpice simulation?

What is the reason for the small differences between measured and predicted voltages?

Exercises 6 17


73/85

Exercises 6.17

An Active-Loaded CMOS Amplifier


74/85

An Active Loaded CMOS Amplifier

Exercise 6.19

BiCMOS Amplifiers


75/85

BiCMOS Amplifiers

Exercise 6.20

BiCMOS Amplifiers


76/85

BiCMOS Amplifiers

Exercise 6.21

BiCMOS Amplifiers


77/85

C OS p e s

Exercise 6.22

BiCMOS Current Mirrors and Differential Amplifiers


78/85

p

Gallium Arsenide (GaAs) Amplifiers


79/85

( ) p

Current sourcesExercise 6.23



80/85

( ) p

A Cascode Current SourceExercise 6.24



81/85

( ) p

Increasing The Output Resistance by Bootstrapping



82/85

( ) p

A Simple Cascode ConfigurationThe Composite Transistor



83/85

( ) p

Differential Amplifiers

Multistage Amplifiers


84/85

g p

Example 6.4

Multistage Amplifiers


85/85

Example 6.5 SPICE Simulation of a Multistage Amplifier

diffrential amplifiers

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