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Flip-flop (electronics)

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#Redirected from $ flip flops%Jump to& na'i(ation" searchThis article is about the electronic component. For other meanings, see flip-flop(disambiguation).

lip)flop schematics from the *ccles and Jordan patent filed +,+-" one drawn as a cascade ofamplifiers with a positi'e feedback path" and the other as a symmetric cross)coupled pair

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n di(ital circuits" a flip-flop is a term referrin( to an electronic circuit #a bistable multi'ibrator %that has two stable states and thereby is capable of ser'in( as one bit of memory. /oday" the term flip-flop has come to mostly denote non-transparent #clocked or edge-triggered % de'ices" whilethe simpler transparent ones are often referred to as latches0 howe'er" as this distinction is 1uitenew" the two words are sometimes used interchan(eably #see history%.

2 flip)flop is usually controlled by one or two control si(nals and3or a (ate or clock si(nal. /heoutput often includes the complement as well as the normal output. 2s flip)flops areimplemented electronically" they re1uire power and (round connections.

Contents

[hide

• + History

• 4 mplementation

• 5 Set6reset flip)flops #SR flip)flops%

• 7 /o((le flip)flops #/ flip)flops%

• 8 J9 flip)flop

• : $ flip)flop

• ; Master6sla'e #pulse)tri((ered% $ flip)flop

o ;.+ *d(e)tri((ered $ flip)flop

• - lip)flop inte(rated circuits

• ++ See also

• +4 ?otes

• +5 References

http://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Electronic_circuithttp://en.wikipedia.org/wiki/Bistablehttp://en.wikipedia.org/wiki/Bistablehttp://en.wikipedia.org/wiki/Multivibratorhttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Computer_storagehttp://en.wikipedia.org/wiki/Latch_(electronics)http://en.wikipedia.org/wiki/Signalshttp://en.wikipedia.org/wiki/Clock_signalhttp://en.wikipedia.org/wiki/Outputhttp://en.wikipedia.org/wiki/Complementhttp://en.wikipedia.org/wiki/Complementhttp://en.wikipedia.org/wiki/Electric_powerhttp://en.wikipedia.org/wiki/Ground_(electricity)http://en.wikipedia.org/wiki/Ground_(electricity)http://toggletoc%28%29/http://en.wikipedia.org/wiki/D_flip_flops#Historyhttp://en.wikipedia.org/wiki/D_flip_flops#Implementationhttp://en.wikipedia.org/wiki/D_flip_flops#Set.E2.80.93reset_flip-flops_.28SR_flip-flops.29http://en.wikipedia.org/wiki/D_flip_flops#Toggle_flip-flops_.28T_flip-flops.29http://en.wikipedia.org/wiki/D_flip_flops#JK_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#D_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#Master.E2.80.93slave_.28pulse-triggered.29_D_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#Master.E2.80.93slave_.28pulse-triggered.29_D_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#Edge-triggered_D_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#Useshttp://en.wikipedia.org/wiki/D_flip_flops#Chaoshttp://en.wikipedia.org/wiki/D_flip_flops#Flip-flop_integrated_circuitshttp://en.wikipedia.org/wiki/D_flip_flops#See_alsohttp://en.wikipedia.org/wiki/D_flip_flops#See_alsohttp://en.wikipedia.org/wiki/D_flip_flops#Noteshttp://en.wikipedia.org/wiki/D_flip_flops#Referenceshttp://en.wikipedia.org/wiki/D_flip_flops#Referenceshttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Electronic_circuithttp://en.wikipedia.org/wiki/Bistablehttp://en.wikipedia.org/wiki/Multivibratorhttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Computer_storagehttp://en.wikipedia.org/wiki/Latch_(electronics)http://en.wikipedia.org/wiki/Signalshttp://en.wikipedia.org/wiki/Clock_signalhttp://en.wikipedia.org/wiki/Outputhttp://en.wikipedia.org/wiki/Complementhttp://en.wikipedia.org/wiki/Electric_powerhttp://en.wikipedia.org/wiki/Ground_(electricity)http://toggletoc%28%29/http://en.wikipedia.org/wiki/D_flip_flops#Historyhttp://en.wikipedia.org/wiki/D_flip_flops#Implementationhttp://en.wikipedia.org/wiki/D_flip_flops#Set.E2.80.93reset_flip-flops_.28SR_flip-flops.29http://en.wikipedia.org/wiki/D_flip_flops#Toggle_flip-flops_.28T_flip-flops.29http://en.wikipedia.org/wiki/D_flip_flops#JK_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#D_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#Master.E2.80.93slave_.28pulse-triggered.29_D_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#Edge-triggered_D_flip-flophttp://en.wikipedia.org/wiki/D_flip_flops#Useshttp://en.wikipedia.org/wiki/D_flip_flops#Chaoshttp://en.wikipedia.org/wiki/D_flip_flops#Flip-flop_integrated_circuitshttp://en.wikipedia.org/wiki/D_flip_flops#See_alsohttp://en.wikipedia.org/wiki/D_flip_flops#Noteshttp://en.wikipedia.org/wiki/D_flip_flops#References


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[edit] History

/he first electronic flip)flop was in'ented in +,+- by William *ccles and . W. Jordan.[+[4 t wasinitially called the ccles!"ordan trigger circuit and consisted of two acti'e elements #radio)tubes%. /he name flip)flop was later deri'ed from the sound produced on a speaker connected to

one of the back coupled amplifiers outputs durin( the tri((er process within the circuit #as such"it may be considered a case of onomatopoeia%.[citation needed /his ori(inal electronic flip)flop@asimple two)input bistable circuit without any dedicated clock #or e'en (ate% si(nal" wastransparent " and thus a de'ice that would be labeled as a AlatchA in many circles today.

/he flip)flop types discussed below #$" RS" J9" /% were first discussed in a +,87


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other types by a few lo(ic (ates. /he beha'ior of a particular type can be described by what istermed the characteristic e1uation" which deri'es the AneEtA #i.e." after the neEt clock pulse%

output" 'net " in terms of the input si(nal#s% and3or the current output" '.

[edit] Setreset flip-flops (SR flip-flops)

/he symbol for an SR latch.

/he fundamental latch is the simple * flip-flop " where S and R stand for set and reset

respecti'ely. t can be constructed from a pair of cross)coupled ?2?$ or ?R lo(ic (ates. /hestored bit is present on the output marked K.

?ormally" in stora(e mode" the S and R inputs are both low" and feedback maintains the K and Koutputs in a constant state" with K the complement of K. f S is pulsed hi(h while R is held low"then the K output is forced hi(h" and stays hi(h e'en after S returns low0 similarly" if R is pulsedhi(h while S is held low" then the K output is forced low" and stays low e'en after R returns low.

SR Flip-Flop operation (!"I#T $ITH %&R 'TS) [:

C*aracteristic ta+le ,citation ta+le

S R ction (t) (t./) S R ction

> > 9eep state > > > L ?o chan(e

> + K > > + + > reset

+ > K + + > > + set

+ + race condition

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#NLN denotes a $onNt care condition0 meanin( the si(nal is irrele'ant%

[edit] To00le flip-flops (T flip-flops)

2 circuit symbol for a /)type flip)flop" where O is the clock input" / is the to((le input and K isthe stored data output.

f the / input is hi(h" the / flip)flop chan(es state #Ato((lesA% whene'er the clock input isstrobed. f the / input is low" the flip)flop holds the pre'ious 'alue. /his beha'ior is described bythe characteristic e1uation&

#or" without benefit of the LR operator" the e1ui'alent&

%

and can be described in a truth table&

T Flip-Flop operation [:


T Q Qnext Comment Q Qnext T Comment

> > > hold state#no clk% > > > ?o chan(e

> + + hold state#no clk% + + > ?o chan(e

+ > + to((le > + + =omplement

+ + > to((le + > + =omplement

http://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=4http://en.wikipedia.org/wiki/Equationhttp://en.wikipedia.org/wiki/Equationhttp://en.wikipedia.org/wiki/XOR_gatehttp://en.wikipedia.org/wiki/Truth_tablehttp://en.wikipedia.org/wiki/D_flip_flops#cite_note-manokime-5http://en.wikipedia.org/wiki/State_transition_tablehttp://en.wikipedia.org/wiki/Excitation_tablehttp://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=4http://en.wikipedia.org/wiki/Equationhttp://en.wikipedia.org/wiki/XOR_gatehttp://en.wikipedia.org/wiki/Truth_tablehttp://en.wikipedia.org/wiki/D_flip_flops#cite_note-manokime-5http://en.wikipedia.org/wiki/State_transition_tablehttp://en.wikipedia.org/wiki/Excitation_table


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When / is held hi(h" the to((le flip)flop di'ides the clock fre1uency by two0 that is" if clockfre1uency is 7 MHD" the output fre1uency obtained from the flip)flop will be 4 MHD. /his Ndi'ide byN feature has application in 'arious types of di(ital counters. 2 / flip)flop can also be builtusin( a J9 flip)flop #J G 9 pins are connected to(ether and act as /% or $ flip)flop #/ input andK pre'ious is connected to the $ input throu(h an LR (ate%.

[edit] JK flip-flop

J9 flip)flop timin( dia(ram

/he JK flip)flop au(ments the beha'ior of the SR flip)flop #JSet" 9Reset% by interpretin( the

S R + condition as a AflipA or to((le command. Specifically" the combination J +" 9 > is acommand to set the flip)flop0 the combination J >" 9 + is a command to reset the flip)flop0and the combination J 9 + is a command to to((le the flip)flop" i.e." chan(e its output to thelo(ical complement of its current 'alue. Settin( J 9 > does ?/ result in a $ flip)flop" butrather" will hold the current state. /o synthesiDe a $ flip)flop" simply set 9 e1ual to thecomplement of J. /he J9 flip)flop is therefore a uni'ersal flip)flop" because it can be confi(uredto work as an SR flip)flop" a $ flip)flop" or a / flip)flop. ?/*& /he flip flop is positi'e ed(etri((ered #=lock Culse% as seen in the timin( dia(ram.

2 circuit symbol for a J9 flip)flop" where O is the clock input" J and 9 are data inputs" K is thestored data output" and KN is the in'erse of K.

/he characteristic e1uation of the J9 flip)flop is&

and the correspondin( truth table is&

JK Flip Flop operation [:

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J K ne,t Comment ne,t J K Comment

> > hold state > > > L ?o chan(e

> + reset > + + L Set

+ > set + > L + Reset

+ + to((le + + L > ?o chan(e

[edit] D flip-flop

$ flip)flop symbol

/he K output always takes on the state of the $ input at the moment of a risin( clock ed(e #orfallin( ed(e if the clock input is acti'e low%.[; t is called the D flip)flop for this reason" since theoutput takes the 'alue of the D input or $ata input" and $elays it by one clock count. /he $ flip)flop can be interpreted as a primiti'e memory cell" Dero)order hold" or delay line.

/ruth table&

Cloc1 D pre2

Risin( ed(e > > L

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Risin( ed(e + + L

?on)Risin( L K pre'

#NLN denotes a $on+t care condition" meanin( the si(nal is irrele'ant%

5)bit shift re(ister

/hese flip flops are 'ery useful" as they form the basis for shift re(isters" which are an essential part of many electronic de'ices. /he ad'anta(e of the $ flip)flop o'er the $)type latch is that itAcapturesA the si(nal at the moment the clock (oes hi(h" and subse1uent chan(es of the data linedo not influence K until the neEt risin( clock ed(e. 2n eEception is that some flip)flops ha'e aNresetN si(nal input" which will reset K #to Dero%" and may be either asynchronous or synchronouswith the clock.

/he abo'e circuit shifts the contents of the re(ister to the ri(ht" one bit position on each acti'etransition of the clock. /he input L is shifted into the leftmost bit position.

[edit] 3astersla2e (p4lse-tri00ered) D flip-flop

2 master6sla'e $ flip)flop is created by connectin( two (ated $ latches in series" and in'ertin(the enable input to one of them. t is called master6sla'e because the second latch in the seriesonly chan(es in response to a chan(e in the first #master% latch.

/he term pulse-triggered means that data are entered on the risin( ed(e of the clock pulse" butthe output doesnNt reflect the chan(e until the fallin( ed(e of the clock pulse.

2 master sla'e $ flip flop. t responds on the ne(ati'e ed(e of the enable input #usually a clock%.

or a positi'e)ed(e tri((ered master6sla'e $ flip)flop" when the clock si(nal is low #lo(ical >%the PenableQ seen by the first or PmasterQ $ latch #the in'erted clock si(nal% is hi(h #lo(ical +%./his allows the PmasterQ latch to store the input 'alue when the clock si(nal transitions from lowto hi(h. 2s the clock si(nal (oes hi(h #> to +% the in'erted PenableQ of the first latch (oes low #+to >% and the 'alue seen at the input to the master latch is PlockedQ. ?early simultaneously" the

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twice in'erted PenableQ of the second or Psla'eQ $ latch transitions from low to hi(h #> to +%with the clock si(nal. /his allows the si(nal captured at the risin( ed(e of the clock by the nowPlockedQ master latch to pass throu(h the Psla'eQ latch. When the clock si(nal returns to low #+to >%" the output of the Asla'eA latch is AlockedA" and the 'alue seen at the last risin( ed(e of theclock is held while the PmasterQ latch be(ins to accept new 'alues in preparation for the neEt

risin( clock ed(e.

2n implementation of a master6sla'e $ flip)flop that is tri((ered on the positi'e ed(e of theclock.

y remo'in( the left)most in'erter in the abo'e circuit" a $)type flip flop that strobes on the falling edge of a clock si(nal can be obtained. /his has a truth table like this&

D 5 ne,t

> L allin( >

+ L allin( +

Most $)type flip)flops in =s ha'e the capability to be set and reset" much like an SR flip)flop.


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y settin( S R >" the flip)flop can be used as described abo'e.

[edit] d0e-tri00ered D flip-flop

2 more efficient way to make a $ flip)flop is not so easy to understand" but it works the same

way. While the master6sla'e $ flip flop is also tri((ered on the ed(e of a clock" its componentsare each tri((ered by clock le'els. /he Aed(e)tri((ered $ flip flopA does not ha'e the mastersla'e properties.

2 positi'e)ed(e)tri((ered $ flip)flop.

[edit] "ses

• 2 sin(le flip)flop can be used to store one bit" or binary di(it" of data. See preset.

• 2ny one of the flip)flop types can be used to build any of the others.

• Many lo(ic synthesis tools will not use any other type than $ flip)flop and $ latch.

• Be'el sensiti'e latches cause problems with Static /imin( 2nalysis #S/2% tools and$esi(n or /est #$/%. /herefore" their usa(e is often discoura(ed.

• Many CI2 de'ices contain only ed(e)tri((ered $ flip)flops

• /he data contained in se'eral flip)flops may represent the state of a se1uencer" the 'alueof a counter " an 2S= character in a computerNs memory or any other piece of

information.

• ne use is to build finite state machines from electronic lo(ic. /he flip)flops rememberthe machineNs pre'ious state" and di(ital lo(ic uses that state to calculate the neEt state.

• /he / flip)flop is useful for constructin( 'arious types of counters. Repeated si(nals tothe clock input will cause the flip)flop to chan(e state once per hi(h)to)low transition ofthe clock input" if its / input is A+A. /he output from one flip)flop can be fed to the clock

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input of a second and so on. /he final output of the circuit" considered as the array ofoutputs of all the indi'idual flip)flops" is a count" in binary" of the number of cycles of thefirst clock input" up to a maEimum of 4n)+" where n is the number of flip)flops used. See&=ounters

o

ne of the problems with such a counter #called a ripple counter % is that theoutput is briefly in'alid as the chan(es ripple throu(h the lo(ic. /here are twosolutions to this problem. /he first is to sample the output only when it is knownto be 'alid. /he second" more widely used" is to use a different type of circuitcalled a synchronous counter . /his uses more compleE lo(ic to ensure that theoutputs of the counter all chan(e at the same" predictable time. See& =ounters

• re1uency di'ision& a chain of / flip)flops as described abo'e will also function to di'idean input in fre1uency by 4n" where n is the number of flip)flops used between the inputand the output.

2 flip)flop in combination with a Schmitt tri((er can be used for the implementation of an arbiter in asynchronous circuits.

=locked flip)flops are prone to a problem called metastability" which happens when a data orcontrol input is chan(in( at the instant of the clock pulse. /he result is that the output may beha'e unpredictably" takin( many times lon(er than normal to settle to its correct state" or e'enoscillatin( se'eral times before settlin(. /heoretically it can take infinite time to settle down. n acomputer system this can cause corruption of data or a pro(ram crash.

lip)flop setup" hold and clock)to)output timin( parameters.

/he metastability in flip)flops can be a'oided by ensurin( that the data and control inputs are

held 'alid and constant for specified periods before and after the clock pulse" called the set4ptime #tsu% and the *old time #th% respecti'ely. /hese times are specified in the data sheet for thede'ice" and are typically between a few nanoseconds and a few hundred picoseconds for modernde'ices.


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le'el" dependin( on the re1uired reliability of the circuit. ne techni1ue for suppressin(metastability is to connect two or more flip)flops in a chain" so that the output of each one feedsthe data input of the neEt" and all de'ices share a common clock. With this method" the probability of a metastable e'ent can be reduced to a ne(li(ible 'alue" but ne'er to Dero. /he probability of metastability (ets closer and closer to Dero as the number of flip)flops connected in

series is increased.

So)called metastable)hardened flip)flops are a'ailable" which work by reducin( the setup andhold times as much as possible" but e'en these cannot eliminate the problem entirely. /his is because metastability is more than simply a matter of circuit desi(n. When the transitions in theclock and the data are close to(ether in time" the flip)flop is forced to decide which e'enthappened first. Howe'er fast we make the de'ice" there is always the possibility that the inpute'ents will be so close to(ether that it cannot detect which one happened first. t is thereforelo(ically impossible to build a perfectly metastable)proof flip)flop.

2nother important timin( 'alue for a flip)flop #3% is the clock)to)output delay #common

symbol in data sheets& t=% or propa(ation delay #tC%" which is the time the flip)flop takes tochan(e its output after the clock ed(e. /he time for a hi(h)to)low transition #tCHB% is sometimesdifferent from the time for a low)to)hi(h transition #tCBH%.

When cascadin( 3s which share the same clock #as in a shift re(ister %" it is important to ensurethat the t= of a precedin( 3 is lon(er than the hold time #th% of the followin( flip)flop" so data present at the input of the succeedin( 3 is properly Ashifted inA followin( the acti'e ed(e of theclock. /his relationship between t= and th is normally (uaranteed if the 3s are physicallyidentical. urthermore" for correct operation" it is easy to 'erify that the clock period has to be(reater than the sum tsu th.

[edit] C*aos

althasar 'an der Col was one of the first people to show electronic circuits may eEhibit chaos in+,4;" with the introduction of the an der Col oscillator . /hen" Beon . =hua showed circuitsmay eEhibit chaos in +,-5 throu(h the introduction of =huaNs circuit. $ue to the 1ualitati'enature of flip)flops" especially the Set3Reset lip)lop" one may intuiti'ely feel it can eEhibitchaos. /his has been su((ested in the works of $anca et al.[- and Hamill et al.[,. Hamill et al.[, discusses the 1ualitati'e nature of circuits&

olta(es or currents may increase eEponentially with time until limited" perhaps by power supplyclippin(" when the circuit may latch up. /his type of instability is put to (ood use in circuits such as

Schmitt tri((ers and flip)flops.[,

and

/he wa'eforms may be noise like or chaotic" in which case they ne'er repeat or latch up0 as yet this typeof beha'ior has few applications and is the least well understood.[,

http://en.wikipedia.org/wiki/Propagation_delayhttp://en.wikipedia.org/wiki/Shift_registerhttp://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=10http://en.wikipedia.org/wiki/Balthasar_van_der_Polhttp://en.wikipedia.org/wiki/Van_der_Pol_oscillatorhttp://en.wikipedia.org/wiki/Leon_O._Chuahttp://en.wikipedia.org/wiki/Leon_O._Chuahttp://en.wikipedia.org/wiki/Chua's_circuithttp://en.wikipedia.org/wiki/D_flip_flops#cite_note-7http://en.wikipedia.org/wiki/D_flip_flops#cite_note-8http://en.wikipedia.org/wiki/Propagation_delayhttp://en.wikipedia.org/wiki/Shift_registerhttp://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=10http://en.wikipedia.org/wiki/Balthasar_van_der_Polhttp://en.wikipedia.org/wiki/Van_der_Pol_oscillatorhttp://en.wikipedia.org/wiki/Leon_O._Chuahttp://en.wikipedia.org/wiki/Chua's_circuithttp://en.wikipedia.org/wiki/D_flip_flops#cite_note-7http://en.wikipedia.org/wiki/D_flip_flops#cite_note-8


13/18

More recently in lackmore et al.[+> it is shown that discrete models of the Set3Reset lip)lopcan eEhibit chaos.

[edit] Flip-flop inte0rated circ4its

nte(rated circuits #=s% eEist that pro'ide one or more flip)flops. or eEample" the ;7;5 dual J9master6sla'e flip)flop" or the ;75;7 octal $ flip)flop" in the ;7>> series.

[edit] See also

Wikimedia =ommons has media related to& Flip-flops

Wikibooks has a book on the topic of Digital Circuits/Flip-Flops

• Monostable

• 2stable

• Culse transition detector

• $eadlock

[edit] %otes+. 7 William Henry *ccles and rank Wilfred Jordan" Ampro'ements in ionic relaysA ritish patent

number& I +7-8-4 #filed& 4+ June +,+-0 published& 8 2u(ust +,4>%. 2'ailable on)line at&http&33'5.espacenet.com3ori(docT$*C$=G$LI+7-8-4G>GKC?I+7-8-4 .

4. 7 W. H. *ccles and . W. Jordan #+, September +,+,% A2 tri((er relay utiliDin( three)electrodethermionic 'acuum tubes"A The lectrician" 'ol. -5" pa(e 4,-. Reprinted in& *adio *evie" 'ol. +"no. 5" pa(es +756+7: #$ecember +,+,%.

5. 7 Mont(omery Chister #+,8-%. #ogical $esign of $igital %omputers. Wiley. p. +4-.http&33books.(oo(le.com3booksTidRi+222222JG1inauthor&phisterj)k)flip)

flopGd1inauthor&phisterj)k)flip)flopGlrGasUbrr>GasUpt2BB/VC*SGei-jfeSabSeSk2Srm8na$KGp(is+.

7. 7 *arly master)sla'e de'ices actually remained #half% open between the first and second ed(e of aclockin( pulse0 today most flip)flops are desi(ned so they may be clocked by a sin0le ed(e as this(i'es lar(e benefits re(ardin( noise immunity" without any si(nificant downsides.

8. 7 CHV+>; $elay lip)lop

http://en.wikipedia.org/wiki/Denis_Blackmorehttp://en.wikipedia.org/wiki/D_flip_flops#cite_note-9http://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=11http://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/7400_serieshttp://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=12http://en.wikipedia.org/wiki/Wikimedia_Commonshttp://commons.wikimedia.org/wiki/Category:Flip-flopshttp://en.wikipedia.org/wiki/Wikibookshttp://en.wikibooks.org/wiki/Digital_Circuits/Flip-Flopshttp://en.wikipedia.org/wiki/Monostablehttp://en.wikipedia.org/wiki/Astablehttp://en.wikipedia.org/wiki/Pulse_transition_detectorhttp://en.wikipedia.org/wiki/Deadlockhttp://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=13http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-0http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-0http://v3.espacenet.com/origdoc?DB=EPODOC&IDX=GB148582&F=0&QPN=GB148582http://v3.espacenet.com/origdoc?DB=EPODOC&IDX=GB148582&F=0&QPN=GB148582http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-1http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-1http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-2http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-2http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-3http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-3http://en.wikipedia.org/wiki/Noise_immunityhttp://en.wikipedia.org/wiki/D_flip_flops#cite_ref-4http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-4http://www.shef.ac.uk/physics/teaching/phy107/dff.htmlhttp://en.wikipedia.org/wiki/Denis_Blackmorehttp://en.wikipedia.org/wiki/D_flip_flops#cite_note-9http://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=11http://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/7400_serieshttp://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=12http://en.wikipedia.org/wiki/Wikimedia_Commonshttp://commons.wikimedia.org/wiki/Category:Flip-flopshttp://en.wikipedia.org/wiki/Wikibookshttp://en.wikibooks.org/wiki/Digital_Circuits/Flip-Flopshttp://en.wikipedia.org/wiki/Monostablehttp://en.wikipedia.org/wiki/Astablehttp://en.wikipedia.org/wiki/Pulse_transition_detectorhttp://en.wikipedia.org/wiki/Deadlockhttp://en.wikipedia.org/w/index.php?title=Flip-flop_(electronics)&action=edit&section=13http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-0http://v3.espacenet.com/origdoc?DB=EPODOC&IDX=GB148582&F=0&QPN=GB148582http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-1http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-2http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://books.google.com/books?id=Ri1IAAAAIAAJ&q=inauthor:phister+j-k-flip-flop&dq=inauthor:phister+j-k-flip-flop&lr=&as_brr=0&as_pt=ALLTYPES&ei=8jfeSabSOZeSkASrm5naDQ&pgis=1http://en.wikipedia.org/wiki/D_flip_flops#cite_ref-3http://en.wikipedia.org/wiki/Noise_immunityhttp://en.wikipedia.org/wiki/D_flip_flops#cite_ref-4http://www.shef.ac.uk/physics/teaching/phy107/dff.html


14/18

:. X a b c Mano" M. Morris0 9ime" =harles R. #4>>7%. #ogic and %omputer $esign Fundamentals,rd dition. . 7 $. lackmore" 2. Rahman" J. Shah #4>>,%. =haos" Solitons and ractals.doi&+>.+>+:3j.chaos.4>>,.>4.>54

[edit] References

• Hwan(" *noch #4>>:%. $igital #ogic and icroprocessor $esign ith /H$#. /homson. S? >)857)7:8,5)8. http&33faculty.lasierra.edu3Yehwan(3di(italdesi(n.

• Salman" *." $asdan" 2." /arapore'ala" ." 9ucukcakar" 9." riedman" *. #4>>:%. ACessimismReduction in Static /imin( 2nalysis >4%. *euseethodology anual . 92C. S? +)7>4>);+7+)7.

• $anca M). #4>>-%. A?umerical approEimation of a class of switch dynamical systemsA.%haos, olitons and Fractals 89& +-7)+,+.

• Hamill $" $eane J" Jeffries $ #+,,4%. AModelin( of chaotic $=3$= con'erters by iteratednonlinear mapsA. 0 Trans 1oer lectronics :& 48)5:.

• $. lackmore" 2. Rahman" J. Shah #4>>,%. %haos, olitons and Fractals.doi&+>.+>+:3j.chaos.4>>,.>4.>54.

Retrie'ed from Ahttp&33en.wikipedia.or(3wiki3lip)flopU#electronics%F$Uflip)flopA=ate(ories& $i(ital electronics Z *lectronic en(ineerin( Z $i(ital systems Z scillators Z Bo(ic(atesHidden cate(ories& 2ll articles with unsourced statements Z 2rticles with unsourced statementsfrom September 4>>- Z 2rticles with unsourced statements from 2pril 4>>,

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