digitaalsüsteemide verifitseerimise kursus1 formal verification: bdd bdds applied in equivalence...
TRANSCRIPT
Digitaalsuumlsteemide verifitseerimise kursus 1
Formal verification BDD
BDDs applied in equivalence
checking
Digitaalsuumlsteemide verifitseerimise kursus 2
Equivalence Checking
bull Two principal approaches
bull Transform implementation and spec (reference implementation) to a canonical form
bull Search for an input assignment that would distinguish the responses of the implementation and reference implementation
bull BDD-s applied for canonical form
Digitaalsuumlsteemide verifitseerimise kursus 3
Canonical forms of Boolean functions
bull Minimized function Karnaugh map
bull Full normal form
bull Truth table
These forms are not compact
Digitaalsuumlsteemide verifitseerimise kursus 4
Decision Diagrams and Equivalence
bull Theoretically any canonical form has exponential worst case complexity
Luckily for many practical functions compact BDDs exist
bull We will cover the topic of utilizing BDDs in equivalence checking and symbolic simulation
Digitaalsuumlsteemide verifitseerimise kursus 5
Examples of canonical forms
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Digitaalsuumlsteemide verifitseerimise kursus 6
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Examples of canonical forms
Digitaalsuumlsteemide verifitseerimise kursus 7
Overview of the history of BDDs
bull 1959 Lee BDD first mentioned
bull 1976 Ubar alternative graphs akastructural BDD-s
bull 1978 Akers BDD protagonist
bull 1985 Bryant ROBDD
bull ROBDD-s started a big BDD boom
Digitaalsuumlsteemide verifitseerimise kursus 8
Binary Decision Diagrams
bull BDD is a directed acyclic graph with a single root
node and two terminal nodes 0-node and 1-node
bull Each internal node is labeled by a Boolean variable
bull From each internal node two edges will originate
which correspond to 0 and 1 value of the variable
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 2
Equivalence Checking
bull Two principal approaches
bull Transform implementation and spec (reference implementation) to a canonical form
bull Search for an input assignment that would distinguish the responses of the implementation and reference implementation
bull BDD-s applied for canonical form
Digitaalsuumlsteemide verifitseerimise kursus 3
Canonical forms of Boolean functions
bull Minimized function Karnaugh map
bull Full normal form
bull Truth table
These forms are not compact
Digitaalsuumlsteemide verifitseerimise kursus 4
Decision Diagrams and Equivalence
bull Theoretically any canonical form has exponential worst case complexity
Luckily for many practical functions compact BDDs exist
bull We will cover the topic of utilizing BDDs in equivalence checking and symbolic simulation
Digitaalsuumlsteemide verifitseerimise kursus 5
Examples of canonical forms
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Digitaalsuumlsteemide verifitseerimise kursus 6
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Examples of canonical forms
Digitaalsuumlsteemide verifitseerimise kursus 7
Overview of the history of BDDs
bull 1959 Lee BDD first mentioned
bull 1976 Ubar alternative graphs akastructural BDD-s
bull 1978 Akers BDD protagonist
bull 1985 Bryant ROBDD
bull ROBDD-s started a big BDD boom
Digitaalsuumlsteemide verifitseerimise kursus 8
Binary Decision Diagrams
bull BDD is a directed acyclic graph with a single root
node and two terminal nodes 0-node and 1-node
bull Each internal node is labeled by a Boolean variable
bull From each internal node two edges will originate
which correspond to 0 and 1 value of the variable
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 3
Canonical forms of Boolean functions
bull Minimized function Karnaugh map
bull Full normal form
bull Truth table
These forms are not compact
Digitaalsuumlsteemide verifitseerimise kursus 4
Decision Diagrams and Equivalence
bull Theoretically any canonical form has exponential worst case complexity
Luckily for many practical functions compact BDDs exist
bull We will cover the topic of utilizing BDDs in equivalence checking and symbolic simulation
Digitaalsuumlsteemide verifitseerimise kursus 5
Examples of canonical forms
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Digitaalsuumlsteemide verifitseerimise kursus 6
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Examples of canonical forms
Digitaalsuumlsteemide verifitseerimise kursus 7
Overview of the history of BDDs
bull 1959 Lee BDD first mentioned
bull 1976 Ubar alternative graphs akastructural BDD-s
bull 1978 Akers BDD protagonist
bull 1985 Bryant ROBDD
bull ROBDD-s started a big BDD boom
Digitaalsuumlsteemide verifitseerimise kursus 8
Binary Decision Diagrams
bull BDD is a directed acyclic graph with a single root
node and two terminal nodes 0-node and 1-node
bull Each internal node is labeled by a Boolean variable
bull From each internal node two edges will originate
which correspond to 0 and 1 value of the variable
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 4
Decision Diagrams and Equivalence
bull Theoretically any canonical form has exponential worst case complexity
Luckily for many practical functions compact BDDs exist
bull We will cover the topic of utilizing BDDs in equivalence checking and symbolic simulation
Digitaalsuumlsteemide verifitseerimise kursus 5
Examples of canonical forms
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Digitaalsuumlsteemide verifitseerimise kursus 6
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Examples of canonical forms
Digitaalsuumlsteemide verifitseerimise kursus 7
Overview of the history of BDDs
bull 1959 Lee BDD first mentioned
bull 1976 Ubar alternative graphs akastructural BDD-s
bull 1978 Akers BDD protagonist
bull 1985 Bryant ROBDD
bull ROBDD-s started a big BDD boom
Digitaalsuumlsteemide verifitseerimise kursus 8
Binary Decision Diagrams
bull BDD is a directed acyclic graph with a single root
node and two terminal nodes 0-node and 1-node
bull Each internal node is labeled by a Boolean variable
bull From each internal node two edges will originate
which correspond to 0 and 1 value of the variable
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 5
Examples of canonical forms
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Digitaalsuumlsteemide verifitseerimise kursus 6
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Examples of canonical forms
Digitaalsuumlsteemide verifitseerimise kursus 7
Overview of the history of BDDs
bull 1959 Lee BDD first mentioned
bull 1976 Ubar alternative graphs akastructural BDD-s
bull 1978 Akers BDD protagonist
bull 1985 Bryant ROBDD
bull ROBDD-s started a big BDD boom
Digitaalsuumlsteemide verifitseerimise kursus 8
Binary Decision Diagrams
bull BDD is a directed acyclic graph with a single root
node and two terminal nodes 0-node and 1-node
bull Each internal node is labeled by a Boolean variable
bull From each internal node two edges will originate
which correspond to 0 and 1 value of the variable
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 6
bull Is f notac + bnotc + anotb equivalent to f anotc + notbc + notab
c ab 00 01 11 10
0 1 1 1
1 1 1 1
Examples of canonical forms
Digitaalsuumlsteemide verifitseerimise kursus 7
Overview of the history of BDDs
bull 1959 Lee BDD first mentioned
bull 1976 Ubar alternative graphs akastructural BDD-s
bull 1978 Akers BDD protagonist
bull 1985 Bryant ROBDD
bull ROBDD-s started a big BDD boom
Digitaalsuumlsteemide verifitseerimise kursus 8
Binary Decision Diagrams
bull BDD is a directed acyclic graph with a single root
node and two terminal nodes 0-node and 1-node
bull Each internal node is labeled by a Boolean variable
bull From each internal node two edges will originate
which correspond to 0 and 1 value of the variable
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 7
Overview of the history of BDDs
bull 1959 Lee BDD first mentioned
bull 1976 Ubar alternative graphs akastructural BDD-s
bull 1978 Akers BDD protagonist
bull 1985 Bryant ROBDD
bull ROBDD-s started a big BDD boom
Digitaalsuumlsteemide verifitseerimise kursus 8
Binary Decision Diagrams
bull BDD is a directed acyclic graph with a single root
node and two terminal nodes 0-node and 1-node
bull Each internal node is labeled by a Boolean variable
bull From each internal node two edges will originate
which correspond to 0 and 1 value of the variable
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 8
Binary Decision Diagrams
bull BDD is a directed acyclic graph with a single root
node and two terminal nodes 0-node and 1-node
bull Each internal node is labeled by a Boolean variable
bull From each internal node two edges will originate
which correspond to 0 and 1 value of the variable
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 9
Binary Decision Diagrams
x1
x2
x3
0 1
01
1
1
0
0
BDD for Boolean function
(x1x2) V x3
BDD is generated by Shannon expansion
10 fxfxf ii
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 10
BDD generation example
Shannonrsquos expansion
10 fxfxf ii
f=ab+bc
b+bc bc
c c
a) Generate a decision tree b) Reduced BDD
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 11
Interpretation of BDDs
bull By traversing the paths of
a BDD
1 Calculate the value of f
2 Derive the function
f=ab+anotbc+notabc+notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 12
Ordered BDD (OBDD)
bull Boolean variables occur in a concrete order
along the paths of the BDD
bull No path has more than 2 occurrences of the
same variable
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 13
Reduced OBDD (ROBDD)
Rules of reduction
a) Node removal
x
f f
10
b) Node sharing
x x x
f0 f1
0 11 0
f0 f1
0 1
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 14
Reduction example
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 15
ROBDD properties
+ ROBDD is a canonical representation of a Boolean function bull Equivalence of Boolean functions is checked
by isomorphicity of their respective BDDs
ndash ROBDD worst case memory consumption is exponentialbull Not applicable in many practical cases
(Eg multiplier)
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 16
BDD size depending on the ordering
f = ab + anotbc + notabc + notanotbd
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 17
BDD size depending on the ordering
bull There are functions whose BDD size grows linearly
wrt number of variables
bull There are functions whose BDD size grows
exponentially in the worst case wrt number of
variables
bull There are functions whose BDD size grows
ALWAYS exponentially regardless of the ordering
(Eg multiplication)
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 18
BDD size depending on the ordering
bull Finding an optimal ordering for the variables is an
unsolved problem
bull Various heuristics applied
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 19
Dynamic reordering of BDD nodes
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 20
Structural BDD-s (Ubarrsquo76)
bull Definition similar to the one of BDD
bull SSBDD is generated in a recursive manner
substituting logical gates by elementary
BDDs
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 21
Structural BDD-s (Ubarrsquo76)
bull ROBDD generated for each output of the
circuit
bull SBDD generated for each fanout-free (tree-
like) subcircuit required memory linear
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 22
SBDD properties
bull Different of ROBDD-s SBDDs are planar
bull Nodes labeled by variables and inverted variables concept of 0 and 1 direction
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 23
Alternative notation
bull Moving to the right (downwards) from a node
corresponds to variable value 1 (value 0)
bull Exiting to the right (downwards) from the graph
corresponds to function value 1 (value 0)
bull Terminal nodes not shown
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 24
Circuit its BDD and SBDD
ab
cd
e
f
y
1 0
11 0
0
10
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 25
SBDD generation
ab
cd
e
f
y
1) 2)
3) 4)
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 26
Structural paths lt=gt BDD nodesbull 11 correspondence between SBDD nodes and
structural paths in the fanout-free circuit
=gt saumlilib info skeemi struktuuri kohta
ab
cd
e
f
y
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 27
ROBDD vs SBDD
ROBDD SBDD
Canonical representation
+ -
Structural representation
- +
Speed of generation
linear linear
Memory consumption
exponential linear
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-
Digitaalsuumlsteemide verifitseerimise kursus 28
SBDD summary
bull SBDD model has a number of advantageous properties for modeling logic circuits
1) Preserve structural information
2) Suitable for fault modeling and simulation
3) Linear memory requirements
- Formal verification BDD
- Equivalence Checking
- Canonical forms of Boolean functions
- Decision Diagrams and Equivalence
- Examples of canonical forms
- PowerPoint Presentation
- Overview of the history of BDDs
- Binary Decision Diagrams
- Slide 9
- BDD generation example
- Interpretation of BDDs
- Ordered BDD (OBDD)
- Reduced OBDD (ROBDD)
- Reduction example
- ROBDD properties
- BDD size depending on the ordering
- Slide 17
- Slide 18
- Dynamic reordering of BDD nodes
- Structural BDD-s (Ubarrsquo76)
- Slide 21
- SBDD properties
- Alternative notation
- Circuit its BDD and SBDD
- SBDD generation
- Structural paths lt=gt BDD nodes
- ROBDD vs SBDD
- SBDD summary
-