digital elctronics

DIGITAL ELECTRONICS

UNIT-4

Mohammad Asif IqbalAssistant Professor, Deptt of ECE,JETGI, Barabanki

Multiplexers

A multiplexer has N control inputs 2N data inputs 1 output

A multiplexer routes (or connects) the selected data input to the output.

The value of the control inputs determines the data input that is selected.

Multiplexers

Z = A′.I0 + A.I1

Datainputs

Controlinput

Multiplexers

Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

A B F0 0 I0

0 1 I1

1 0 I2

1 1 I3

MSB LSB

Multiplexers

Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 + A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

MSB LSB

A B C F0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

Multiplexers

Encoder/Decoder Vocabulary

ENCODER- a digital circuit that produces a binary output code depending on which of its inputs are activated.

DECODER- a digital circuit that converts an input binary code into a single numeric output.

ENCODERS AND DECODERS

A 0

A 1

A 2

A 3

A 4

A 5

A 6

A 7

ENCODER

O 0

O 1

O 2

A 0

A 1

A 2

O 0

O 1

O 2

O 3

O 4

O 5

O 6

O 7

DECODER

ONLY ONE INPUT ACTIVATED AT A TIMEBINARY CODE OUTPUT

BINARY CODE INPUT

ONLY ONE OUTPUT ACTIVATED AT A TIME

THE 8421 BCD CODE

• BCD stands for Binary-Coded Decimal.

• A BCD number is a four-bit binary group that represents one of the ten decimal digits 0 through 9.

Example:

Decimal number 4926 4 9 2 6

8421 BCD coded number 0100 1001 0010 0110

ELECTRONIC ENCODER-DECIMAL TO BCD

0

Decimalto

BCDEncoder

BCD output

Decimal input0 0 0 0

5

0 1 0 17

0 1 1 1

3

0 0 1 1

• Encoders are available in IC form.• This encoder translates from decimal input to

BCD output.

10 line to 4 line Encoder

ENCODER1248

DECIMAL BINARY (BCD)

9 5V

8 5V7 5V6 5V5 5V4 5V3 5V2 5V1 5V

74147I9I8I7I6I5I4I3I2I1

A0A1A2A3

10 line to 4 line Encoder

01

23

45

6

78

9

DECODER

BINARY (BCD)

DECIMAL

1 0V2 0V

4 0V

8 0V

74LS42

A3A2A1A0

9876543210

4 line to 10 line Decoder

BCD-to-7-SegmentDecoder/

Driver

DECODERS: BCD TO 7-SEGMENT DECODER/DRIVER

BCD input

0 0 0 0

Decimal outputLED

0 0 0 10 0 1 00 0 1 10 1 0 0

• Electronic decoders are available in IC form.• This decoder translates from BCD to decimal.• Decimals are shown on an 7-segment LED display.• This IC also drives the 7-segment LED display.

BEFORE STARTING LET’S RECALL NAND GATE

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

BASIC STORAGE ELEMENT

0

1

1

0

1

LATCH

FLIP-FLOP

CLOCK

S

R

Q

Q’

=1

=0

0

1

=1

=0

0

0

1

0

0 0 1 0

FLIP-FLOP

CLOCK

S

R

Q

Q’

=0

=1

1

0

=0

=1

0

0

0

1

0 0 1 0

0 1 0 1

0 0 0 1

FLIP-FLOP

INPUT OUTPUT

S R Q Q’

0 0 NO CHANGE

0 1 0 1

1 0 1 0

1 1 ? ?

S

R

CLOCK

Q’

Q SET

RSET

=1

=1

0

0=1

=1INDETERMINANT

CHARACTERISTIC TABLE

BLOCK DIAGRAM REPRESENTATION

S

R

Q’

Q

CLOCK

DD Q Q’

0 0 1

1 1 0

Q Q(n+1) D

0 0 1

1 1 0

Q(n) D Q(n+!)

0 0 1

1 1 0

D FLIP-FLOPD Q Q’

0 0 1

1 1 0

Q Q(n+1) D

0 0 1

1 1 0

Q(n) D Q(n+!)

0 0 1

1 1 0

CHARACTERISTIC TABLE

TRUTH TABLE

EXCITATION TABLE

J K FLIP-FLOP

J

K

CLOCK

Q

Q’

=1

=0

1

0

=1

=1=1

=0=0

=1 =0

=1

WAVE FORM REPRESENTATION

(t) T 2T

CLOCK

Q

0

1

NOW, changes at I/P will affect O/PAny change at I/P

will not effect O/P

0

1

RACE AROUND CONDITION

SOLUTION OF RACE AROUND CONDITION

(t) T 2T

CLOCK

Q

0

1

0

1

T F

PROPAGATION DELAY

FINAL SOLUTION……

(t) T 2T

CLOCK

Q

0

1

0

1

JK FLIP-FLOPCHARACTERISTIC TABLE

TRUTH TABLE

EXCITATION TABLE

PROBLEMSQ:- Determine the output of PGT clocked SR flip flop which Q initially 0 for the given input waveforms

QQ’

Q:- Determine the output of PGT clocked SR flip flop which Q initially 1 for the given input waveforms.

Master Slave Flip Flop

K

JQ

Q’ =0

=1 0 0 1 1

=1

=1

1

0

=1

=0 =1

=0=0

=1

Analysis of clocked sequential circuits

X’

BBX’

B

Definition

• A register is a digital circuit with two basic functions: Data Storage and Data Movement• A shift register provides the data movement function• A shift register “shifts” its output once every clock cycle

• A shift register is a group of flip-flops set up in a linear fashion with their inputs and outputs connected together in such a way that the data is shifted from one device to another when the circuit is active

Shift Register Applications• converting between serial

data and parallel data • temporary storage in a

processor• scratch-pad memories

• some arithmetic operations• multiply, divide

• communications• UART

• some counter applications• ring counter • Johnson counter• Linear Feedback Shift Register

(LFSR) counters

• time delay devices• more …

Shift Register Characteristics• Types

• Serial-in, Serial-out• Serial-in, Parallel-out• Parallel-in, Serial-out• Parallel-in, Parallel-out• Universal

• Direction• Left shift• Right shift• Rotate (right or left)• Bidirectional

n-bit shift register

Data Movement• The bits in a shift register can move in any of the following manners



Data Movement• Block diagrams for shift registers with various input/output options:




Serial-In Serial-Out• Data bits come in one at a time and

leave one at a time• One Flip-Flop for each bit to be

handled• Movement can be left or right, but

is usually only in a single direction in a given register

• Asynchronous preset and clear inputs are used to set initial values

Serial-In Serial-Out

• The logic circuit diagram below shows a generalized serial-in serial-out shift register• SR Flip-Flops are shown• Connected to behave as D Flip-Flops• Input values moved to outputs of each Flip-Flop with the clock (shift) pulse

N-Bit Shift Register

0N 1

Shift Registers• The simplest shift register is one that uses only Flip-Flops• The output of a given Flip-Flop is connected to the D input of the Flip-Flop at its

right. • Each clock pulse shifts the contents of the register one bit position to the right. • The Serial input (SI) determines what goes into the leftmost Flip-Flop during the

shift. The Serial output (SO) is taken from the output of the rightmost Flip-Flop.

Q Q QQ

Serial-In Serial-Out• A simple way of looking at the

serial shifting operation, with a focus on the data bits, is illustrated at right

• The 4-bit data word “1011” is to be shifted into a 4-bit shift register

• One shift per clock pulse• Data is shown entering at left

and shifting right41

1

2

3

4

5

Serial-In Serial-Out• The diagram at right shows

the 4-bit sequence “1010” being loaded into the 4-bit serial-in serial-out shift register

• Each bit moves one position to the right each time the clock’s leading edge occurs

• Four clock pulses loads the register

42

Serial-In Serial-Out• This diagram shows the 4-

bit sequence “1010” as it is unloaded from the 4-bit serial-in serial-out shift register

• Each bit moves one position to the right each time the clock’s leading edge occurs

• Four clock pulses unloads the register

43

Serial-In Serial-Out

• Serial-in, serial-out shift registers are often used for data communications• such as RS-232• modem transmission and

reception• Ethernet links• SONET• etc.

Serial-to-Parallel Conversion• We often need to convert from serial

to parallel• e.g., after receiving a series transmission

• The diagrams at the right illustrate a 4-bit serial-in parallel-out shift register

• Note that we could also use the Q of the right-most Flip-Flop as a serial-out output


Serial-to-Parallel Conversion• We would use a serial-in

parallel-out shift register of arbitrary length N to convert an N-bit word from serial to parallel

• It would require N clock pulses to LOAD and one clock pulse to UNLOAD

Serial-to-Parallel Conversion• These two shift

registers are used to convert serial data to parallel data

• The upper shift register would “grab” the data once it was shifted into the lower register

Parallel-to-Serial Conversion• We use a Parallel-in Serial-out Shift

Register • The DATA is applied in parallel form to the

parallel input pins PA to PD of the register • It is then read out sequentially from the

register one bit at a time from PA to PD on each clock cycle in a serial format

• One clock pulse to load• Four pulses to unload


Parallel-to-Serial Conversion• Logic circuit for a parallel-in, serial-out shift register

Mux-like

0

0

1

0

1

1

Parallel-In Parallel-Out• Parallel-in Parallel-out Shift

Registers can serve as a temporary storage device or as a time delay device

• The DATA is presented in a parallel format to the parallel input pins PA to PD and then shifted to the corresponding output pins QA to QD when the registers are clocked

• One clock pulse to load• One pulse to unload

50


Universal Shift Register• Universal shift register• Can do any combination of parallel

and serial input/output operations• Requires additional inputs to

specify desired function• Uses a Mux-like input gating

L/SL/S

A

B

A

BF

1

01

0

Universal Shift Register• Parallel-in, parallel-out shift register

Mux-like

0

0

1

0

1

1

Universal Shift Register • Parallel shift register (can serve as converting

parallel-in to serial-out shifter):

Registers summary• A register is a special state machine that stores multiple bits

of data

• Several variations are possible:• Parallel loading to store data into the register• Shifting the register contents either left or right• Counters are considered a type of register too!

• One application of shift registers is converting between serial and parallel data

• Most programs need more storage space than registers provide• We’ll introduce RAM to address this problem

• Registers are a central part of modern processors

Introducing counters• Counters are a specific type of sequential circuit

• The state serves as the “output” (Moore)

• A counter that follows the binary number sequence is called a binary counter• n-bit binary counter: n flip-flops, count in binary from 0 to 2ⁿ-1

• Counters are available in two types:• Synchronous Counters• Ripple Counters

• Synchronous Counters:• A common clock signal is connected to the C input of each flip-flop

Synchronous Binary Up Counter• The output value increases by one on each clock cycle

• After the largest value, the output “wraps around” back to 0

• Using two bits, we’d get something like this:

Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0

00 01

1011

Synchronous Binary Up CounterPresent State Next State

A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0

D1= A’B + AB’

D0= B’

clock

A

B

What good are counters?

• Counters can act as simple clocks to keep track of “time”

• You may need to record how many times something has happened

• How many bits have been sent or received?• How many steps have been performed in some computation?

• All processors contain a program counter, or PC• Programs consist of a list of instructions that are to be executed

one after another (for the most part)• The PC keeps track of the instruction currently being executed• The PC increments once on each clock cycle, and the next program

instruction is then executed.

Synch Binary Up/Down Counter• 2-bit Up/Down counter

• Counter outputs will be 00, 01, 10 and 11• There is a single input, X. > X= 0, the counter counts up > X= 1, the counter counts down

• We’ll need two flip-flops again. Here are the four possible states:

00 01

1011

The complete state diagram and table

00 01

1011

0

0

0

10 1

1

1

Present State I nputs Next StateQ1 Q0 X Q1 Q00 0 0 0 10 0 1 1 10 1 0 1 00 1 1 0 01 0 0 1 11 0 1 0 11 1 0 0 01 1 1 1 0

• Here’s the complete state diagram and state table for this circuit

D flip-flop inputs• If we use D flip-flops, then the D inputs will just be the same as the desired next states

• Equations for the D flip-flop inputs are shown at the right

• Why does D0 = Q0’ make sense?

Present State I nputs Next StateQ1 Q0 X Q1 Q00 0 0 0 10 0 1 1 10 1 0 1 00 1 1 0 01 0 0 1 11 0 1 0 11 1 0 0 01 1 1 1 0

Q00 1 0 1

Q1 1 0 1 0X

Q01 1 0 0

Q1 1 1 0 0X

D1 = Q1 Q0 X

D0 = Q0’

Synchronous Binary Up/Down Counter

clock

X Q1

Q0

Unused states• The examples shown so far have all had 2n states, and used n flip-flops.But

sometimes you may have unused, leftover states• For example, here is a state table and diagram for a counter that repeatedly

counts from 0 (000) to 5 (101)• What should we put in the table for the two unused states?

Present State Next StateQ2 Q1 Q0 Q2 Q1 Q00 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 0 0 01 1 0 ? ? ?1 1 1 ? ? ?

001

010

011

100

101

000

Unused states can be don’t cares… • To get the simplest possible circuit, you can fill in don’t cares for the

next states. This will also result in don’t cares for the flip-flop inputs, which can simplify the hardware

• If the circuit somehow ends up in one of the unused states (110 or 111), its behavior will depend on exactly what the don’t cares were filled in with

Present State Next StateQ2 Q1 Q0 Q2 Q1 Q00 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 0 0 01 1 0 x x x1 1 1 x x x

001

010

011

100

101

000

65

…or maybe you do care• To get the safest possible circuit, you can explicitly fill in next states

for the unused states 110 and 111

• This guarantees that even if the circuit somehow enters an unused state, it will eventually end up in a valid state

• This is called a self-starting counter

Present State Next StateQ2 Q1 Q0 Q2 Q1 Q00 0 0 0 0 10 0 1 0 1 00 1 0 0 1 10 1 1 1 0 01 0 0 1 0 11 0 1 0 0 01 1 0 0 0 01 1 1 0 0 0

001

010

011

100

101

000

111110

More complex counters• It can increment or decrement, by setting the UP input to 1 or 0• You can immediately (asynchronously) clear the counter to 0000

by setting CLR = 1• You can specify the counter’s next output by setting D3-D0 to any

four-bit value and clearing LD• The active-low EN input enables or disables the counter

• When the counter is disabled, it continues to output the same value without incrementing, decrementing, loading, or clearing

• The “counter out” CO is normally 1, but becomes 0when the counter reaches its maximum value, 1111

2-bit Complex Binary Counter

R

Q1

Q0

CO

R

EN

LDD1

CLK

D0

UP

CLR

An 8-bit counter

• As you might expect by now, we can use these general counters to build othercounters

• Here is an 8-bit counter made from two 4-bit counters• The bottom device represents the least significant four bits,

while the top counter represents the most significant four bits• When the bottom counter reaches 1111 (i.e., when CO = 0), it

enables the top counter for one cycle

• Other implementation notes:• The counters share clock and clear signals• Hex displays are used here

A restricted 4-bit counter• We can also make a counter that “starts” at some value besides 0000

• In the diagram below, when CO=0 the LD signal forces the next state to be loaded from D3-D0

• The result is this counter wraps from 1111 to 0110 (instead of 0000)

Another restricted counter• We can also make a circuit that counts up to only 1100, instead of 1111

• Here, when the counter value reaches 1100, the NAND gate forces the counter to load, so the next state becomes 0000

Ripple Counter

Simple, yet asynchronous circuits !!!

Summary

• Counters serve many purposes in sequential logic design

• There are lots of variations on the basic counter• Some can increment or decrement• An enable signal can be added• The counter’s value may be explicitly set

• There are also several ways to make counters• You can follow the sequential design principles to build counters

from scratch• You could also modify or combine existing counter devices

THANK YOU!

digital elctronics

Engineering