digital electronics pld

Chapter 13

IMPLEMENTATION OF IMPLEMENTATION OF COMBINATIONAL LOGIC BY COMBINATIONAL LOGIC BY

PROGRAMMABLE LOGIC PROGRAMMABLE LOGIC DEVICES DEVICES

Ch13L1-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2

Lesson 1

Programmable Logic Devices


One SOP expression each for each output column of Truth table

• Any logic function implemented by a combination circuit, there is a truth table. Each row of each output-column in a truth table can be specified as a mini-term of Boolean function

• An output column for a Boolean function is expressed in the form of sum of products (SOPs) expression [Product terms are the miniterms.]


Example-1 —An SOP ExpressionAn output, Y • Y = A. B. C + A. B. C = Σ m(2,7)• It means truth table has logic 1

state for two rows out of 8 — One for ABC = 010 and other for 111.

• There are two miniterms — m2 and m7 that are present in Y


Example-2 - Two SOP ExpressionsOutputs, Y0 and Y1 Y0= A. B. C. D + A. B. C. D + A. B. C. D Y1= A. B. C. D + A. B. C. D

Y0 = 1 for three rows [for m5, m7, m8]Y1 = 1 for two rows [for m1, m5]


AND-OR ARRAY

• A miniterm corresponds to AND operation

• A sum corresponds to OR operations between miniterms

• AND-OR array therefore Boolean implements functions


AND-OR ARRAY• For n inputs (2n truth table rows) a

matrix of 2n × input AND gates and 2n

input m number OR gates• (2×n) input AND is used because each

SOP expression contains of n variables and their n complements.

• Example 1— n = 3 and m =1• Example 2 — n = 4 and m =2


Programmable Logic Device (PLD)• Programmable logic device has a two

dimensional AND-OR array and has fusible links. By programming a set of links, a Boolean expression output is obtained at the OR gates. Number of Boolean functions, which can be implemented from PLD = number of OR gates = m.


Three Variable AND-OR ARRAY

• Each AND has a distinct set of three inputs each among A, B and C and complements A, B and C.

• 6 inputs of each AND are interconnected as per miniterm (one of the 8 possible logic states).

• An OR gate of 8 inputs from 8 ANDs (for 8 miniterms) can implement any three variable Boolean function.


Example 1—AND-OR ARRAY

• Assume that there are eight ANDs with each AND having six inputs (2 ×n).

• Assume one OR (m = 1) • Y = A. B. C + A. B. C = Σ m(2,7)

implements if OR gate of AND-OR array connects to only those AND gates which corresponds to m2 and m7 and rest of the links are fused (not connected) in the AND OR array.


Σ m(2,7) Implementing PLD CircuitAND End No FusibleLinks in case of PROM

OR End Columns 8 Fusible- Links

in case of PROM

m0

m7

2n = 8 Inputs ANDsm= 1 8-input OROnly two links present, Other fused

Y

m2××××××××

××××××××××××

××××


Four Variable AND-OR ARRAY• Each AND has a distinct set of four

inputs each among A, B, C and D and four complements A, B, C and D. 8 inputs of the AND are interconnected to 16 possible logic states (miniterms) in case of 4 input variables in the Boolean expression

• Each OR gate can have maximum 16 links to implement a Boolean function


Example 2—AND-OR ARRAY• Assume that there are 16 ANDs with

each AND having six inputs (2 × n) and one OR (m = 1)

• Outputs, Y0 and Y1 Y0= A. B. C. D + A. B. C. D +

A. B. C. D = Σ m(5, 7, 8) and Y1= A. B. C. D + A. B. C. D

= Σ m(1, 5)


Example 2—AND-OR ARRAY• It implements by two OR gates of

AND-OR array, one connected to connects to only those AND gates which correspond to m5, m7 and m8 and other connected to m1 and m5 generating ANDs.

• Rest of the links of each OR are fused (not connected) in the AND-OR array.


ΣΣΣΣ m(5, 7, 8) and ΣΣΣΣ m(1,5) Implementing PLD Circuit

AND End No FusibleLinks in case of PROM

OR End Columns 16 Fusible- Links PROM

m5

m8

Y0

m7 ×××× ××××

××××××××m1

Y1

××××

××××

××××

××××××××××××××××××××

×××× ××××


Fusible Links

2n = 16 Inputs ANDsm= 2 8-input ORsOnly three links present in one OR and two link in

another ORAll other links in both ORS are fused


PLD Circuit Fusible Links• Horizontal ORs with 2n possible links at

each OR• Total Number of ORs = m = Number of

Boolean Functions• Vertical ANDs with 2n possible links at

each AND• Total number of ANDs = 2n = Number of

miniterms• Maximum possible fusible links = 2n . 2n. m


Programmable Logic Device (PLD)Three type of Devices• Fusible OR links only (PROM)• Fusible AND links only (PAL)• Fusible AND and OR both links (PLA)


PLD CircuitAND End Fusible Links only in case of aPAL or PLA

OR End Columns 2n Fusible- Links only in case of a PROM or PLA

m0

m(2n–1)

2n input ANDs16-input ORs Y1Y0


PLD programmer

• A programming is a systemic hardware related procedure implemented by software at a programming system, called programmer or laboratory programmer or PLD programmer and the programming means executing the procedure for fusing (snapping) the needed links in the erased or fresh PLD


Erased PLD

• Erased PLD means in which fusible links ready for programming


Summary


• A Boolean function output corresponds to a row of truth table

• A Boolean function may have 1 as output for number of rows

• Each row identifies by a miniterm.• Boolean functions can be implemented by

AND-OR arrays PLDs• PLD is a programmable AND-OR array in

which there are links, which are fused to implement the Boolean functions


• (2 × n × 2n × m) links maximum possible at an AND-OR array in PLD for m combinational circuits

• PLDs have programmable OR or AND or both links, which are fusible, in PROM, PAL or PLA, respectively.


End of Lesson 1 on Programmable Logic Devices


THANK YOU

digital electronics pld

Documents