digital ic counters

38
Prof Jess Role @UEAB 2008 DIGITAL IC COUNTERS Lecture 7

Upload: tashya-hampton

Post on 30-Dec-2015

88 views

Category:

Documents


7 download

DESCRIPTION

DIGITAL IC COUNTERS. Lecture 7. Consider the timing diagram for the 4-bit counter circuit. There is a delay or ripple effect on the output transitions, each output being delayed from the previous due to the propagation delay through the flip-flop. - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

DIGITAL IC COUNTERS

Lecture 7

Page 2: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Asynchronous and Synchronous Circuits

Valid Output

Clock

Q0

Q1

Q2

Q3

• Consider the timing diagram for the 4-bit counter circuit.

• There is a delay or ripple effect on the output transitions, each output being delayed from the previous due to the propagation delay through the flip-flop.

• When all the outputs do not become valid “at once”, the circuit is ASYNCHRONOUS.

• These circuits are generally identified by the different flip-flops being clocked by different signals.

• This counter circuit is often called a RIPPLE COUNTER.

Page 3: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Synchronous Circuits

• In many circuits it is necessary to ensure that all outputs change simultaneously or SYNCHRONOUSLY. This can be achieved by clocking all the flip-flops with the same clock signal.

• Look at a Synchronous 4-bit counter circuit

• This circuit must produce synchronous outputs because all the flip-flops are clocked by the same signal.

D Q

D Q

D Q

D Q

C0

Q0C1

Q1C2

Q2C3

Q3

Clock

Q0

Q1

Q2

Q3

Page 4: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Synchronous Counter: A Closer Look

To look at how this might work, we will first simplify it to a 2-bit counter, ie: 00->01->10->11->00->…

At startup the outputs are both 0.These feed back into the comb. cct to putvalues of 1 for Y0 and 0 for Y1, ready forthe next clock pulse.The clock “strikes”: the 1 and 0 flowthrough to X0 and X1, but again feedback to the comb. cct which places 0 ontoY0 & 1 onto Y1 (ready for the next clock).The clock “strikes”: the 0 and 1 flowthrough to X0 and X1, but again feedback to the combinatorial circuit which places 1 onto Y0 & 1 onto Y1.The clock “strikes”: the 1 and 1 flow through to X0 and X1, but againfeed back to the combinatorial cct which places 0 onto Y0 & 0 onto Y1.Clock: The X’s are both 0 & the Y’s are 1 & 0, we’re back to the start.

X0

X1

Clock

Combinatorial Circuit

Y0

Y1

Page 5: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Synchronous Counter as a State Machine

How is this counter working?

The outputs are part of the inputs for the next Y0 and Y1 pair, ie the circuit is remembering its past output.

That is, it’s behaving like a state machine.

Sometimes it is better to model thebehaviour of a machine ratherthan what it actually looks like.

The PALASM system allows us tospecify a machine as a state machineand it will program the circuits for us.

So that is the direction we must now take:

State Machines and The PALASM System Section 3.

S0

00

S1

01

S2

10

S3

11

X1 X0

Page 6: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

What's A 7-Segment Display?

A 7-segment display is a package with 7 bar-shaped LEDs arranged to allow the display of many useful digits and some letters.

Each segment (labeled A-G) contains an LED which may be individually controlled. DP is an eighth LED, the decimal point.

Page 7: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Common cathode means that each segment's cathode is connected to common pins – 3 & 8, allowing the anode of each to be connected to the controller.

Page 8: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

BCD to 7 Segment

Page 9: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Limiting resistor Computation

RS = mA

V

10

3.2 = 230

Page 10: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

BCD to 7 Segment Crystal Display

Page 11: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

74ALS193

Page 12: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

74HC193 Two Stage Arrangement

Page 13: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Page 14: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Basic Integrated Circuit Counter7490 Decade Counter

Clock

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 15: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 16: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 17: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 18: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 19: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 20: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 21: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 22: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 23: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 24: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 25: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 26: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 27: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 28: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modifying the count sequence

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

Page 29: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Cascading Stages

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

SECONDS(One’s Digit)

SECONDS(Ten’s Digit)

Page 30: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Cascading Stages

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

R9(1)

CLK A

7490

QA

QB

QC

QD

CLK B

R9(2)

R0(1)

R0(2)

14

7

6

3

2

VCC

GNDInput

5

10

1

12

9

8

11

+5V

SECONDS(One’s Digit)

SECONDS(Ten’s Digit)

??

Page 31: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Modulo Counter

Page 32: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Page 33: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Page 34: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Asynchronous counter

Page 35: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Page 36: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Page 37: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Presettable Parallel Counter with Asynchronous Preset

Page 38: DIGITAL IC COUNTERS

Prof Jess Role @UEAB 2008

Up/Down Counter