digital ic counters
DESCRIPTION
DIGITAL IC COUNTERS. Lecture 7. Consider the timing diagram for the 4-bit counter circuit. There is a delay or ripple effect on the output transitions, each output being delayed from the previous due to the propagation delay through the flip-flop. - PowerPoint PPT PresentationTRANSCRIPT
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DIGITAL IC COUNTERS
Lecture 7
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Asynchronous and Synchronous Circuits
Valid Output
Clock
Q0
Q1
Q2
Q3
• Consider the timing diagram for the 4-bit counter circuit.
• There is a delay or ripple effect on the output transitions, each output being delayed from the previous due to the propagation delay through the flip-flop.
• When all the outputs do not become valid “at once”, the circuit is ASYNCHRONOUS.
• These circuits are generally identified by the different flip-flops being clocked by different signals.
• This counter circuit is often called a RIPPLE COUNTER.
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Synchronous Circuits
• In many circuits it is necessary to ensure that all outputs change simultaneously or SYNCHRONOUSLY. This can be achieved by clocking all the flip-flops with the same clock signal.
• Look at a Synchronous 4-bit counter circuit
• This circuit must produce synchronous outputs because all the flip-flops are clocked by the same signal.
D Q
D Q
D Q
D Q
C0
Q0C1
Q1C2
Q2C3
Q3
Clock
Q0
Q1
Q2
Q3
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Synchronous Counter: A Closer Look
To look at how this might work, we will first simplify it to a 2-bit counter, ie: 00->01->10->11->00->…
At startup the outputs are both 0.These feed back into the comb. cct to putvalues of 1 for Y0 and 0 for Y1, ready forthe next clock pulse.The clock “strikes”: the 1 and 0 flowthrough to X0 and X1, but again feedback to the comb. cct which places 0 ontoY0 & 1 onto Y1 (ready for the next clock).The clock “strikes”: the 0 and 1 flowthrough to X0 and X1, but again feedback to the combinatorial circuit which places 1 onto Y0 & 1 onto Y1.The clock “strikes”: the 1 and 1 flow through to X0 and X1, but againfeed back to the combinatorial cct which places 0 onto Y0 & 0 onto Y1.Clock: The X’s are both 0 & the Y’s are 1 & 0, we’re back to the start.
X0
X1
Clock
Combinatorial Circuit
Y0
Y1
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Synchronous Counter as a State Machine
How is this counter working?
The outputs are part of the inputs for the next Y0 and Y1 pair, ie the circuit is remembering its past output.
That is, it’s behaving like a state machine.
Sometimes it is better to model thebehaviour of a machine ratherthan what it actually looks like.
The PALASM system allows us tospecify a machine as a state machineand it will program the circuits for us.
So that is the direction we must now take:
State Machines and The PALASM System Section 3.
S0
00
S1
01
S2
10
S3
11
X1 X0
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What's A 7-Segment Display?
A 7-segment display is a package with 7 bar-shaped LEDs arranged to allow the display of many useful digits and some letters.
Each segment (labeled A-G) contains an LED which may be individually controlled. DP is an eighth LED, the decimal point.
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Common cathode means that each segment's cathode is connected to common pins – 3 & 8, allowing the anode of each to be connected to the controller.
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BCD to 7 Segment
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Limiting resistor Computation
RS = mA
V
10
3.2 = 230
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BCD to 7 Segment Crystal Display
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74ALS193
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74HC193 Two Stage Arrangement
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Basic Integrated Circuit Counter7490 Decade Counter
Clock
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Modifying the count sequence
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
Prof Jess Role @UEAB 2008
Cascading Stages
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
SECONDS(One’s Digit)
SECONDS(Ten’s Digit)
Prof Jess Role @UEAB 2008
Cascading Stages
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
R9(1)
CLK A
7490
QA
QB
QC
QD
CLK B
R9(2)
R0(1)
R0(2)
14
7
6
3
2
VCC
GNDInput
5
10
1
12
9
8
11
+5V
SECONDS(One’s Digit)
SECONDS(Ten’s Digit)
??
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Modulo Counter
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Asynchronous counter
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Presettable Parallel Counter with Asynchronous Preset
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Up/Down Counter