digital ic design flow - 國立臺灣大學access.ee.ntu.edu.tw/course/dsd_93second/2005ppt/lec...
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![Page 1: Digital IC Design Flow - 國立臺灣大學access.ee.ntu.edu.tw/course/dsd_93second/2005ppt/Lec 2... · 2010-07-14 · Graduate Institute of Electronics Engineering, NTU Digital IC](https://reader033.vdocuments.net/reader033/viewer/2022041813/5e5906c9fb29d70a251fd0ac/html5/thumbnails/1.jpg)
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
Digital IC Design FlowDigital IC Design Flow
Lecturer: 吳安宇Date: 2005.03.04
V1.0: 3/3/2005
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pp. 2Huai-Yi HsuDigital IC Design Flow 2005.03.03
OutlineOutlinevMOS TransistorvIntegrated CircuitsvMOS ProcessvMoore’s LawvDesign ChallengevIC Design flow
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pp. 3Huai-Yi HsuDigital IC Design Flow 2005.03.03
The MOS TransistorThe MOS TransistorPolysilicon Aluminum/Cu
Channel/Gate length: The distance between Source and Drain
0.18um/0.13um: this year’s main stream90nm: next year
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pp. 4Huai-Yi HsuDigital IC Design Flow 2005.03.03
Discrete TransistorsDiscrete Transistors
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pp. 5Huai-Yi HsuDigital IC Design Flow 2005.03.03
The First Integrated Circuits The First Integrated Circuits
Bipolar logic1960’s
ECL 3-input GateMotorola 1966
Invented/patented by - Jack Kilby (Texas Instrument, Nobel Laureate)- Bob Noyce (Fairchild)
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pp. 6Huai-Yi HsuDigital IC Design Flow 2005.03.03
Intel 4004 MicroIntel 4004 Micro--ProcessorProcessor
19711000 transistors1 MHz operation
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pp. 7Huai-Yi HsuDigital IC Design Flow 2005.03.03
Intel Pentium (IV) microprocessor:Intel Pentium (IV) microprocessor:millions of transistorsmillions of transistors
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pp. 8Huai-Yi HsuDigital IC Design Flow 2005.03.03
88--inch Waferinch Wafer
An 8-inch (200-mm) diameter wafer containing Intel Pentium 4 processors
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pp. 9Huai-Yi HsuDigital IC Design Flow 2005.03.03
Die CostDie Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
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pp. 10Huai-Yi HsuDigital IC Design Flow 2005.03.03
The MOS TransistorThe MOS TransistorPolysilicon Aluminum/Cu
Channel/Gate length: The distance between Source and Drain
0.18um/0.13um: this year’s main stream90nm: next year
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pp. 11Huai-Yi HsuDigital IC Design Flow 2005.03.03
Patterning of SiO2Patterning of SiO2
Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
PhotoresistSiO2
UV-lightPatternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
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pp. 12Huai-Yi HsuDigital IC Design Flow 2005.03.03
The chip manufacturing processThe chip manufacturing process
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pp. 13Huai-Yi HsuDigital IC Design Flow 2005.03.03
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single photolithographic cycle (from [Fullman]).
PhotoPhoto--Lithographic ProcessLithographic Process
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pp. 14Huai-Yi HsuDigital IC Design Flow 2005.03.03
Process v.s. Pizza MakingProcess v.s. Pizza Making
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pp. 15Huai-Yi HsuDigital IC Design Flow 2005.03.03
MooreMoore’’s Law:s Law: Driving Technology AdvancesDriving Technology Advances
v Logic capacity doubles per IC at regular intervals (1965).v Logic capacity doubles per IC every 18 months (1975).
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pp. 16Huai-Yi HsuDigital IC Design Flow 2005.03.03
Process Technology EvolutionProcess Technology Evolution
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pp. 17Huai-Yi HsuDigital IC Design Flow 2005.03.03
Chips SizesChips Sizes
Source: IBM and Dataquest
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pp. 18Huai-Yi HsuDigital IC Design Flow 2005.03.03
Shrinking Product CyclesShrinking Product Cycles
v Shrinking product cyclesv Shrinking development turnaround timesv Need for productivity increase (remember the “design gap”)v Note: PCS: 個人通訊服務 (Personal Communication Service)
PCS: Personal Communication Services
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pp. 19Huai-Yi HsuDigital IC Design Flow 2005.03.03
Productivity TrendsProductivity Trends
Source: Sematech
Complexity outpaces design productivity
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000Logic Tr./ChipTr./Staff Month.
xxxx
xx
x21%/Yr. compound
Productivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Logi
c Tr
ansi
stor
per
Chi
p(M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Prod
uctiv
ity(K
) Tra
ns./S
taff
-Mo.
Com
plex
ity
Courtesy, ITRS Roadmap
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pp. 20Huai-Yi HsuDigital IC Design Flow 2005.03.03
Design Productivity CrisisDesign Productivity Crisis
v Human factors may limit design more than technology.v Keys to solve the productivity crisis:
v Design techniques: Hierarchical design, SoC design (IP reuse, platform-based design), etc.
v CAD: algorithms & methodology
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pp. 21Huai-Yi HsuDigital IC Design Flow 2005.03.03
Increasing Processing PowerIncreasing Processing Powerv Very high-performance circuits in today’s
technologies:v Gate delays: ~27ps for a 2-input Nand in CU11v Operating frequencies: up to 500MHz for SoC/Asic, over
1GHz for custom designs
v The increase in speed/performance of circuits allowed blocks to be reused without having to be redesigned and tuned for each application
v Enhanced Design Tools and Techniques (EDA tools)v Although not enough to close the “design gap”, tools are
essential for the design of today’s high-performance chips
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pp. 22Huai-Yi HsuDigital IC Design Flow 2005.03.03
IPIP--Based Based SoCsSoCsv An Evolutionary Pathv Early daysØ IP/Cores not really designed for reuse (no standard
deliverables)ØMultiple Interfaces, difficult to integrate
v IPs evolved: parameterization, deliverables, verification, synthesizable, reusable
v On-Chip bus (OCB) standards began to appear (e.g, IBM, ARM)
v Reusable IP + On-chip bus architecturesv 1998: max number of cores > 30 cores
core content between 50% and 95%
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pp. 23Huai-Yi HsuDigital IC Design Flow 2005.03.03
IP / CoresIP / Coresv Soft IP/Corev Delivered as RTL Verilog or VHDL source code with
synthesis script (i.e: clock generation logic)v Customers are responsible for synthesis, timing closure, and
all front-end processingv Firm IP/Corev Delivered as a netlist to be included in customer’s netlist
(with don't touch attribute)v Possibly with placement information
v Hard IP/Corev Due to their complexity, they are provided as a blackbox
(GL1/GDSII). Ex. Processor cores, Analog cores, PLLsv Usually very tight timing constraints. Internal views not be
alterable or visible to the customer
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pp. 24Huai-Yi HsuDigital IC Design Flow 2005.03.03
Chasing the Design GapChasing the Design Gap
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pp. 25Huai-Yi HsuDigital IC Design Flow 2005.03.03
Changes in the Nature of IC DesignChanges in the Nature of IC Design
(IEEE Spectrum Nov,1996)
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pp. 26Huai-Yi HsuDigital IC Design Flow 2005.03.03
Evolution of Silicon DesignEvolution of Silicon Design
Source: “Surviving the SoC revolution – A Guide to Platform-based Design,”Henry Chang et al, Kluwer Academic Publishers, 1999
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pp. 27Huai-Yi HsuDigital IC Design Flow 2005.03.03
Methodology Methodology –– Analysis and Verification Analysis and Verification
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pp. 28Huai-Yi HsuDigital IC Design Flow 2005.03.03
IC Design and ImplementationIC Design and ImplementationIdea
Design
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pp. 29Huai-Yi HsuDigital IC Design Flow 2005.03.03
Types of Types of ASICsASICs
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pp. 30Huai-Yi HsuDigital IC Design Flow 2005.03.03
Types of Types of ASICsASICsvFull-custom ASICsvSemi-custom ASICsvCell-based ASICsvGate Array-based ASICs
vProgrammable ASICsvProgrammable logic devicesvField Programmable Gate Array
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pp. 31Huai-Yi HsuDigital IC Design Flow 2005.03.03
CMOS ProcessCMOS Process
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pp. 32Huai-Yi HsuDigital IC Design Flow 2005.03.03
A Modern CMOS ProcessA Modern CMOS Process
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
DualDual--Well TrenchWell Trench--Isolated CMOS ProcessIsolated CMOS Process
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pp. 33Huai-Yi HsuDigital IC Design Flow 2005.03.03
Circuit Design and LayoutCircuit Design and Layout
VDD VDD
Vin Vout
M1
M2
M3
M4
Vout2
Its Layout ViewIts Layout ViewSchematic ViewSchematic View
0 1 0
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pp. 34Huai-Yi HsuDigital IC Design Flow 2005.03.03
CMOS Inverter LayoutCMOS Inverter Layout
A A’
np-substrate Field
Oxidep+n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
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pp. 35Huai-Yi HsuDigital IC Design Flow 2005.03.03
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pp. 36Huai-Yi HsuDigital IC Design Flow 2005.03.03
Full-custom Designv Performance at transistor levelv Utilize layout editing toolsv Virtuoso (Cadence, USA)v Laker (SpringSoft, Taiwan)
v Very expensive in design cost and design timev 10-20 gates per week
(low design productivity)
v Used for:v Analogv Leaf cells - libraries, memory cellsv Datapath unit in high performance
designs (ALU in high-end CPU)
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pp. 37Huai-Yi HsuDigital IC Design Flow 2005.03.03
Standard Cell Standard Cell -- ExampleExample
3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time
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pp. 38Huai-Yi HsuDigital IC Design Flow 2005.03.03
Automatic Cell GenerationAutomatic Cell Generation
Courtesy Acadabra
Initial transistorgeometries
Placedtransistors
Routedcell
Compactedcell
Finishedcell
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pp. 39Huai-Yi HsuDigital IC Design Flow 2005.03.03
CellCell--based Design (or standard cells)based Design (or standard cells)
Routing channel requirements arereduced by presenceof more interconnectlayers
Functionalmodule(RAM,multiplier, …)
Routingchannel
Logic cellFeedthrough cellR
ows
of c
ells
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Graduate Institute of Electronics Engineering, NTU
pp. 40Huai-Yi HsuDigital IC Design Flow 2005.03.03
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Graduate Institute of Electronics Engineering, NTU
pp. 41Huai-Yi HsuDigital IC Design Flow 2005.03.03
Cell-based IC (CBIC) Design
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Graduate Institute of Electronics Engineering, NTU
pp. 42Huai-Yi HsuDigital IC Design Flow 2005.03.03
Standard Cell Standard Cell —— ExampleExample
[Brodersen92]
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Graduate Institute of Electronics Engineering, NTU
pp. 43Huai-Yi HsuDigital IC Design Flow 2005.03.03
Transition to Automation and Regular StructuresTransition to Automation and Regular Structures
Intel 4004 (Intel 4004 (‘‘71)71)Intel 8080Intel 8080 Intel 8085Intel 8085
Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel
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Graduate Institute of Electronics Engineering, NTU
pp. 44Huai-Yi HsuDigital IC Design Flow 2005.03.03
Pre-diffused(Gate Arrays)
Pre-wired(FPGA's)
Array-based
LateLate--Binding ImplementationBinding Implementation
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Graduate Institute of Electronics Engineering, NTU
pp. 45Huai-Yi HsuDigital IC Design Flow 2005.03.03
Gate Array Gate Array —— SeaSea--ofof--gatesgates
rows of
cells
routing channel
uncommitted
VD D
GND
polysilicon
metal
possiblecontact
In1 In2 In3 In4
Out
UncommitedCell
CommittedCell(4-input NOR)
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Graduate Institute of Electronics Engineering, NTU
pp. 46Huai-Yi HsuDigital IC Design Flow 2005.03.03
SeaSea--ofof--gate Primitive Cellsgate Primitive Cells
NMOS
PMOS
Oxide-isolation
PMOS
NMOS
NMOS
Using oxide-isolation Using gate-isolation
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Graduate Institute of Electronics Engineering, NTU
pp. 47Huai-Yi HsuDigital IC Design Flow 2005.03.03
SeaSea--ofof--gatesgates
Random Logic
MemorySubsystem
LSI Logic LEA300K(0.6 µm CMOS)
Courtesy LSI Logic
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Graduate Institute of Electronics Engineering, NTU
pp. 48Huai-Yi HsuDigital IC Design Flow 2005.03.03
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Graduate Institute of Electronics Engineering, NTU
pp. 49Huai-Yi HsuDigital IC Design Flow 2005.03.03
The return of gate arrays?The return of gate arrays?
metal-5 metal-6
Via-programmable cross-point
programmable via
Via programmable gate array(VPGA)
Exploits regularity of interconnect: Structured ASIC
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Graduate Institute of Electronics Engineering, NTU
pp. 50Huai-Yi HsuDigital IC Design Flow 2005.03.03
System SpecificationSystem Specification
From CIC
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Graduate Institute of Electronics Engineering, NTU
pp. 51Huai-Yi HsuDigital IC Design Flow 2005.03.03
Algorithm MappingAlgorithm Mapping
RTL Level
System Level
From CIC
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Graduate Institute of Electronics Engineering, NTU
pp. 52Huai-Yi HsuDigital IC Design Flow 2005.03.03
Gate and Circuit Level DesignGate and Circuit Level Design
From CIC
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Graduate Institute of Electronics Engineering, NTU
pp. 53Huai-Yi HsuDigital IC Design Flow 2005.03.03
Physical Level DesignPhysical Level Design
From CIC
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Graduate Institute of Electronics Engineering, NTU
pp. 54Huai-Yi HsuDigital IC Design Flow 2005.03.03
Design Abstraction LevelsDesign Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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Graduate Institute of Electronics Engineering, NTU
pp. 55Huai-Yi HsuDigital IC Design Flow 2005.03.03
SemicustomSemicustom Design FlowDesign Flow
HDLHDL
Logic SynthesisLogic Synthesis
FloorplanningFloorplanning
PlacementPlacement
RoutingRouting
Tape-out
Circuit ExtractionCircuit Extraction
Pre-Layout Simulation
Pre-Layout Simulation
Post-Layout Simulation
Post-Layout Simulation
StructuralStructural
PhysicalPhysical
BehavioralBehavioralDesign Capture
Des
ign
Itera
tion
Des
ign
Itera
tion
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Graduate Institute of Electronics Engineering, NTU
pp. 56Huai-Yi HsuDigital IC Design Flow 2005.03.03
Pre-layout simulation
Post-layout simulation
Logic Design
Physical Design
Circuit extraction
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Graduate Institute of Electronics Engineering, NTU
pp. 57Huai-Yi HsuDigital IC Design Flow 2005.03.03
Design FlowDesign Flow
Design Specification
Design Partition
Design Entry-VerilogBehavioral Modeling
Simulation/FunctionalVerification
Design Integration &Verification
Pre-SynthesisSign-Off
Synthesize and MapGate-Level Netlist
Post-Synthesis Design Validation
Post-SynthesisTiming Verification
Test Generation &Fault Simulation
Cell Placement, ScanChain & Clock Tree
Insertion, Cell Routing
Verify Physical &Electrical Design Rules
Extract Parasitics
Post-LayoutTiming Verification
Production-ReadyMasks
Production-ReadyMasks
Front End
Design Sign-Off
Back End
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Graduate Institute of Electronics Engineering, NTU
pp. 58Huai-Yi HsuDigital IC Design Flow 2005.03.03
Concept of SynthesisConcept of SynthesisvSynthesis is Constraint DrivenvTechnology Independent
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Graduate Institute of Electronics Engineering, NTU
pp. 59Huai-Yi HsuDigital IC Design Flow 2005.03.03
The The ““Design ClosureDesign Closure”” ProblemProblem
Courtesy Synopsys
Iterative Removal of Timing Violations (white lines)
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Graduate Institute of Electronics Engineering, NTU
pp. 60Huai-Yi HsuDigital IC Design Flow 2005.03.03
Behavioral ModelBehavioral Model
Transistor Level
Gate Level
Register Transfer Level
Architecture
Algorithm
Systemconcept
Increasingbehavioralabstraction
Increasingdetailed
realization &complexity
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Graduate Institute of Electronics Engineering, NTU
pp. 61Huai-Yi HsuDigital IC Design Flow 2005.03.03
Design Domain (Verification and Design Domain (Verification and Closure)Closure)
Behaviorallevel of
abstraction
Design Model Domain
Abstract PhysicalStructural
System
Algorithm
RTL
Gate
Switch
ArchitectureDesign
StructuralDesign
LogicDesign
LayoutDesign
Verification
Verification
Verification
ArchitectureSynthesis
RTL levelSynthesis
Logic levelSynthesis