Digital Image Processing

1

A Low-Cost

VLSI

Implementation

for Efficient

Removal of

Impulse Noise

Image and video signals might be corrupted by impulse noise in the process of

signal acquisition and transmission. In this paper, an efficient VLSI implementation

for removing impulse noise is presented. Our extensive experimental results show

that the proposed technique preserves the edge features and obtains excellent

performances in terms of quantitative evaluation and visual quality. The design

requires only low computational complexity and two line memory buffers. Its

hardware cost is quite low. Compared with previous VLSI implementations, our

design achieves better image quality with less hardware cost. Synthesis results show

that the proposed design yields a processing rate of about 167 M samples/second by

using TSMC 0.18 m technology

Digital

Image

Processing

2013

2

An FPGA-Based

Hardware

Implementation

of Configurable

Pixel-Level

Color Image

Fusion

Image fusion has attracted a lot of interest in recent years. As a result,

different fusion methods have been proposed mainly in the fields of remote sensing

and computer (e.g., night) vision, while hardware implementations have been also

presented to tackle real-time processing in different application domains. In this

paper, a linear pixel-level fusionmethod is employed and implemented on a field-

programmable-gate-array-based hardware system that is suitable for remotely sensed

data. Our work incorporates afusion technique (called VTVA) that is a linear

transformationbased on the Cholesky decomposition of the covariance matrix of the

source data. The circuit is composed of different modules, including covariance

estimation, Cholesky decomposition, and transformation ones. The resulted

compact hardware design can be characterized as a

linearconfigurable implementation since the color properties of the final

fused color can be selected by the user in a way ofcontrolling the resulting

correlation between colorcomponents.

Digital

Image

Processing

2013

3

Memory-

Efficient High-

Speed

Convolution-

Based Generic

Structure for

Multilevel 2-D

DWT

In this paper, we have proposed a design strategy for the derivation of memory-efficient

architecture for multilevel 2-D DWT. Using the proposed design scheme, we have derived a

convolution-based generic architecture for the computation of three-level 2-D DWT based on

Daubechies (Daub) as well as biorthogonal filters. The proposed structure does not involve

frame-buffer. It involves line-buffers of size 3(K-2)M/4 which is independent of throughput-

rate, where K is the order of Daubechies/biorthogonal wavelet filter and M is the image

height. This is a major advantage when the structure is implemented for higher throughput.

The structure has regular data-flow, small cycle period TM and 100% hardware utilization

efficiency. As per theoretical estimate, for image size 512 × 512, the proposed structure for

Daub-4 filter requires 152 more multipliers and 114 more adders, but involves 82 412 less

memory words and takes 10.5 times less time to compute three-level 2-D DWT than the best

of the existing convolution-based folded structures. Similarly, compared with the best of the

existing lifting-based folded structures, proposed structure for 9/7-filter involves 93 more

multipliers and 166 more adders, but uses 85 317 less memory words and requires 2.625 times

less computation time for the same image size. It involves 90 (nearly 47.6%) more multipliers

and 118 (nearly 40.1%) more adders, but requires 2723 less memory words than the recently

proposed parallel structure and performs the computation in nearly half the time of the other.

Inspite of having more arithmetic components than the lifting-based structures, the proposed

structure offers significant saving of area and power over the other due to substantial

reduction in memory size and smaller clock-period. ASIC synthesis result shows that, the

Digital

Image

Processing

2013

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VLSI – 2013

Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,

Digital Communications and Information theory, Digital Image Processing,

Bus Protocols and System on Chip

proposed structure for Daub-4 involves 1.7 times less area-delay-product (ADP) and

consumes 1.21 times less energy per image- (EPI) than the corresponding best available

convolution-based structure. It involves 2.6 times less ADP and consumes 1.48 times less EPI

than the parallel lifting-based structure.

4

HD Resolution

Intra Prediction

Architecture for

H.264 Decoder

High performance video standards use prediction techniques to achieve high picture

quality at low bit rates. The type of prediction decides the bit rates and the image

quality. Intra Prediction achieves high video quality with significant reduction in bit

rate. This paper presents novel area optimized architecture for Intra prediction of

H.264 decoding at HDTV resolution. The architecture has been validated on a

Xilinx Virtex-5 FPGA based platform and achieved a frame rate of 64 fps. The

architecture is based on multi-level memory hierarchy to reduce latency and ensure

optimum resources utilization. It removes redundancy by reusing same functional

blocks across different modes. The proposed architecture uses only 13% of the total

LUTs available on the Xilinx FPGA XC5VLX50T.

Digital

Image

Processing

2012