Digital Integrated Circuits for Communication

Class 04

Overview

Static CMOS

Conventional Static CMOS Logic

Ratioed Logic

Pass Transistor/Transmission Gate Logic

Dynamic CMOS Logic

Domino

np-CMOS

Combinational vs. Sequential Logic

Logic

Circuit

Logic

CircuitOut

OutInIn

(a) Combinational (b) Sequential

State

Output = f(In) Output = f(In, Previous In)

Static CMOS Circuit

At every point in time (except during the switching transients) each gate output is connected to either

VDD or Vss via a low-resistive path.

The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during

switching periods).

This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

Static CMOSVDD

VSS

PUN

PDN

In1

In2

In3

F = G

In1

In2

In3

PUN and PDN are Dual Networks

PMOS Only

NMOS Only

NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high

X Y

A B

Y = X if A and B

X Y

A

B Y = X if A OR B

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors in Series/Parallel Connection

X Y

A B

Y = X if A AND B = A + B

X Y

A

B Y = X if A OR B = AB

PMOS Transistors pass a “strong” 1 but a “weak” 0

PMOS switch closes when switch control input is low

Complementary CMOS Logic Style Construction (cont.)

Example Gate: NAND

Example Gate: NOR

Example Gate: COMPLEX CMOS GATE

VDD

A

B

C

D

D

A

B C

OUT = D + A• (B+C)

Standard Cell Layout Methodology

VDD

VSS

Well

signalsRouting Channel

metal1

polysilicon

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Dynamic CMOSIn static circuits at every point in time

(except when switching) the output is connected to either GND or VDD via a low resistance path.fan-in of n requires 2n (n N-type + n P-type)

devices

Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.requires on n + 2 (n+1 N-type + 1 P-type)

transistors

15

Dynamic Gate

In1

In2 PDN

In3

Me

Mp

Clk

Clk

Out

CL

Out

Clk

Clk

A

BC

Mp

Me

Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

on

off

1

off

on

((AB)+C)

16

Conditions on OutputOnce the output of a dynamic gate is

discharged, it cannot be charged again until the next precharge operation.

Inputs to the gate can make at most one transition during evaluation.

Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

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Properties of Dynamic GatesOverall power dissipation usually higher

than static CMOSno static current path ever exists between VDD

and GND (including Psc)no glitchinghigher transition probabilitiesextra load on Clk

PDN starts to work as soon as the input signals exceed VTn, so VLT, VIH and VIL equal to VTn

low noise margin (NML)

Needs a precharge/evaluate clock

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Issues in Dynamic Design 1: Charge Leakage

CL

Clk

Clk

Out

A

Mp

Me

Leakage sources

CLK

VOut

Precharge

Evaluate

Dominant component is subthreshold current

19

Solution to Charge Leakage

CL

Clk

Clk

Me

Mp

A

B

Out

Mkp

Same approach as level restorer for pass-transistor logic

Keeper

20

Issues in Dynamic Design 2: Charge Sharing

CL

Clk

Clk

CA

CB

B=0

A

OutMp

Me

Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness

21

Charge Sharing Example

CL=50fF

Clk

Clk

A A

B B B !B

CC

Out

Ca=15fF

Cc=15fF

Cb=15fF

Cd=10fF

22

Issues in Dynamic Design Clock Feedthrough

CL

Clk

Clk

B

A

OutMp

Me

Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.

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Cascading Dynamic Gates

Clk

Clk

Out1

In

Mp

Me

Mp

Me

Clk

Clk

Out2

V

t

Clk

In

Out1

Out2V

VTn

Only 0 1 transitions allowed at inputs!

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Domino Logic

In1

In2 PDN

In3

Me

Mp

Clk

ClkOut1

In4 PDN

In5

Me

Mp

Clk

ClkOut2

Mkp

1 11 0

0 00 1

Domino LogicDomino logic is a CMOS-based evolution of the

dynamic logic techniques based on either PMOS or NMOS transistors.

It was developed to speed up circuits.In Dynamic Logic, a problem arises when cascading

one gate to the next. The precharge "1" state of the first gate may cause

the second gate to discharge prematurely, before the first gate has reached its correct state.

This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.

Domino Logicvarious solutions to the problem of how to cascade dynamic

logic gates. One solution is Domino Logic, which inserts an ordinary

static inverter between stages. While this might seem to defeat the point of dynamic logic,

since the inverter has a PFET (one of the main goals of Dynamic Logic is to avoid PFETs where possible, due to speed),

Two reasons it works well. First, there is no fanout to multiple PFETs. The dynamic gate connects to exactly one inverter, so the

gate is still very fast. And since the inverter connects to only NFETs in dynamic

logic gates, it too is very fast. Second, the PFET in an inverter can be made smaller than in some types of logic gates.

Domino LogicIn a domino logic cascade structure consisting of

several stages, the evaluation of each stage ripples the next stage evaluation,

similar to a domino falling one after the other. Once fallen, the node states cannot return to "1"

(until the next clock cycle) just as dominos, once fallen, cannot stand up.

The structure is hence called Domino CMOS Logic.

It contrasts with other solutions to the cascade problem in which cascading is interrupted by clocks or other means.

Important Domino Logic features:They have smaller areas than conventional

CMOS logic (as does all Dynamic Logic).Parasitic capacitances are smaller so that

higher operating speeds are possible.Operation is free of glitches as each gate can

make only one transition.Only non-inverting structures are possible

because of the presence of inverting buffer.Charge distribution may be a problem.