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LAB REPORT ON

Digital Logic Design

MC-218

Submitted By ..............................

Session 2014-15

Fourth Semester `

Delhi Technological University

(Formerly Delhi College of Engineering) Shahbad Daulatpur, Delhi



INDEX

S. No. Experiment Date Signature

1 Verification of logic gates (AND, OR, NAND, NOR, XOR, X-NOR) using truth tables.

2 To make all gates using universal gates

3 To design half adder and full adder using logic gates.

4 To design half Subtractor and full subtractor using logic gates.

5 Design 4 bit binary to gray and gray to binary code convertors using logic gates.

6 Implementation of Multiplexers and De- Multiplexers.

7 Implementation of Code Comparators and Parity Bit Generator

8 Implementation of J-K Flip Flop.

9 Verification of Synchronous 3-Bit Up

Counter and Synchronous 3-Bit Down Counter.

10 Verification of Bidirectional Register and Serial in Serial out (SISO) , Serial in Parallel out (SIPO) , Parallel in Parallel out(PIPO).



EXPERIMENT NO. 1

AIM : Verification of logic gates (AND, OR, NAND, NOR, XOR, X-NOR) using truth

tables.

APPARATUS : Digital IC Trainer Kit, cords

AND GATE

Circuit Diagram :

Truth Table :

Procedure :

1. Take no. of cords as per the required input and put in the slot for input.

2. Put the other end of the cord in the input slot of AND gate.

3. Join the output of the AND gate to the OUTPUT slot to see the required output.

OR GATE

Circuit Diagram :



Truth Table :

Procedure :


2. Put the other end of the cord in the input slot of OR gate.

3. Join the output of the OR gate to the OUTPUT slot to see the required output.

NAND GATE

Circuit Diagram :

Truth Table :

Procedure :




2. Put the other end of the cord in the input slot of NAND gate.

3. Join the output of the NAND gate to the OUTPUT slot to see the required output.

NOR GATE

Circuit Diagram :

Truth Table :

Procedure :


2. Put the other end of the cord in the input slot of NOR gate.

3. Join the output of the NOR gate to the OUTPUT slot to see the required output.

XOR GATE

Circuit Diagram :



Truth Table :

Procedure :


2. Put the other end of the cord in the input slot of XOR gate.

3. Join the output of the XOR gate to the OUTPUT slot to see the required output.

X-NOR GATE

Circuit Diagram :

Truth Table :

RESULT : All circuits are working and are verified by the truth tables.



EXPERIMENT NO. 2

AIM : To make all gates using universal gates.


THEORY : NAND and NOR gates are known as universal gates as all the logic gates

can be constructed using only these two gates.

AND gate using NAND gates

Circuit Diagram :

Procedure :


2. Put the other end of the cord in the input slot of NAND gate. Here all the gates used

are NAND gates only.

3. Now join the output to the input of the other gates to complete the circuit and at

last join to the OUTPUT of the system to see the required output.

Truth Table :

OR gate using NAND gates

Circuit Diagram :



Procedure :






Truth Table :

XOR gate using NAND gates

Circuit Diagram :

Procedure :








Truth Table :

X-NOR gate using NAND gates

Circuit Diagram :

Procedure :






Truth Table :



AND gate using NOR gates

Circuit Diagram :

Procedure :


2. Put the other end of the cord in the input slot of NOR gate. Here all the gates used

are NOR gates only.



Truth Table :

OR gate using NOR gates

Circuit Diagram :

Procedure :





are NOR gates only.



Truth Table :

XOR gate using NOR gates :

Circuit Diagram :

Procedure :



are NOR gates only.



Truth Table :



X-NOR gate using NOR gates

Circuit Diagram :

Procedure :



are NOR gates only.



Truth Table :

RESULT : All circuits are working and are verified by the truth tables.



EXPERIMENT NO. 3

AIM : To design half adder and full adder using logic gates.


HALF ADDER

Circuit Diagram :

Truth Table :

Procedure:

1. Wire the circuit diagram as shown in circuit diagram.

2. Feed the logic signals from logic input switches and monitor the outputs using the

logic level output indicators.

3. Verify the Half Adder truth table.

FULL ADDER



Circuit Diagram :

Truth Table :

Procedure :

1. Wire the full adder circuit as shown in circuit diagram.

2. Feed the logic signals from logic input switches and monitor the outputs using the

logic level output indicators.

3. Verify the Full Adder truth table.

RESULT : The given adders have been designed and are showing the appropriate

results as per the truth tables.



EXPERIMENT NO. 4

AIM : To design half Subtractor and full subtractor using logic gates.


HALF SUBTRACTOR :

Circuit Diagram :

Truth Table :

Procedure:

1. Wire the circuit diagram as shown in circuit diagram.

2. Feed the logic signals from logic input switches and monitor the outputs using

the logic level output indicators. 3. Verify the Half Subtractor truth table.



FULL SUBTRACTOR :

Circuit Diagram :

Truth Table :

Procedure :

1. Wire the full adder circuit as shown in circuit diagram.

2. Feed the logic signals from logic input switches and monitor the outputs using the logic level output indicators.

3. Verify the Full Adder truth table.

RESULT : The given subtractors have been designed and are showing the appropriate results as per the truth tables.



EXPERIMENT NO. 5

AIM : Design 4 bit binary to gray and gray to binary code convertors using logic gates.


BINARY TO GRAY

Circuit Diagram :

Truth Table :

Procedure :

1. Wire the circuit as shown in circuit diagram.



2. Feed the logic signals from logic input switches and monitor the outputs

using the logic level output indicators.

3. Verify the Binary to Gray Code Convertor truth table.

GRAY TO BINARY

Circuit Diagram :

Truth Table :



Procedure :



the logic level output indicators. 3. Verify the Binary to Gray Code Convertor truth table.

RESULT : The given code convertors have been designed and are showing the appropriate results as per the truth tables.



EXPERIMENT NO. 6

AIM : Implementation of Multiplexers and De-Multiplexers.


MULTIPLEXER

CIRCUIT DIAGRAM

TRUTH TABLE

Procedure :



the logic level output indicators.



3. Verify the Multiplexer (2-1) truth table.

DE-MULTIPLEXER

CIRCUIT DIAGRAM

TRUTH TABLE

Procedure :




3. Verify the De-Multiplexer(1-2) truth table.

RESULT : The given Multiplexer and De-Multiplexer have been designed and are showing the appropriate results as per the truth tables.



EXPERIMENT NO. 7

AIM : Implementation of Code Comparators and Parity Bit Generator


Comparators

Circuit Diagram

Truth Table



Procedure :




3. Verify the Comparator truth table.

Parity Bit Generator

Circuit Diagram

Truth Table



Procedure :




3. Verify the Parity Bit truth table.

RESULT : The given Code Comparator and Parity Bit Generator have been designed and are showing the appropriate results as per the truth tables.



EXPERIMENT 8

AIM : Implementation of J-K Flip Flop.

APPARATUS : Software: Orcad Capture , Input Chips and Gates: NOT (7404) ,

NAND (7400) , NAND (7411).

PROCEDURE :

1. Open Capture CIS application.

2. Go to File -New -Project.

3. Give a project name and specify the directory to save the project. Click OK.

4. Select ‘Create a blank project’ and click OK.

5. A grid will appear on the screen.

6. Go to Place -Part -Add Library. Select ‘74 LS’ library and choose the required gate and place it on the grid.

7. Go to Place -Wire and connect the wires as required.

8. Click Place -Part -Add Library. Select ‘SOURCE’ library and choose the ‘DigClock’ option.

9. Set the ONTIME and OFFTIME of the DigClock as required.

10. Place the DigClock at the required inputs.

11. Go to PSpice -Create Netlist.

12. Again, click PSpice -New Simulation Profile and give a suitable name.

13. Set ‘Run to Time’ as 10us in the Simulation Settings and click OK.

14. Click Place -Marker -Voltage/Level Marker and place it at the desired inputs and outputs.

15. Go to Pspice -Run and the output will appear.



J-K Flip Flop

Circuit Diagram

Truth Table



Output

RESULT : The given flip flops are implemented by gates and are showing the appropriate results as per the truth tables.



EXPERIMENT 9

AIM : Verification of Synchronous 3-Bit Up Counter and Synchronous 3-Bit Down

Counter.


AND (7408) , OR (7432) , CHIP(74107)

PROCEDURE :


















Synchronous 3-Bit Up Counter

Circuit Diagram

Truth Table

Output



Synchronous 3-Bit Down Counter

Circuit Diagram

Truth Table

Output

RESULT : The given Counters are implemented by gates and are showing the appropriate results as per the truth tables.



EXPERIMENT 10

AIM : Verification of Bidirectional Register and Serial in Serial out (SISO) , Serial in Parallel out (SIPO) , Parallel in Parallel out(PIPO).


AND (7408) , OR (7432) , CHIP(7474)

PROCEDURE :


















Bidirectional Left Shift

Circuit Diagram

Output



Bidirectional Right Shift

Circuit Diagram

Output



Serial in Serial out (SISO)

Circuit Diagram

Output



Serial in Parallel out (SIPO)

Circuit Diagram

Output



Parallel in Parallel out (PIPO)

Circuit Diagram

Output

RESULT : The given Shift Registers are implemented by gates and are showing the appropriate results as per the truth tables.

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