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Textbook Chapter 3
Digital Logic: From Transistors to Gates
CMPE12 – Summer 2009 01-2
Transistor: building block of computers Microprocessors contain tons of transistors
Intel Montecito (2005): 1.72 billion Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple PowerPC G5 (2003): 58 million Intel 4004 (1971): 2500
The Transistor
CMPE12 – Summer 2009 01-3
The Transistor: Past and Present
CMPE12 – Summer 2009 01-4
Moore’s Law“The number of active components per chip will double every 18 months.”
CMPE12 – Summer 2009 01-5
GPU Speed Compared to CPU
CMPE12 – Summer 2009 01-6
Metal-Oxide-Semiconductor transistor
CMPE12 – Summer 2009 01-7
How big is a transistor? If a CPU die were as big as this whole
classroom… A transistor would be…
CMPE12 – Summer 2009 01-8
Logically, each transistor is used as a switch Combined to implement logic functions
AND, OR, NOT Combined to build higher-level structures
Adder, multiplexer, decoder, register, … Combined to build a processor
LC-3
What is a transistor?
CMPE12 – Summer 2009 01-9
n-type MOS transistorn-type MOS (nMOS)
when Gate has positive voltage,short circuit between #1 and #2(switch closed)
when Gate has zero voltage,open circuit between #1 and #2(switch open)
Gate = 1
Gate = 0Terminal #2 must be
connected to GND (0V).
CMPE12 – Summer 2009 01-10
p-type MOS transistorp-type is complementary to n-type
when Gate has positive voltage,open circuit between #1 and #2(switch open)
when Gate has zero voltage,short circuit between #1 and #2(switch closed)
Gate = 1
Gate = 0
Terminal #1 must beconnected to +2.9V in
this example.
CMPE12 – Summer 2009 01-11
Simple switch circuitSwitch open:No current through
circuitLight is offVout is +2.9V
Switch closed:Short circuit across
switchCurrent flowsLight is onVout is 0V
Switch-based circuits can easily represent two states:
on/off, open/closed, voltage/no voltage.
CMPE12 – Summer 2009 01-12
Digital Values for Analog Signals Use the switch behavior of MOS transistors to
implement logical functions: AND, OR, NOT Digital symbols:
We assign a range of analog voltages to each digital (logic) symbol
Assignment of voltage ranges depends on electrical properties of transistors being used
CMPE12 – Summer 2009 01-13
CMOS circuit CMOS is Complementary Metal Oxide Semiconductor Uses both n-type and p-type MOS transistors
p-type (pMOS)Attached to + voltagePulls output voltage UP when input is zero
n-type (nMOS)Attached to GNDPulls output voltage DOWN when input is one
CMPE12 – Summer 2009 01-14
Inverter (NOT gate)
In Out0 V 2.9 V
2.9 V 0 V
In Out0 1
1 0
CMPE12 – Summer 2009 01-15
Truth Table The most basic
representation of a logic function
Lists the output for all possible input combinations
How many rows of the truth table needed? 2#inputs
X Y …A B …
OutputsInputs
X Y …A B …
OutputsInputs
CMPE12 – Summer 2009 01-16
Truth Table: Inverter Inverted signals are
denoted with an overbar Or with a prime symbol
A’
Input Output
A Y = A’
CMPE12 – Summer 2009 01-17
Truth Table: AND Gate The result of an AND
operation is 1 if and only if all inputs are 1
Depict AND by the multiplication symbol A·B
Or by lumping the signals together AB
We don’t really build these gates…
Inputs Output
A B Y = A · B
CMPE12 – Summer 2009 01-18
NAND gate (NOT-AND)
A B C0 0 10 1 11 0 11 1 0
Note: Parallel structure on top, serial on bottom.
CMPE12 – Summer 2009 01-19
AND gate
Add an inverter to a NAND.
A B C
0 0 0
0 1 0
1 0 0
1 1 1
CMPE12 – Summer 2009 01-20
Truth Table: OR Gate The result of an OR
operation is 1 if and only if any inputs are 1
Depict OR by the addition symbol A+B
Inputs Output
A B Y = A + B
CMPE12 – Summer 2009 01-21
NOR Gate: NOT-OR
A B C
0 0 1
0 1 0
1 0 0
1 1 0
Note: Serial structure on top, parallel on bottom.
CMPE12 – Summer 2009 01-22
OR gate
Add an inverter to a NOR gate.
A B C
0 0 0
0 1 1
1 0 1
1 1 1
CMPE12 – Summer 2009 01-23
About the Little Circle… The little circle is what inverts
CMPE12 – Summer 2009 01-27
Synthesis of AOI Gates AOI means AND-OR-Invert Truth table to a AOI gate (transistor-level) Recall:
PMOS (with the bubbles) on top NMOS (no bubbles) on bottom Series structure makes AND Parallel structure makes OR
CMPE12 – Summer 2009 01-28
Synthesis of AOI Gates Method 1: sum of products
Start with ones Build “pull-up” branch first
Method 2: sum of products Start with zeros Build “pull-down” branch first
Use inverters to complement inputs and output Which method?
Depends on the truth table More ones: method 1 More zeros: method 2
CMPE12 – Summer 2009 01-29
Synthesis of AOI Gates Method 1: Sum of products for Y
Cover the ones Build “pull-up” branch first using inverted inputs Derive “pull-down” branch as the dual of pull-up
branch Y=
VDD
Y
VSS
A B C Y0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 0
CMPE12 – Summer 2009 01-30
Synthesis of AOI Gates Method 2: Sum of products for Y’
Cover the zeros Build “pull-down” branch first, using asserted inputs Derive “pull-up” branch as a dual of the pull-down
branch Y’=
VDD
Y
VSS
A B C Y0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 0
CMPE12 – Summer 2009 01-31
Recommended exercisesCombinational circuits Ex 3.5, 3.6, 3.7, 3.8, 3.9 Ex 3.11, 3.12, 3.18 Ex 3.20, 3.22, 3.23, 3.24 with TA/Tut Ex 3.30, 3.31, 3.35 Ex 3.44