digital signal processors for mobile phone terminals - eeingrid/ee213a/lectures/ueda_class.pdf ·...

K. Ueda, '99 VLSI Circuits Short Course

Digital Signal Processorsfor Mobile Phone Terminals

Katsuhiko Ueda

Matsushita Electric Ind. Co., Ltd.



Abstract

- This talk will discuss the role of the DSP in the terminal and how to achieve high performance with low power consumption.

- Mobile phone system is moving rapidly into mobile multimedia era. A DSP architecture suitable for this new era will be also discussed.

- A DSP is one of the key components in a digital cellular phone terminal.

1


Outline

1. The role of DSP in cellular phone terminal.

5. Summary.

4. Mobile multimedia DSP.

3. Issues for DSP in next generation mobile phone systems.

2. How to achieve high performance with low power consumption.

2


Architecture of Portable Phone Terminal

Microcomputer Keypad/Display

-----

Role of DSP- Speech CODEC- Channel CODEC- Equalizer- Mod/Demodulator

Receiver

Synthesizer

Demodulator

Speaker

Microphone

Transmitter Modulator

Channel CODECEqualizer

CODECSpeech

3


1 TDMA Frame (40ms)

125us (8KHz)

-> 2,560bits/40ms -> 64kbps(8bits*8KHz)

8bits

(u-Law)

1 slot (~6.7ms, 7kbps)

Receiver

Synthesizer

Demodulator

SpeakerMicrophone

Transmitter Modulator

Channel CODEC CODECSpeech

Speech: 138bits/40ms -> 3.45kbps

FEC: 86bits/40ms -> 2.15kbps

Total: 5.6kbps

User 1 User 2 User 3 User 4 User 5 User 6 User 1User 642kbps

Relationship between Speech sig. and Tx sig. (PDC)

Point A

Point B

Point A

Point B

4


Speech CODEC

DigitizedInput Speech

Signal

Code Book Synthesis Filter

SpectrumAnalysis

Gain

Bit rate[kbps]

[MOPS]

10 200

10

20

5

1

15

PSI-CELP

13kbpsVSELP

RPE-LTP11.2kbpsVSELP

Parameterspeech signal

Minimizing the differencebetween input speech

signal and synthesized

5


Dedicated DSP for Portable Phone

BASIC DSP

Dedicated

DSP

for Portable Phone

DPU

SAT

ALU

REG

(ACC)

MUL

DATA MEMORY

MEMORY X

MEMORY Y

POINTER UNIT

POINTER

ADR CTRL(ex. modulo, bit reverse)

CONTROL

INST

MEMORY

POINTER

ADR CTRL(ex. repeat, loop)

DECODER

I/O

SERI AL

PARALLEL

DMA CTRL

n- Increase Performance by adding accelerators

- Reduce Power consumption

Pc f*c*v^2 f: frequency, c: capacitance v: voltage

6


A DSP Architecture for Portable Phone Terminal

Redundant binary number system

Dedicated MAC unit

Specialmemory

scheme torealize doublespeed MAC

Viterbi accelerator

A BUS 16B BUS 16

MACSAT

BSFT

DPU

INST ROM

ALU

M BUS 16

ACC

DATAREGS

RB-MAC

PU

PARALLEL

ACS

DATA MEMORY

SERIAL

I/O

IR

DEC

IP

cc

sp STACK

PROGRAMCONTROLData ROM AMA

AMB

da

CLK

GENPLL

EXT

CLK

DSP-CORE

DMA CONT

Double Access

Data RAM

Double speed MAC scheme

7


16-bit 16-bit

A-BUSB-BUS

MEMORY Y

(MY)

16-bit

16-bit16-bit

EVENSIDE

ODDSIDE

MEMORY X

(MX)

16-bit

16-bit16-bit

EVENSIDE

ODDSIDE

MULTIPLIER

ACC

ADDER

32-bit

40-bit

PIPELINE REG

MAC UNIT

TEMP REG TEMP REG

POINTER Y

(PY)

POINTER X

(PX)

BARREL SHIFTER

1 MACHINE

CYCLE

1/2 MACHINE

CYCLE

1/2 MACHINE

CYCLE

D(2x)

D(2x+1)

D(2x+2)

D(2x+3)

D(2x+3)

D(2x+5)

D(2x)

D(2x+1)

D(2x+2)

D(2x+3)

D(2x+3)

D(2x+5)

D(2x) D(2x+1) D(2x+2) D(2x+3) D(2x+4) D(2x+5)

D(2y) D(2y+1) D(2y+2) D(2y+3) D(2y+4) D(2y+5)

D(2x)

*

D(2y)

D(2x+1)

*

D(2y+1)

Output of MX

TEMPREG

A-BUS

B-BUS

MULTIPLIERD(2x+2)

*

D(2y+2)

D(2x+3)

*

D(2y+3)

D(2x+4)

*

D(2y+4)

D(2x+5)

*

D(2y+5)

1 cycle

0.5 cycle

Double Speed MAC Scheme 8


Accelerator for Viterbi Decoding

- Normal operation: The ALU is used as

a 16-bit processing unit.

Upper 8-bits Lower 8-bits

SHIFT REG

ALU

COMPARATOR REG

Add

Select

Compare

PM0(t-1)

PM1(t-1)

PM0(t)BMa(t)

BMb(t)

BMa(t) BMb(t)PM0(t-1) PM1(t-1)

PM0(t) = min[(PM0(t-1)+BMa(t)),

(PM1(t-1)+BMb(t))]

Two Adds, one Compare

and one Select -> ACS operation - ACS operation: The ALU is used as

two 8-bit adders.

9


Comparison of the number of clock cycles needed to realizean 11.2kbps VSELP CODEC.

Effect of Accelerators

DSP w/o MAC &Viterbi Accelerators

0

20

40

60

80

100[%]

Misc

ALU

MAC

Block FloatingError Correction

- 11.4%

- 8%

Total: - 33.1%

- 9.0%

- 4.7%

DSP w/ MAC &Viterbi Accelerators

10


y(0)=c(0)x(0)+c(1)x(-1)+c(2)x(-2)+c(3)x(-3)+

y(1)=c(0)x(1)+c(1)x(0)+c(2)x(-1)+c(3)x(-2)+

y(2)=c(0)x(2)+c(1)x(1)+c(2)x(0)+c(3)x(-1)+

FIR Filtering: tow outputs in parallel with delay register

Dual MAC Scheme

y(3)=c(0)x(3)+c(1)x(2)+c(2)x(1)+c(3)x(0)+

MAC1

Acc1

MAC0

Acc0

REGx(n-i+1) x(n-i)c(i) c(i)

# of MACoperations

# of Memoryreads

SingleMAC

DualMAC

Dual MACwith REG

N N N

2N 2N N

Low power consumption

11


ACC

P-Reg 1

RBMU

P-Reg 2

RTBC

RBAU

RBA 1 RBA 2

RBA 3

16 b 16 b

24 b 24 b

40 b

40 b

A-BUS

B-BUS

MUL0.5 cycle

ACC0.5 cycle

RB->B CNV0.5 cycle

RBMU : Redundant Binary Multiply UnitRBAU : Redundant Binary Accumulation UnitRTBC : Redundant Binary Digit to Binary Digit Conversion Unit

0 20 40 60 80 100

ConvMmux1Preg2

Partial Product Gen.Encoder

FA Tree1(BW)RBA Tree1(RB)

Preg1 FA Tree2(BW)RBA Tree2(RB)

BW-MAC

RB-MAC

Power Consumption Ratio normalized to a BW-MAC

[%]

RB-MAC

MAC Unit using Redundant Binary Number 12


Speaker

Microphone

Transmitter

Audio I/F

Keypad/Display

MicrocomputerTDMA Controller

A System LSI realizing Base Band Processing & Control

0.35 um CMOS2.5 Million9.26x10.0mm11x11mm CSP16b MCU MN102L(3MIPS)16b DSP MN1930(40MIPS)Demodulator, TDMA Controller,VCO, etc.

Features of the LSI

Process Tech.# of TransistorsDie SizePackage

Integrated IP

Receiver

Synthesizer

Demodulator

Modulator

Digital SignalProcessor

Misc VCO

13


Goal of the next generation Mobile Phone System

Current System(PDC)

5.6 / 11.2 kbps

Next GenerationSystem

(W-CDMA)

8 kbps ~ 2 Mbps

Video Phone

High SpeedWirelessNetwork

High Bit Rate Data Transfer

-> MORE cycles for error correction

Video CODEC Capability

System Requirements

-> MORE data input/output to/from DSP

Of course, LOW POWER

14

Hello


FreqTime

f1 f2 f3 f4

f2 A

BA B

Analog System

FDMA (Frequency Division Multiple Access)

Increasing Capability of Access Systems

f1

Freq

f1,c2

A

BTime c1c2 Digital System

ex. IS-95, W-CDMA

CDMA(Code Division Multiple Access)f1,c1

BA

Increase

- Channel Capacity - Data Speed

-> System Complexity (DSP Performance) Freq

Time

f1 f2 f3 f4

f1,s1

f1,s2

s

1

s

2

s

3

s

1

s

2

s

3

A

BA

BAB Digital System

ex. PDC, GSM, IS-54, PHS

TDMA (Time Division Multiple Access)

15


DUP

Receiver

Transmitter

De-spreadA/D

D/A Spread

Rake

Channel

CODEC

Speech/

VideoCODEC

Control unit

Low-power & High speed A/D

Low-power & High speed correlator

High speed Viterbi/ Turbo decoder

Data

Voice

Video

Base band SignalProcessing unitRF unit

High speed &Low-power LSI

DSP

Next Generation Mobile Phone Terminal and Issues to LSIs 16

Low-power Video/

Audio CODEC LSI


DSP Architecture for the Next Generation System

M BUS

DPP

Data

Adrs

AMA

AMB

regs Instruction

Memory

IOU

CKU

CORE

16

CKU: Clock control Unit

DPP: Direct Parallel Port

DPU: Data Processing Unit

ICU: Interrupt Control Unit

IOU: data I/O Unit

PCU: Program flow Control Unit

PU: Pointer Unit

- RF- ADC,DAC- Spreading/ Despreading

Wide bandwidth

to/from DSP

- Trace back

- Modulo

- Bit reverse

PU

PCU

ICU

High Performance Processing Unit

for Viterbi Decoding

DPU

A B

Data Memory

17


Dual ACS Operation

T-1 T

PM0

PM1

PM0'

PM1'

2 path metrics are updated in 1 cycle

AU0AU1 ALUCOMP

CMPR

ASR1 ASR2

32

32

Data

Memory

PM1 PM0

{BM1,BM0}

{BM1+PM1}

{BM0+PM0}< >

{PM1,PM0}

{BM0+PM1}{BM1+PM0}

{BM0+PM1}

{BM1+PM0}< >

to Data Memory

register

{BM1+PM1}{BM0+PM0}

to Data Memory

Conventional

This scheme

8 Kbps

(VOICE)

32 Kbps

(DATA)

64 Kbps

(DATA)

20 40 60 80

Data Rate

[MIPS]

18


Clock frequencyTechnologyNumber of devicesDie sizeSupply voltage

Performance

67.5MHz(14.8nsec)0.25um-CMOS(4-Metal)7,670KTr.9.41 x 9.22(=86.76)mm^21.8V(Internal), 3.3V(IO)4GOPS15frames/sec(CIF CODEC)

Features

DSP Core DSP Core

Double

Buffer

Double

Buffer

Shared

Memory

Local

MemoryLocal

Memory

DMA Controller

SDRAM

Dedicated

Engine

Dedicated

EngineVideo

I/F

Host

I/F

DA

AD

Video

Out

Video

In

CPU

Main-ProcessorSub-Processor

Shared

Register

DSP for Wireless Video Phone 19


1. DSP is one of key components in portable phone terminal and high performance with low power consumption is essential factor.

2. In the mobile multimedia era, new DSPs with higher performance and increased functionality will be necessary.

3. DSP for portable phone must keep on achieving

MORE MIPS and LESS power consumption.

Summary 20


[5] I. Verbauwhede and M. Touriguian, "Low Power DSP Engine for Wireless Communications," Journal of VLSI Signal Processing 18, pp.177-186, 1998.

[2] K. Honma and O. Kato, "Trends of research and development in Europe and America," Journal of The IEICE, Vol.78, no.2, pp.173-178, 1995.

[1] K. Ueda, T. Sugimura, et. al., "A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption," IEICE Transaction, Vol. E78-C, No.12, pp.1709-1716, 1995.

[3] H. Kabuo, M. Okamoto, et. al., "An 80 MOPS-Peak High-Speed and Low-Power-Consumption 16-bit Digital Signal Processor," IEEE JSSC, Vol. 31, No. 4, pp.494-503, 1996.

[7] M. Okamoto K. Stone, et. al., "A High Performance DSP Architecture for Next Generation Mobile Phone Systems," IEEE DSP Workshop,1998.

[9] S. Kurohmaru, M. Matsuo, et. al., "A MPEG4 Programmable Codec DSP with an Embedded Pre/Post-processing Engine," IEEE CICC,1999.

[4] A. P. Chandrakasan, S. Sheng, et. al., "Low-power CMOS digital design," IEEE JSSC, Vol. 27, No. 4, pp.473-484, 1992.

[References]

[8] T. Ishikawa, H. Suzuki, et al., "W-CDMA hardware-related issues," IEEE ICCT,1998.

[6] N. Nakajima, H. Shibata, et al., "Baseband System LSI for Cellular Mobile Telephone," Matsushita Technical Journal, pp.46-52, 1999.

Mobile Phone for Internet & Data Communication

Panasonic P502i

Applications- E-mail- Web Browsing- Banking- Locating combining car navigation systemetc.

Ex. i Mode system provided by NTT DoCoMo

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