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Microelectronics Section ESA UNCLASSIFIED –For Official Use (1) 14. Oct 2011

Digital System-On-Chip Digital System-On-Chip components at ESAcomponents at ESA

ASIC technology platforms and converters

Standard microprocessor components

Components with dedicated DSP function

Roland Weigand, Laurent Hili

European Space Agency

Microelectronics Section

MEWS 24, Tsukuba, Japan

Digital System-On-Chip components at ESA MEWS 24


Outline• ASIC platforms

– Current technologies (180 – 150 nm)

– New technologies: 90 nm (UMC), 65 nm (ST)

– Converters: ADC, DAC, HSSL

• Standard SPARC V8 microprocessor components– LEON2: AT7913E, AT697

– LEON3: SCOC3

– LEON4: NGMP – QUADLION

• Components with dedicated DSP functionality– FFTC: Fast Fourier Transform Co-processor

– AGGA4: GNSS baseband processor for GPS, Galileo, Glonass, Compass

– CWICOM: CCSDS Wavelet Image Compression ASIC

– HPDP: High Performance Data Processor

– Smart image sensors for sun-sensors and star-trackers



ESTECHQ

ESAC

ESOC

ESRIN

2251 staff in total

1310 staff

293 staff

368 staff

207 staff

73 staff

European Space Research and Technology Centre

R&D, engineering and test centre

The ESA Microelectronics Sectionhttp://www.esa.int/TEC/Microelectronics

8 permanent staff

Directorate of Technical and Quality ManagementElectrical Engineering Department

Data Systems Division

http://www.google.co.uk/imgres?imgurl=http://qt.nokia.com/images/qt-in-use/customers/esa_logo.jpg&imgrefurl=http://qt.nokia.com/images/qt-in-use/customers/esa_logo.jpg/view&usg=__pr8FzCO8YxliHZLHcAWHflfSFcU=&h=378&w=957&sz=196&hl=en&start=1&zoom=1&um=1&itbs=1&tbnid=hF334y4jbuAyfM:&tbnh=58&tbnw=148&prev=/images%3Fq%3DESA%2Blogo%26um%3D1%26hl%3Den%26rlz%3D1T4ADBF_en-GBNL316NL316%26tbs%3Disch:1







Current ASIC platforms• Atmel ATC18RHA 180 nm (see Atmel presentation)

• DARE (Design Against Radiation Effects) library on UMC 180 nm– High total dose tolerance, mixed signal capability available– Area and power consuming library, limitations in memory compiler– 90 nm planned, but funding currently on-hold

• LFoundry 150 nm (Germany)– Mixed signal, 5V IO and NVM available, no radiation hardened library– ESCC Space process capability study with DLR and Tesat

http://www.dlr.de/qp/en/desktopdefault.aspx/tabid-3091/4699_read-6881/→ LFoundry Germany seems to be bankrupt → activity on hold ?

• Ramon Chips (Tower 180 nm, Israel)– SEU hardened library available for 180 nm, 130 nm in preparation– Mixed signal capability, embedded NVM TBD– Device qualification possible (MIL-STD-883 lot acceptance)– Export licence and commercial availability to be clarified

• XFAB 180 nm (Germany)– Mixed signal, 5V IO and NVM available– Radiation hardened standard cell library currently not available– No space experience so far, but radiation evaluation and rad-hard library planned



Motivation for DSM programme

Deep Sub Micron ASIC technologies are key for establishing European capabilities in the domain of:

Digital telecom payloads Improve European competitiveness on mobile processors and digital sub

channelisers (narrowband processors)

Enable technology for future multimedia satellites and flexible payloads with active antennas (broadband processors)

Earth Observation payloads SAR, altimetry, interferometry

Mass memories

High Speed Serial Links (HSSL > 1Gbps)

Navigation payloads Wideband signal generation

The DSM programme is managed and co-financed by ESA and CNES



Motivation for DSM programme

• Microelectronics technology developments are driven by telecom needs for future broadband and versatile payloads (mobile, multimedia, HDTV)

• Higher ASIC complexity– 20 … 30 Millions gates– Higher clock data path (≥ 400 MHz)– Higher power dissipation per ASIC (≥ 15 Watts)– Higher pin count package (flip chip ≥ 1600 pins)– Higher data rate interfaces (HSSL 6.25 Gbps)

• Faster and power efficient ADC and DAC– Analog input bandwidth 500 MHz instead of 150MHz – ADC and DAC data rate ≥ 1.5 Gsamples/s– High complexity antenna systems / beamforming

» Number of ADC ≥ 200» Number of DAC ≥ 200

– Need to reduce the power consumption per converters» Max power per ADC ≤ 1.5 Watt » Max power per DAC ≤ 1.5 Watt



Interfacing between DSM ASIC and broadband ADC / DAC

ADC DAC

12b

12b

12b

12b

SERDES 6.25 Gbps High Speed Serial Link (6.25 Gbps)

ASIC (65 nm)

Baseband processing

- Sub channeliser- Beam forming- Switch

2 x 750 Msps2 x 750 Msps

Broadband / low power ADC1.5 Gsps

Broadband / low power DAC1.5 Gsps

Quatuor device (65 nm)Quad high speed link

4 x 6.25 Gsps

Quatuor device (65 nm)



Broadband ADC / E2V

Features (EV10AS180):

10 bits ADC integrated 1:1/2/4 Demux (selectable) 2.2 Gsps conversion rate (full BW) 1.7 Watt low latency 4 clock cycles LVDS outputs 0.5 Vpp differential input (100 ohms) Power supplies: 5.2V, 3.3V and 2.5V Ci-CGA225 package B7HF200 SiGeC technology from Infineon

Performances

Single Tone Performance @ Fs=1.5Gsps : SFDR = -60 dBFS, ENOB = 8.5 Bit; SNR = 55 dBFS at Fin = 750 MHz @-12 dBFS SFDR = -60 dBFS, ENOB = 8.4 Bit; SNR = 53 dBFS at Fin = 1800 MHz @-12 dBFS

Broadband Performance: NPR = 44 dB at -13 dBFS Optimum Loading Factor in 1st Nyquist NPR = 43 dB at -13 dBFS Optimum Loading Factor in L-band

100 Krads radiation tolerant



Broadband DAC / E2V

Features (EV12DS130):

12 bits DAC integrated parallel Mux 4:1 / 2:1 (selectable) 3Gsps conversion rate 6GHz analog output BW 1.3 Watt low latency 4 clock cycles NRZ, RTZ, narrow RTZ, RF modes LVDS inputs 1 Vpp differnetial output (100 ohms) Power supplies: 3.3V digital, 3.3V and 5V analog Ci-CGA225 package B7HF200 SiGeC technology from Infineon

Performances

NPR @ -14dB loading factor, Fs = 3Gsps 1st Nyquist (NRZ/NRTZ) NPR=49db ENOB=9.7 bits 2nd Nyquist (NRTZ/RTZ) NPR=44db ENOB=8.8 bits 3rd Nyquist (RF) NPR=42db ENOB=8.4 bits

100 Krads radiation tolerant

This activity is under CNES contract



Broadband DAC / E2V

Comparison between NRZ, NRTZ, RTZ and RF modesMax output power versus frequency over the 3 Nyquist zones



ST 65nm CMOS technology

• 65nm-LP CMOS from ST France : European technology, ITAR free• 65nm CMOS commercially qualified in 2007• 65nm CMOS Core Process :

– Dual / Triple Gate Oxides– Dual / Triple Threshold Voltages for MOS Transistors– 7-9 Full Copper Dual Interconnect Levels– Low K

• Characteristics :

– 750 kgates/mm2– 2GHz stdcells– 5.7nW/(MHz x gates)– 1.25-7.5GBit/s HSSL modules

ST Rad Hard offer based on CMOS 65nm-LP commercial process Reliability and Radiation maximisation performed at design stages



ST 65nm / reliability enhancement

Systematic application of ST Design-in-Reliability (DiR) methodology (focusing HCI and NBTI) with dedicated tools for aging simulations• Specific layout rules for reliability enhancement• Study of tighter controls at process level• Analysis of reliability figures from Std qualification• ST has build an industrial flow which allows a full coverage of reliability effects all along

the product value chain.• Reliability tests will be performed during ESCC evaluation phase to confirm it



ST 65nm / radiation enhancement

• Rad-hard capabilities measured under ESA contracts (ST 130nm, 90nm, 65nm and 45nm)

– No current increase seen up to 100krad(Si) TID

• SEL-free with Deep-N well process option

• SEE/SETs fault injection techniques for Digital and Analog blocks sensitivity analysis

– Usage of existing Robust cells, TMR

– Hardening of clock-trees against SETs

– Shadowing of configuration registers + scrubbing

– Development of Rad-Hard new cells

– Layout techniques



ST 65nm CMOS technology / Space offer

Skyrob

(Rad Hard)

Skyrob

(Fast)

Corelib

(Commercial)

SEU rate

seu/bit/day (Geo)shielding 100mils Al

1E-9

Robust x250

1.8E-9Robust x110

2E-7

Timing

Set-up + delay (ps)

750

50% slower

500

As fast

500

Area

um2

26

X2 area

23

X1.7 area

13

Energy

pJ

4

X1.8

3.8

X1.7

2.2

Comparison for a DFFX3(drive 3)



ST 65nm high speed serial link

• High speed serial link will be offered in 2 versions:– IP core– Device 4 x 6.25 Gbps (Quatuor)

• SerDes features (1 lane)– BER < 10-14

– 1.25 Gbps to 6.25 Gbps– Differential CML input / output (serial interface)– 4 TAP programmable pre-emphasis– 4 TAP adaptative decision feedback equaliser (DFE)– Clock data recovery for pleisio synchronous operations– JTAG & BIST (PRBS for auto test)

• Quatuor features (4 lanes)– LVDS parallel interface 2 x 12 bits + 1 Data Ready– 8b/10b encoder– Up to 25 Gbps aggregated data rate (half duplex)– Supply voltages 1.2V and 2.5V– Sampling clock from 150 MHz to 1.5GHz– Power ~ 1W (worst case)



ST 65nm high speed serial link (Quatuor)

-100

-80

-60

-40

-20

0

20

40

60

80

100

-30 -20 -10 0 10 20 30 40

49krad

154kradRecovery

afterannealing

SERData

16b/20bencoder

SER

Clk

Framing /

Stamping /

CRC calculatio

n

6.25Gbps

ADC10/12bits1.5Ghz

16 bits20 bits

2 wires

~ Pll

Sampling clock

Reference clock

QUATUOR

Div42 Phases

ElasticBufferSynch4 x

4 x 48 bits

SERData

6.25Gbps16 bits

20 bits2 wires

SERData

6.25Gbps16 bits

20 bits2 wires

SERData

6.25Gbps16 bits

20 bits2 wires

12 bits

12 bits

Datardy lvds

Port ALvds/Reg

Port BLvds/Reg

Bus /

Speed aligner

4x48 bits

24 bits

24 bits

9.3793.75Mhz MCLK 312.5 Mhz

Div4 (12 or 8 bits)

37.5375Mhz

16b/20bencoder

16b/20bencoder

16b/20bencoder

Serdes S7

25 Gbps aggregated data rate

Receiver eye diagram openingENEA test campaign December 2009Device fully operational at 200 Krads



ST 65nm / test vehicles

TC1 (rad hard library):

• all cells from SKYROB lib (Rad Hard) ~ 25 cells• all cells from CORROB lib (Rad Tol) ~ 21 cells• commercial flip flop + TMR• hardened flip flop (but no TMR)• SRAM + ECC• 7 ring oscillators to characterise the process

TC2 (PLL 1st type):

• high performance multiphase PLL covering frequency range from 100MHz … 1 GHz• special IOs

• cold spare CMOS• cold spare LVDS• SSTL• I2C

TC3 (high speed serial link / HSSL):

• Quatuor / 4 x 6.25 Gbps (full duplex)

TC4 (commercial library subset):

• commercial library subset ~ 319 cells (extracted from CoreLib standard voltage)• balanced clock tree buffers ~ 58 cells



DSM 65nm, HSSL, ADC, DAC – current status

• DSM 65nm– Standards cells library definition done– Macros definition done– 1st library test vehicle (std cells) manufactured & preliminary

characterised– 2nd library test vehicle planned for Q3/11– 3rd library test vehicle (final version) planned for Q1/12– Planned in 2012, ESCC evaluation of library without package – Planned in 2012, design & prototyping of the high pin count flip

chip package ~ 1600 pins



• HSSL 6.25Gbps (Quatuor)

– 1st prototype manufactured

– Preliminary electric & radiation tests performed but not fully conclusive

– 2nd prototype redesign & manufacturing planned in 2012

– 2nd prototype ESCC evaluation planned ~ Q4/12

• Broadband ADC

– Full electric characterisation done

– ESCC evaluation on the way, planned to complete in Q1/12

– Objective 2012 to get the device registered in EPPL

• Broadband DAC

– Full electric characterisation done

– ESCC evaluation on the way, planned to complete in Q1/12

– Objective 2012 to get the device registered in EPPL

DSM 65nm, HSSL, ADC, DAC – current status



Spacewire Remote Terminal Controller - AT7913E• LEON2-FT SPARC V8 @ 50 MHz

• 4 + 4 kB instruction/data cache

• Meiko IEEE-754 FPU

• ADC/DAC interfaces

• Two SpaceWire links with RMAP

• Redundant CAN 2.0 link with DMA

• FIFO interface with DMA

• Up to 50 MHz system frequency

• Up to 200 Mbit/s SpaceWire data rate

• 349-pin MCGA with 50 mil pin spacing

• Californium SEU testing performed at ESAHeavy Ion test campaign planned with Atmel

• First missions:BepiColombo, SolarOrbiter

• Documentation, SMD and User Manual: http://www.atmel.com/dyn/products/product_card.asp?part_id=4595 http://microelectronics.esa.int/components/AT7913E_UserManual-2-4.pdf



AT697 SPARC V8 (LEON2FT) @ 100 MHz, PCI 2.2• Established on Atmel catalog (QML-Q, QML-V), data sheets, SMD available: http://www.atmel.com

• Atmel 180 nm, 360 kGates, 550 kbit memory

• Evaluation boards from Atmel / Aeroflex Gaisler

• ESCC evaluation/qualification to be completed in 2011

• Selected by numerous projects: ~ 400 FM orders (2009 – 2011)

• Previous generation: TSC695 (ERC32) Sparc V7 @ 25 MHz500 nm technology, ~ 3000 FM orders (2003 – 2011), still in use

• Packages:MQFP256, LGA349MCGA not availableany more



FF1 FF2 FF3

MajorityVoter

Q1

Q2

Q3

clock tree 3

clocktree 2

clocktree 1

D1 D2

D3

clk

D

Q

clk2

clk1

clk3

SET pulse

SET latched intoFF1 only

Q remains at correct value

SEU hardening in AT697: STMR = TMR with triple skewed clock

Triplicated clock tree

and skewed clocks

~ SET pulse length

by skewing the clocks, a glitch at D is latched at most in one of the 3 FF

Q = (Q1 and Q2) or (Q2 and Q3) or (Q1 and Q3)



LEON3FT based Microprocessor – SCOC3• Spacecraft Controller On-a Chip

http://www.astrium.eads.net/node.php?articleid=5360

– LEON3FT @ 80 MHz, GRFPU

– CCSDS TM/TC interface with X-strapping interface

– SpaceWire, 1553, CAN, UART

– Dual AMBA-AHB bus architecture

– Dual PROM/SRAM/SDRAM interface

– Basic SW development (BSP/drivers) ongoingECSS pre-qualification planned

– SW tools (simulator, IDE) available

– Data-sheet/user manual available on request

– To be established as standard component,commercialised by Astrium France

– FPGA-based Evaluation board (STARKIT)developed under CNES contract

– First missions: SEOSAT, ASTROTERRA (SPOT 6/7)CSO (3 French military satellites), KRS (Kazakhstan)

– Atmel 180 nm (1.8 Mgates + 2.2 Mbit memory)

– Package: LGA472 with 6-sigma columns (currently assembled in the US, to be transferred to Europe)



SCOC3 block diagram



NGMP: ESA's Next Generation Microprocessor

• 4x LEON4 CPU cores @ 400 MHz• L2 cache, 128-bit AHB processor bus, Branch prediction• 4 kByte instruction cache and 4 kByte data cache per core• Two shared double precision IEEE-754 FPUs• Multiple AHB bus structure to decouple processor, IO and debug transfers• Full MMU protection for processor and DMA IO peripherals• Timer and interrupt infrastructure supporting AMP configurations• Enhanced debug features:

DSU, trace buffers on PCI/AHB, performance counters• Debug link via Ethernet, JTAG, USB or RMAP• 64-bit DDR2 / SDRAM / PROM memory interface with background scrubbing unit• High-Speed-Serial link interfaces (based on ST HSSL, details TBD)• Spacewire router with 8 external Spacewire ports and 4 internal AHB DMA ports• PCI 2.3 32-bit 66 MHz link• 2 Ethernet links• MIL1553, SPI• UARTs, GPIOs

Target technology: 65 nm ST-Microelectronics



Next Generation Microprocessor (block diagram)



NGMP detailed block diagram part 1 (left side)



NGMP detailed block diagram part 2 (right side)



NGMP: ESA's Next Generation Microprocessor (status & roadmap)• Preliminary “GINA” study based on quad-core LEON3-SMP [DASIA 2006]

– ALR Pouponnot: “A Giga INstruction Architecture (GINA)”

• NGMP development started with Aeroflex-Gaisler in June 2009– PDR (verified VHDL-RTL) achieved in December 2010

– Preliminary Datasheet and Verification Report availablehttp://microelectronics.esa.int/ngmp/ngmp.htm

– FPGA prototypes on various boards available to the user community

– Development of SW environment (BSP, compiler, GRMON)

• NGMP QUADLION prototypes in (non rad-hard) commercial technology– Prototypes / evaluation boards available in Q3 2012

– Target technology eASIC Nextreme-2 ( 45 nm structured ASIC)

– Implementation at target speed (goal 400 MHz)

• Next phase: Proto-FM in rad-hard target technology – funding available– Radiation testing and functional validation

– Schedule uncertain, waiting for the ST 65 nm space library

• Final phase: FM manufacturing with bugfixes and user feedback – subject to funding

• Ongoing and planned SW activities related to NGMP and multi-core processors



NGMP Benchmarking• Benchmarks run at the same frequency (50 MHz) for all devices

→ differences in max clock frequency (NGMP = 400 MHz) to be considered

• SCOC3, AT7913 have similar performance as AT697

improvedcycles perinstruction(CPI)

good scalingon multi-threadedbenchmarks(4 cores) → almost x4



FFTC – Fast Fourier Transform Coprocessor• Original IP PowerFFT from Eonic ( http://www.eonic.com/index.asp?item=32 )

• Space development with Astrium Germany, features (→ block diagram next slides):– 4 parallel Radix-2 FFT butterfly engines @ 128 MHz

– ALU with ADD / SUB / MULTIPLY / Conjugate operations @ 128 MHz

– Various combinations possible between FFT and ALU operations

– Data paths in complex double-precision floating point arithmetic

– 64-bit input and output data ports and 4 parallel 57-bit SDRAM ports @ 100 MHz

– Conversion between various integer and floating point formats at each data port

– Cross-bar switch allowing concurrent data streams between data ports and processor

– EDAC protection on internal/external memories, SEU hardened flip-flops/latches

– 1 kpoint complex FFT in 10 s, 1 Mpoint complex FFT in 21 ms

– 100 Msamples/sec sustainded throughput

• Applications: Radar (SAR) processing, Spectrometers, Data compression

• Atmel 180 nm, 1.5 Mgates logic (pre-layout), 205 kbit block memory

• Package SPGA 625 (TBD, qualification pending)

• Tapeout Q4 / 2009, prototypes Q4 / 2010, validation ongoing

• Commercialisation planned as standard component



FFTC Architecture



FFTC Processing core



AGGA4 – Advanced GPS Galileo ASIC

• Applications: Precise Orbit Determination (POD) and Radio Occultation (RO)

• Successor of AGGA2 ( http://www.atmel.com/dyn/resources/prod_documents/doc3b8bc303e1b06.pdf ), which was used in GRAS (GNSS Receiver for Atmospheric Sounding) on METOP

• AGGA4 Features → block diagram next slide– LEON2-FT with standard peripherals (SpW, MIL1553, UART, PIO, SPI, Timers)

– GNSS front-end module allowing to connect 4 antennas with digital beamforming

– FFT processing module for fast acquisition to resolve Doppler uncertainty

– 36 single-frequency / dual-code GNSS base-band channels, containing each of them:– Final downconversion with code/carrier NCOs– 5 complex (I/Q) correlators per channel: 5 ( EE, E, punctual, L, LL) for BOC tracking– Code generators with LFSR (required for very long codes e.g. GPS L2CL) and

code memories (required for Galileo and other signals)– Code/carrier loop aiding unit to compensate Doppler drift

• Development with EADS Astrium Germany– Commercialisation as standard component

– Atmel 180 nm, ~ 3.5 Mgates logic (pre-layout, 140000 FF/latches), 878 Kbit memory

– Package MQFP 352

– Tapeout planned in Q4 / 2011



AGGA4 block diagram



AGGA4 GNSS core



AGGA4 - Applications

• Precise Orbit Determination to support Earth Observation applications

– Gravity and magnetic field missions

– Relative positioning

– Interferometry

– Altimetry

• Radio-Occultation

– measure Doppler shift

– derive bending of GNSS signal byrefraction in the atmosphere

– derive vertical profiles (temperature,pressure, humidity)



CWICOM – CCSDS Wavelet Image Compression ASIC

• Development with Astrium France/Germany– Implements CCSDS Wavelet Image Compression Standard 122.0-B-1

– Output data according to CCSDS packet protocol CCSDS 133.0-B-1

– Lossless and lossy compression @ 60 Mpixels/sec (64 MHz clock)

– Spacewire and SPI serial links as command (and slow data) interfaces

– 16-bit parallel interfaces (1 pixel per clock cycle) for video input and output data

– Atmel 180 nm, 1.1 Mgates logic (32769 flip-flops) 4.4 Mbit on-chip RAM (68 instances)

– First layout ongoing, tapeout Q4 / 2011

– Commercialisation as standard ASIC



HPDP High PerformanceData Processor

• Development withAstrium Germanyand ISD Greece

• Technology ST 65 nm

• Features– Based on PACT XPP III Array Processor

( http://www.pactxpp.com/ )

– More than 5 Giga operations per second

– 40x 16-bit ALU Elements @ 100 MHz

– 2x Harvard type VLIW 16-bit processor cores (FNCs) running at 50MHz

– 256 Kbit high-speed on-chip RAM with EDAC

– External SRAM/SDRAM interface with EDAC, bandwidth of up to 200 Mbyte/s

– 4 x 1.6 Gbit/s Streaming Ports

– 3 SpaceWire interfaces @ 100 Mbps

– SW tools: SDE, cycle accurate simulator, graphical debugging tools, libraries/APIs



Smart CMOS Image sensors for Sun Sensors and Star Trackers

• SSOC (Sun Sensor On-Chip) Development with CMOSIS, Belgium, BAE Systems and Selex Galileo

• UMC 180 nm CMOS Image Sensor (CIS) with DARE digital library

• Features of present generation– Plug & play: finds the sun by itself

– TID hard pixel array

– Windowing for object tracking

– Defect pixel filtering

– Image pre-processing (background subtraction, thresholding, object clustering, centroiding...)

– Spacewire interface

– On-chip regulators and oscillator (single 5V supply)

• Next generation sensors planned with enhanced processing

– EM = 2014, FM = 2016



Acknowledgements and contacts

Acknowledgements to companies and colleagues which are involved into the developments for having supplied inputs for this presentation:– For the DSM/ADC/DAC programme: ST Microelectronics, E2V and CNES

( Florence.Malou [at] cnes.fr, Jean-Louis.Venturin [at] cnes.fr )

– AT7913E: RUAG Sweden, Aeroflex Gaisler, Atmel, Jørgen Ilstad ( Jorgen.Ilstad [at] esa.int )

– AT697: Atmel France ( sparc-applab.hotline [at] nto.atmel.com )

– SCOC3: Astrium France Elancourt ( products [at] astrium.eads.net )

– NGMP: Aeroflex Gaisler Sweden ( info [at] gaisler.com )

– FFTC: Astrium Germany, Eonic and Martin Süß ( Martin.Suess [at] esa.int )

– AGGA4: Astrium Germany, Josep Roselló Guach ( Josep.Rosello [at] esa.int )

– CWICOM: Astrium France/Germany, Raffaele Vitulli ( Raffaele.Vitulli [at] esa.int )

– HPDP: Astrium Germany, ISD Greece, Roland Trautner ( Roland.Trautner [at] esa.int )

– SSOC: CMOSIS Belgium, Stephen Phil Airey ( stephen.airey [at] esa.int )

Further information can be obtained from the contact e-mails mentioned hereabove, or from the authors of this presentation

– Roland Weigand ( Roland.Weigand [at] esa.int ), Laurent Hili ( Laurent.Hili [at] esa.int )

Thank you for your attention – Questions?

ご清聴ありがとうございました

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