digitally assisted analog circuits - eecs at uc berkeleyboser/presentations/2004-05-18... ·...

Digitally Assisted Analog Circuits

Bernhard E. BoserUniversity of California, Berkeley

Department of Electrical Engineering and Computer Sciences

http://www.eecs.berkeley.edu/~boser

Digitally Assisted Analog Circuits © 2004 B. Boser 2

Integrated Circuit Trends� Moore�s Law

� Transistor count doubles every 2 years

� Rapidly improving circuit performance:� E.g. microprocessors:

� Clock rate doubles in 2.3 years� Performance doubles every 1.5 years

� Enables new functions, e.g. � digital video, � wireless LAN, WAN, 3G, �

� Analog circuit performance trends?� Present trends� Challenges� Opportunities


Analog Circuit Applications

Digital Signal Processing

Cellular telephony

Cameras

Disk drives

Fiberoptics

Optical communication

Air bag sensors

Networking

Audio

Video


Analog Circuit Performance (ADC)

1.0E+08

1.0E+09

1.0E+10

1.0E+11

1.0E+12

1.0E+13

1987 1992 1997 2002

FOM

1 [H

z-LS

B]

All ADCs: 2x in 6.5 years

Lead ADCs: 2x in 4.7 years

Res

olut

ion

X Sa

mpl

ing

Rat

e

Year

80-MS/sec12-Bits

5-GS/sec6-Bits


ADC Performance Projection2032

1.0E+08

1.0E+09

1.0E+10

1.0E+11

1.0E+12

1.0E+13

1987 1992 1997 2002

FOM

1 [H

z-LS

B]

“Software Radio”16-Bit1GHz


Analog-Digital Performance Comparison

150x

15 years

1

10

100

1000

1987 1995 2003

Rel

ativ

e Pe

rfor

man

ce

ADC (2x / 4.7 years)

µP MIPS (2x / 1.5 years)

10000


Analog-Digital Power Comparison1987 1995 2003

ADC Power/Conversion (0.5x / 2.7years)

Energy/Logic Transition (0.5x / 1.7years)

Lead µP Power/MIPS (0.5x / 3.4years)

1

0.1

14x

2.5x

Bet

ter

0.01

0.001


Analog-Digital Power Comparison

Digital

C gate, wiring capacitanceVDD supply voltagefCLK clock speed

� Reducing VDD lowers power� Power = f(scaling, C)

Analog

B resolution [Bits]VDD supply voltagefCLK clock speed

� Reducing VDD inreases power� Power = f(resolution, B)

CLKDDdig fCVP 2∝ CLKDD

B

ana fV

P22

∝


Analog Circuit Challenges

Power Dissipation

Speed

Matching LinearityNoise

Precision


Analog Precision Techniques

C

2C

2C

Vid Vod = 2 Vid

C

Gain = 2

Feedback

Gain = 100,000


Intrinsic Transistor Gain

0

5

10

15

20

25

30

35

40

45

0.0 0.1 0.2 0.3 0.4

0.18µm

0.25µm

0.35µm

0.5µm

g mr o

VDS [V]

25

5

Channel length L ↓Gain ↓

Scaling �hurts�


Consequences �� [Annema, TCAS99]:

� �The overall effect is that power consumption decreases with newer CMOS processes down to about 0.25 or 0.35 µm.�

� �The trend that power consumption increases with decreasing supply voltage was shown to be fundamental ��

� [Annema, PlanetAnalog, 2004, http://www.planetanalog.com/printableArticle.jhtml?articleID=17701355]� �In conclusion, analog circuits can benefit from technology scaling if

the supply voltages are not scaled down, unlike in their digitalcounterparts.�

� [Bult, ISSCC99]:� �Power dissipation generally increases if a circuit operates under

reduced signal swing conditions to maintain performance.�

� Scaling has no benefits?

http://www.planetanalog.com/printableArticle.jhtml?articleID=17701355


Scaling Benefits

0

10

20

30

40

50

60

-0.1 0.0 0.1 0.2 0.3 0.4 0.5VGS-VTH [V]

f T [G

Hz]

0.18µm

0.25µm

0.35µm

0.5µm

0

5

10

15

20

25

30

-0.1 0.0 0.1 0.2 0.3 0.4 0.5

VGS-VTH [V]

gm/I D

[1/V

]

0.18µm0.25µm

0.35µm

0.5µm

Square Law

Efficiency gm/ID

Intrinsic speed (fT)


Transistor Performance

0

50

100

150

200

250

300

350

400

-0.1 0.0 0.1 0.2 0.3 0.4 0.5

VGS-VTH [V]

f T⋅g

m/I D

[GH

z/V]

0.18µm

0.25µm

0.35µm

0.5µm

Scaled transistor:Significantly better performance at lower voltage


Technology Scaling� Device performance improves

� Speed (fT)� Power efficiency (gm / ID)

� Digital circuits� Capitalize on improved devices� Clock rate doubles every 2.3 years� Performance (MIPS, SPECint) doubles every 1.5 years

� Analog circuits� Low supply, intrinsic device gain negatively impacts precision� Relative performance increasingly lags that of digital circuits� Performance doubles in 5 years� Over 15 years, analog/digital performance gap is ~ 150x

� Is this also a �law�


Analog Circuit Challenges

Speed

Matching LinearityNoise

Matching and linearity constraints are not fundamentalPrecision

Power Dissipation


Analog Circuit NonlinearityDout,raw Dout

Vin Dout,raw

NonlinearAnalog-to-Digital

Converter

Digital Signal Processor

(DSP)

Vin Dout,raw Dout

( )( )( )

in

in

rawoutout

VVff

DfD

==

=−

−

1

,1

( )inrawout VfD =,


Open-Loop Amplification�Open loop�Precision Amplifier

+ Faster+ Lower Power+ Lower Noise+ Increased Signal

Range� Nonlinear

! Use DSP to linearize!

Practical?


Experimental Verification

REFERENCEAND BIAS

PIPELINEBACKEND

STAGE1SHA

CLK

LOGIC

� 12bit, 75MHz, 0.35µm, post-processor off chip� Based on commercial part (Analog Devices AD9235)


Measured INL

0 1000 2000 3000 4000-20

-10

0

10

20

Code

INL

[LS

B]

Post-Proc. OFF

Code


Measured INL

0 1000 2000 3000 4000-20

-10

0

10

20

Code

INL

[LS

B]

Post-Proc. OFFPost-Proc. ON

Code


INL Zoom (Post-Proc. ON)

0 1000 2000 3000 4000-1

-0.5

0

0.5

1

Code

INL

[LS

B]


Stage1 Amplifier Power

0

10

20

30

40

50

60

Pow

er [m

W]

-62% (33mW)

[Kelly, ISSCC 01](Closed-Loop)

This Work(Open-Loop)


Digital Nonlinearity Correction

SystemID

AnalogNonlinearity

DigitalInverse

Modulation

Dout,corrVin Dout

Parameters

� System ID determines optimum post distortion� Background operation tracks variations over time without

interrupting normal circuit operation


Digital Post-Processor� 8400 Gates, 64 bytes RAM, 64kBit ROM� Implementation in 0.35µm technology

Area=1.4mm2 (18%) Power=10.5mW (3.6%)

0

10

20

30

40

AmplifierSavings

Post-Processor

Pow

er [m

W]

Pipelined ADC(7.9 mm2)

Post-Processor


Analog / Digital Power Comparison"Number of logic gates with same energy consumption as a state-of-the-art B-bit ADC"

0

200,000

400,000

600,000

800,000

1,000,000

6 7 8 9 10 11 12 13 14 15 16ADC Resolution [B]

Num

ber o

f Gat

es

0.13µm

1.2µm

0.35µm


Analog / Digital Area Comparison

0

1,000

2,000

3,000

4,000

0 0.005 0.01 0.015 0.02Area [mm2]

Num

ber o

f Gat

es

0.13µm

1.2µm

0.35µm

8080 µP Core

Area of a 10pF integrated (linear) capacitor


Circuit IssuesPrecision Amplifier �Open loop�


Self-Heating

Vo2

Vi2

Vo1

Vi1

� Signal dependent current

� Signal dependent device temperature & characteristics

� Background calibration too slow to track changes


Device Interleaving

Vo2

Vi2

Vo1

Vi1

Interleaved layout " uniform temperature distribution


0 2 4 6 8 10

45

50

Tchi

p [o C

]

0 2 4 6 8 10-4048

Time [sec]

p1 [L

SB

]

Constant BiasReplica Bias

Reduced Temperature Sensitivity

Time [sec]


Conclusion� Technology scaling trends are only conditionally beneficial for

analog circuit performance

� Analog circuit improvements lag progress of digital functions

� Digitally assisted analog circuits offload accuracy constraints to digital processor

� Benefits:� Improved analog circuit performance� Profit from future technology scaling


Acknowledgements

� Boris Murmann, Mike Scott, Dimitrios Katsis, Anshi Liang

� Katsu Nakamura, Dan Kelly, Larry Singer

� Analog Devices for design re-use

� Funding from Analog Devices and UC MICRO


Book

http://www.wkap.nl/prod/b/1-4020-7839-0

Hardbound, May 2004, 175 pp.ISBN 1-4020-7839-0

eBook, April 2004ISBN 1-4020-7840-4

digitally assisted analog circuits - eecs at uc berkeleyboser/presentations/2004-05-18... ·...

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