diglab1 - introduction to xilinx schematic editor aug 28

8/18/2019 DIGLAB1 - Introduction to Xilinx Schematic Editor Aug 28

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THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

1

ECNG 2004

LABORATORY & PROJECT DESIGN IIhttp://myelearning.sta.uwi.edu/course/view.php?id=1678

Semester I, 2009/2010

1. GENERAL INFORMATION

Lab #: DIGLAB1

Name of the Lab:Introduction to the Xilinx Schematic Editor

Lab Weighting: - Estimated totalstudy hours1: 3½

Delivery mode: Lecture

Online

Lab

Other

Venue for the Lab: Electronics Laboratory

Lab Dependencies2 The theoretical background to this lab is provided in ECNG 1014

Theoretical content link: http://myelearning.sta.uwi.edu/course/view.php?id=684

Pre-Requisites – None

Recommended

prior knowledge

and skills3:

None

Course Staff Position/Role E-mail

Phone

Office OfficeHours

Marcus L George Instructor [email protected] ext3164 ElectronicsLab Office

Fridays

10am - 1pm


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THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

2

2. LAB LEARNING OUTCOMES

Upon successful completion of this lab assignment, students will be able to: CognitiveLevel

1. Demonstrate competence with the simulation and implementation of digital

systems utilizing Xilinx and the Spartan III FPGA development board.C

2. Understand the basics of Xilinx Schematic Editor

- Select macros for the creation of schematics

- Search for macros using the ‘symbol name filter’ feature

- Create a schematic using macros selected- Add wires to the schematic to interface macros

-

Add I/O markers to the design- Observe the internal structure of macros available from the Xilinx

symbol library.

- Obtain the datasheets for macros used in the editor using the

‘symbol info’ feature.

C

3. Create a 1-bit adder macro and use it to create a 4-bit adder macro. C

4. View the RTL Schematic of the system implemented. C

5. Perform both functional simulation(Simulate Behavioural Model) andtiming simulation(Simulate Post-Place and Route VHDL Model) for a

digital system using Modelsim 6.0SE/XE.

C

6. Create an implementation Constraints file for the design and assign package pins and downloading the implementation onto the FPGA

development board.

C


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DIGLAB1: Introduction to the Xilinx Schematic Editor

4

4. IN-LAB

Allotted Completion

Time:

3 hours

Required lab

Equipment:

1 printed copy of the DIGLAB1 manual (students must bring this copy to

the lab)

1 Computer

Spartan 3 Development board (including J-Tag cable & adaptor)

4.1. Introduction

You can build moderately complex logic circuits of up to several hundred gates wiring the SSI and

MSI IC’s. Logic synthesis programs are often used in digital system design. The logic circuit can

input a truth table, a circuit schematic (best for smaller circuits), or use a hardware description

language (HDL). Operation of the circuit is then simulated to make sure the logic design is correct.

The next step is typically to either design a custom VLSI IC (usually only justified for high volume

applications or applications with specialized requirements), or programmed into either a field

programmable gate array (FPGA) or a complex programmable logic device (CPLD). In this lab,we

will learn how to use the Xilinx ISE Tools to implement and simulate logic circuit designs from a

schematic.


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5

4.2. Creating a New Project

A project in ISE is a collection of all files necessary to create and download a design to the selected

device. To create a new project:

4.2.1. Select File > New Project.

4.2.2. In the New Project Wizard dialog box, enter the project name ‘My_4bit_Adder_’ in the

diagram below. You can browse to the desired directory using the browse button next to

the Project Location field.

4.2.3.

Now Click Next.


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4.2.4. In the New Project Wizard Device and Design Flow dialog box, use the pull-down arrow

to select the Value for each Property Name. Click in the field to access the pull down list.

Change the values as follows:

• Device Family: Spartan3

• Device: xc3s400/xc3s1000

• Package: ft256

• Speed Grade: -5

• Synthesis Tool: XST (VHDL/Verilog)

• Simulator: Modelsim

•

Generated Simulation Language: VHDL


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4.2.5.

Click Next

This will open a New Project dialog box.

Click Next! Then click Next again! Then click Finish.

4.2.6. In the New Source dialog box select Schematic from the list. Name the file as

MyFullAdder in the File Name field. Verify that the Add to project check box is

selected.


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4.2.7. Click Next. Then click Finish!

This will launch Engineering Capture System (ECS). You may have to choose the tab

labeled MyFullAdder and close other windows in the left side (don’t close the Sources


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window). A blank sheet opens in an ECS schematic window. In ECS, you can create a

schematic diagram from scratch.


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4.3. Creating a Schematic

On the left side of the screen you will see two small windows – “Categories” and “Filter”. This is

where we will find all the components we will need to assemble our full adder.

4.3.1. Select Logic in the Categories window. Only logic gates in the Symbols window will be

displayed. From the Filter window add an OR2 gate along with two AND2 gates onto your

workspace. Also grab two XOR2 gates.


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4.3.2. Click on the Add Wire icon . This will allow you to connect the components together.

Click on the lead of one gate then on the lead of the next and a wire will be drawn that

connects the two together. Note that

S = A B C

Cout = (A B) C + A·B

Note the use of the following symbols:

⊕ used to denote XOR, eg. A ⊕ B means A XOR B

+ used to denote OR , eg. A +

B means A OR B

· used to denote AND, eg. A·B means A AND B

After the wires have been connected your circuit should look as follows. Make sure to add

wires to outputs S and Cout.

Now we need to add I/O Markers. These markers will help Xilinx determine where the

inputs/outputs are when it converts this schematic into a macro.


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4.3.3.

Click the I/O Marker icon . Place markers on each input and output by clicking on the

terminal that you wish to place the marker.

Your schematic should look like this with the markers in place. Xilinx automatically assigns names

to the markers, but remembering the names can get confusing really fast. For clarity, change the

names. Right click on the marker and rename. Alternatively, you can select the pointer tool and

double click on the marker you wish to rename. In the Object properties dialog box change the

name of the marker by changing the name in the Value field. Click “Ok”. Similarly rename all

your markers. When you are done the schematic will appear as follow.


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4.4. Creating a Macro

Now that our schematic is complete we would like to create a macro. A macro is a user-created

symbol that can be used just like a component. The advantage of creating a macro is that once you

have a macro for your full adder you can use the same macro over and over again. First, save your

schematic. Then from the tool bar select “Tools”, then “Symbol Wizard”. Finally select “Specify

Manually”.

Click Next!


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A dialog box with the input and output ports of the schematic open up. Click ‘ Add Pin’ in order to

add pin to macro. Check whether the input and output ports are defined as you intended.

Click Next!

In this dialog box you can change some appearance properties of the symbol being created.

Click Next!

You can see your symbol in a “symbol wizard” dialog box. Click Finish!


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Now there is a shortcut for creating macros!!!

4.4.1. Click/highlight any of the VHDL or schematic files in the “source window” so that you see

the corresponding “process window”.

4.4.2. In the process window double click on “Create Schematic Symbol” (refer to screen-shot

below). This creates the schematic symbol corresponding to the VHDL code created and

adds it to the library so you can use it in your designs. “Create Schematic Symbol”

creates macros using default settings. You can use it instead of using the ‘symbol editor’.

4.4.3. Now close the Symbol editor. Close the schematic we had just been working on, and return

to the project navigator.


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4.4.4.

Now we will create a new Schematic. Right click on the Device (xc3s400-5 ft 256), then

select New Source…

4.4.5. Select Schematic from the list and name it “My_4bit_Adder_Chip”. Next click “Finish”

This will reopen the schematic editor.


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4.4.6.

Now select the symbols tab and look in the ‘Categories Window’. You will realize that a

new category named has been added. In this category the full

adder created previously can be found.

You have just completed creating your first macro!


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4.5. Mini-Exercise

Use the new schematic previously created named “My_4bit_Adder_Chip” and the full-

adder macro created previously to create a 4-bit adder. You can select copies of this adder fromthe new category created and connect them together as shown in the diagram below. The

resulting macro must look like the 4-bit adder macro shown in the next diagram.


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4.6. Obtaining the RTL Schematic for the system

Obtain the RTL Schematic for ‘My_4bit_Adder_Chip’ by double clicking on the ‘View RTL

Schematic’ section of the Process View window as shown in the diagram below. The RTL

Schematic allows the user to view he internal architecture of the macro created. You will notice

the RTL Schematic resembles the schematic you implemented.


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4.7. Simulation of the design using Modelsim 6.0SE/XE

If Modelsim 6.0SE/XE is not already linked to the Xilinx 7.1ISE softare then you need to do so

before progressing in this lab, using the reading resource named “Linking Modelsim 6.0SE/XE

to Xilinx 6.3i/7.1i”. This document can be downloaded from the course Website on

MyElearning.

In the New Source dialog box select “Test Bench Waveform” from the list. Name the file as

“My_4bit_Adder_tb”in the File Name field. Verify that the “Add to project” check box is

selected.

Click Next!


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Attach the test bench waveform file to the top level schematic module ‘My_4bit_Adder_Chip’

and click Next! Then click Finish!

Set the test bench waveform with the following test cases as shown in the table below.

A3 A2 A1 A0 B3 B2 B1 B0 Cin

0

0

0

1

0

1

0

0

1

0

0

0

1

0

1

0

0

0

0

1

0

0

0

0

0

1

0

0

1

0

0

0

0

0

1

0

Table 1: Test cases for simulation

Now save the design.

N.B.: In this lab you will be introduced to two kinds of simulation, functional and timing

simulation. This will be introduced in section 4.8 of the lab.


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4.8. Simulation Theory

Functional Simulation

A functional simulation is done to verify the operation of the circuit. We use it to ensure that the

circuit’s functional behavior correct. If we want to perform a functional simulation we just

double click on “Simulate Behavioral Model” in the Xilinx 6.3i/7.1i process window.

Timing Simulation

The timing simulation will give you detailed information about the time it takes for a signal to pass from one gate to the other (gate delay) and gives information on the circuit worst-case

conditions. The total delay of a complete circuit will depend on the number of gates the signal

sees and on the way the gates have been placed in the FPGA or CPLD. Thus timing information

can only be obtained after the design has been implemented. If we want to perform a timing

simulation we just double click on “Simulate Post-Place & Route VHDL Model” in the Xilinx

6.3i/7.1i process window.


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4.9. Practical: Simulation using Modelsim

Highlight the test bench waveform in the Module View window, then double click ‘Simulate

Behavioral Model’ from the process window. The Modelsim 6.0SE/XE GUI loads

automatically.

Verify that the system is functional by thoroughly analyzing the timing diagram generated.

Repeat the simulation using ‘Simulate Post-Place and Route VHDL Model’.


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4.10. Programming the FPGA development board

The first step to programming the FPGA development board is to create the implementation

constraints file. This is done by selecting “Implementation Constraints File” from the “New

Source” dialog window. The file must then be given the name “My_4bit_Adder_ucf”. We then

click Next.

Ensure that the implementation constraint file created is connected to the top level schematic

‘My_4bit_Adder_Chip’ as shown in diagram below. Then click Next. Then click Finish.


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We then double click the Implementation Constraints File from the Module View and then

assign package pins using the table below.

Before you create the Implementation constraints file students are advised to utilize the

datasheet of the Spartan 3 Toolkit (SBOARD.pdf) to locate the switches, pushbuttons and

LEDs to be used in this laboratory exercise. If you are having problems doing this please call

the attention of a TA.


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Table 2: Pin assignments for the Implementation

Design Port FPGA Pin AssignedA3 K13 (FPGA switch)

A2 K14 (FPGA switch)

A1 J13 (FPGA switch) A0 J14 (FPGA switch)

B3 H13 (FPGA switch)

B2 H14 (FPGA switch)

B1 G12 (FPGA switch)

B0 F12 (FPGA switch)

Cin M13 (FPGA Pushbutton)

S3 N14 (FPGA LED)

S2 L12 (FPGA LED)

S1 P14 (FPGA LED)

S0 K12 (FPGA LED)

Cout P11 (FPGA LED)

After assigning package pins, save the changes made and double click ‘Configure Device

iMPACT’ under the Generate Programming File tab from the Process Window as shown in the

diagram below.


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Click Next!

Click Finish!


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Click OK!

Click Open!

You are now prompted for a PROM programming file as shown in the figure below. We are not

programming the PROM at this time, therefore select Bypass.


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5. POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date: N/A

Submission

Procedure:

N/A

Deliverables: N/A

End of DIGLAB1: Introduction to the Xilinx Schematic Editor

diglab1 - introduction to xilinx schematic editor aug 28

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