diglab4 - time multiplexing of displays aug 28

8/18/2019 DIGLAB4 - Time Multiplexing of Displays Aug 28

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THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

1

ECNG 2004

LABORATORY & PROJECT DESIGN IIhttp://myelearning.sta.uwi.edu/course/view.php?id=1678

Semester I, 2009/2010

1. GENERAL INFORMATION

Lab #: DIGLAB4

Name of the Lab: Time Multiplexing of Displays

Lab Weighting: 10 % [TOTAL = 71MARKS]

Estimated total

study hours1:

10

Delivery mode: Lecture

Online

Lab Other

Venue for the Lab: Electronics Laboratory

Lab Dependencies2 The theoretical background to this lab is provided in ECNG 1014

Theoretical content link: http://myelearning.sta.uwi.edu/

Pre-Requisites – None

Recommendedprior knowledge

and skills3:

Use Xilinx Schematic Editor to implement simple digital circuitsLaboratory exercises DIGLAB1 - DIGLAB3

Course Staff Position/Role E-mail

Phone

Office Office

Hours

Marcus L George Instructor [email protected] ext3164 ElectronicsLab Office

Fridays

10am - 1pm


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THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING

Department of Electrical & Computer Engineering

2

2. LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to: Cognitive

Level

1. Understand the concept of time multiplexing when applied to seven-

segment displays

C

2. Apply Karnaugh maps to the design of BCD to seven-segment convertersand look-up-tables

Ap

3. Implement BCD to seven-segment converters and look-up-tables using

Xilinx Schematic Editor

Ap

4. Implement a time-multiplexing display by integrating appropriate macros Ap

5.

Analyze the concept of time multiplexing of displays at various frequenciesusing the implemented system

An


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DIGLAB4: Time Multiplexing of Displays

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3. PRE-LAB

3.1.

Required Reading Resources

Digital Design Principles and Practices, by John F. Wakerly

3.2. Reading Exercise

Using suitable reading resources (ECNG1014 notes, recommended books, internet, etc), research

and understand the following topics.

• Time Multiplexing of Displays

• BCD to 7-segment Converter

• Look-up-Table (LUT)

Read and understand pages 47-51 of the datasheet for the Spartan 3 FPGA development

board(S3BOARD.pdf ). This is a reading exercise that students must do in preparation for the in-

lab session. Bring printed copies of the lab4 manual and of pages 47-51 of the datasheet to thelab for the in-lab exercise.

Due Date: The deadline for submission of the pre-lab for this laboratory exercise is

as follows:

All Groups: Monday 5th

October 2009 at 12 noon

Feedback onPre-Lab

Feedback for this pre-lab exercise will be given by Mr. Marcus George

on Thursday 8th

October 2009 in Room 5.1. Students’ pre-lab marks

will be made available.

Submission

Procedure:

Submit reports to the designated graduate assistant in the Electronics

laboratory. Students must also fill out a report submission receipt and

have it signed or stamped by the graduate assistant.Estimated time to

completion:

3 hours


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3.3.

BCD-to-7 Segment Decoder

Design a BCD to seven-segment decoder to create the numeric digit display patterns shown in

Figure 1.

Figure 1: Pin diagram of BCD-to-7segment decoder

The display element is of the common anode variety. The decoder receives its BCD input on 4

lines D3D2D1D0, D3 being the MSB.

The BCD to 7-segment decoder will be designed to match the requirements of the Spartan 3

FPGA development board. Segments will be switched on only when a LOW signal is specified.


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Figure 2: Cathode pattern for decimal digits

(a)

Complete the following truth table of the BCD to 7-segment decoder. [3 marks]

Inputs Outputs

D3 D2 D1 D0 Seg_a Seg_b Seg_c Seg_d Seg_e Seg_f Seg_g

0 0 0 0 0 0 0 0 0 0 1

Binary code of any number > 9

(Display OFF) 1 1 1 1 1 1 1

(b) Using Karnaugh Maps, find the minimum expressions of all the outputs. Show all working.

[14 marks]

(c) Draw the logic circuit implementation for all outputs. Each logic circuit should be

individually shown. [8 marks]

(d) Implement the BCD-to-7 segment converter using the Xilinx Schematic Editor. [1 marks]

(e) Perform functional and timing simulation on the complete BCD-to-7 segment converter. [2

marks]


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3.4.

Display LUT

The table below gives the truth table for the LUT used in the display unit of figure 5 below.

Input(I)

I1I0

Output(O)

O3O2O1O0

0 0

0 1

1 0

1 1

1 1 1 0

1 1 0 1

1 0 1 1

0 1 1 1

Using this truth table:

(a) Karnaugh Maps, to find the minimum expressions of all the outputs

O0 to O3. [8 marks]

(b) Draw the logic circuit implementation for all outputs. [5 marks]

(c) Implement the LUT using the Xilinx Schematic Editor. [1 marks]

(d) Perform functional and timing simulation on the complete LUT. [2 marks]

NB: Students are advised to utilize buses and bus taps in your implementation of modules of

sections 3.3 and 3.4 of the pre-lab.


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4. IN-LAB

Allotted Completion

Time:

3 hours

Required lab

Equipment:

1 printed copy of the DIGLAB4 manual (students must bring it to the

lab)

1 Computer

Spartan 3 Development board toolkit(including J-Tag cable & adaptor)

Small breadboard

40-pin ribbon connector cable

Connecting Wires

1 Pliers/Wire Cutter/Wire Nippers(students must bring to the lab)

Students must bring the following modules with them to the lab:

3×16bits Multiplexer(designed and implemented in DIGLAB2)

4×4bits Multiplexer(designed and implemented in DIGLAB2)

1kHz Frequency divider(designed and implemented in DIGLAB3)

BCD-to-7 Segment converter(designed and implemented in pre-lab of

DIGLAB4)

Display LUT(designed and implemented in pre-lab of lab4)

4.1. In-Lab Procedure

In this laboratory exercise data is displayed using Time Multiplexing of displays. The display

unit can receive data from three 16-bit data sources which are connected to 3-to-1 16-bit

multiplexer with a 2-bit ‘select’ port. The selected 16 bits are broken into four parts and are

connected to a 4-to-1 4-bit multiplexer. In time multiplexing of displays each digit is displayed,

but not at the same time. They are displayed in a sequence, starting with the least significant

digit and ending with the most significant, before starting the entire process over again from the

least significant. Figure 3 shows the display of the number 2369 using time multiplexing while

figure 8 gives a generic timing diagram to illustrate time multiplexing.


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Figure 3: Time Multiplexing of Displays

Figure 4: Seg signal timing

In order to achieve time multiplexing of the displays we need to select which digit needs to be

displayed before we display it. Now the switching rate for the displays is achieved by a 1kHz


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clock signal. Therefore a modulo 4 counter is used to count from 0 to 3. The value inside the

counter is assigned to the ‘dataout’ port of the counter. This is then inputted in a look-up-

table(LUT) which takes the counter’s value and looks up the 4-bit value that must be used to

select data to be displayed. This must also be connected to the 4 anode pins on the FPGA

development boards.

The value from the modulo 4 counter is used to select one of 4-bit inputs connected to the input

of the 4-to-1 4-bit multiplexer. The selected value is converted from BCD to 7-segment format

using a BCD to 7-segment converter. The BCD to 7-segment converter can be designed and

implemented using the same method used to design and implement the LUT mentioned above.

Figure 2 above gives the cathode pattern for decimal digits to be displayed. This table should

have been used when designing and implementing the BCD to 7-segment converter.

The 7-bit value obtained from the BCD to 7-segment converter is sent to the 1 to 4 7-bit

demultiplexor which assigns it to one of the four output ports depending on the value on the

‘select’ port of the demultiplexer, which in essence causes the display of data on the 7-segment

displays. Figure 5 below gives the data-path block diagram for the display unit.


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Figure 5: Datapath block diagram of the Display Unit

4.1.1.

Using work done in the pre-lab and in-labs for DIGLAB2 and DIGLAB3,

implement the display unit shown in figure 5 above.

4.1.2.

Synthesize and implement the design.

4.1.3.

Perform functional and timing simulation on the display unit.

4.1.4.

Create a macro for the display unit as shown in figure 6 below. You can use

the shortcut for creating macros.


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Figure 6: The Black-box diagram of the Display Unit

4.1.5.

Create a new schematic source.

4.1.6. Supply the display unit with a 1kHz clock signal by connecting a 1kHz

frequency divider to the unit as shown in figure 7 below. (The frequency

divider takes the reference clock and produces a 1kHz clock signal for the

display unit).

4.1.7. Synthesize and implement the design.

4.1.8.

Create a macro for the system. Again you can use the shortcut for this

purpose.


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Figure 7: Datapath block diagram of the completed display system for lab 4

4.1.9.

Create an implementation constraints file for the design using the data shown

in table 2 below. Also use the datasheet for the Spartan 3 FPGA

development board(S3BOARD.pdf) to connect display_value_1,

display_value_2 and display_value_3 to pins of the FPGA development

board. You will need 48 available pins. You can use any available pin of the

FPGA development board.


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4.1.10.

Now double-click on “Edit Constraints(Text)” as demonstrated below:

4.1.11. Now edit the net list such that all pins that must be logic HIGH are fixed to

logic HIGH. This is done by adding “| PULLUP” just before the semi-colon

as demonstrated on line 4 of the text file of the figure below.

eg. NET "TEST_PIN0" LOC = "C3" | PULLUP;

Now edit the net list such that all pins that must be logic HIGH are fixed to

logic

HIGH. This is done by adding “| PULLDOWN” just before the semi-colon.

This is

demonstrated in line 5 of the text file of the figure below:

eg. NET "TEST_PIN1" LOC = "C4" | PULLDOWN;


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4.1.12.

Have your circuit checked by your instructor/teaching assistant before

powering up.

4.1.13.

Download the design onto the Spartan 3 FPGA development board and

perform on-board testing. Test your display unit using table 1 below. Record

all results.

4.1.14.

Demonstrate the functional system to your instructor/teaching assistant.

NB: It must be noted that the same “48-bit data format (3×16bits)” value is utilized

for all four test cases of table 1 below. We only vary the “select” port.

It must be noted that port A of the 3×16bits multiplexer is the least significant 16 bits

while port C of the 3×16bits multiplexer is the most significant 16-bits.


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Table 1: Test Cases to be used for the in-lab exercise

Test # 48-bit data format(3×16bits) select Value displayed

1 1001100110011001 1000011101100101 0100001100100001 00

2 1001100110011001 1000011101100101 0100001100100001 01

3 1001100110011001 1000011101100101 0100001100100001 10

4 1001100110011001 1000011101100101 0100001100100001 11

Table 2: Pin Configuration for the Display Unit

Design Port FPGA Pin to be mapped toclk T9

reset M13(FPGA pushbutton)select(0) K13(FPGA switch)

select(1) K14(FPGA switch)

anode(0) D14

anode(1) G14

anode(2) F14

anode(3) E13

seg(0) E14

seg(1) G13

seg(2) N15

seg(3) P15

seg(4) R16seg(5) F13

seg(6) N16

Proceed to post-lab exercise.


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5. POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date: The deadline for submission of report for this laboratory exercise is as

follows:

All Groups: Monday 26th

October 2009 at 12 noon

Feedback on Lab Feedback for this laboratory exercise will be given by Mr. Marcus

George on Friday 30th

October 2009 in the Electronics Laboratory

during office hours. Students’ lab marks will be made available.

Submission

Procedure:

Submit reports to designated graduate assistant in the Electronics

laboratory. Students must also fill out a report submission receipt and

have it signed or stamped by the graduate assistant.

Deliverables: Submit an informal report consisting of the responses to the post-lab

exercises in addition to a lab discussion and conclusion.

[1] Discussion of the lab should include: [3 mark]

a.

Relate design to the results obtained.

b. If design was successful then explain why it works. If not

successful then explain why design did not work along with and

possible solutions.c.

Include and explain all observations made.

d. Design decisions made and justification for decisions made.

e.

Problems faced and how were they dealt with.

[2] Conclusion of the lab should include: [1 mark]

State briefly, but clearly, what you have gained from this laboratory.

Outline aspects that you have noted within the experiment outside of the

questions asked. Make comments on the procedure of the lab - Is there

anything that you could have done differently? How did you split thework between group members? Did you have a plan of action? What else

would you suggest that should be added to this lab session?


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5.1. Assignment:

5.1.1. Fill out Table 1 above and submit a copy of the completed table in your

report. [4 marks]

5.1.2.

Supply the display unit with the following clock signals:

a. 50MHz

b. 1Hz

Download the design onto the Spartan III FPGA development board and

explain all observations made. [4 marks]

5.1.3.

Explain the process of ‘time multiplexing of displays’. [2 marks]

5.1.4.

Give two advantages of time multiplexing of displays. [2 marks]

5.1.5.

Can we use NPN transistors instead of the PNP transistors for the seven-

segment display? If yes, what would be the initial value of the anode vector?

[2 marks]

5.1.6.

Estimate the power saving using this method compared to the non-

multiplexed method. Assume that all 4 displays are to be utilized. [4 marks]

5.1.7.

Is it a good engineering practice to leave pins of the FPGA development

board open instead of connecting them to ground (GND)? Explain your

answer. [3 marks]

5.1.8.

Submit a copy of the implementation constraints file for the complete

system, clearly showing the pins each port is connected to. [2 marks]

End of DIGLAB4: Time Multiplexing of Displays

diglab4 - time multiplexing of displays aug 28

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