direct analysis and synthesis of multiphase switched-current networks using signal-flow graphs

*Correspondence to: Dr M. H. Helfenstein, ETH Zurich, Institute for Signal and Information Processing, ETF D 102, ETH-Zentrum,CH-8092 Zurich, Switzerland. Email: [email protected] with GlobeSpan Technologies Inc., Middletown, NJ 07748, USA.Contract grant sponsor: KWF Jessi-Project; contract grant number: 2302.1 Eureka EU 127

CCC 0098—9886/98/030253—28$17.50 Received 3 January 1997( 1998 John Wiley & Sons, Ltd. Revised 12 September 1997

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. ¹heor. Appl., 26, 253—280 (1998)

DIRECT ANALYSIS AND SYNTHESIS OF MULTIPHASESWITCHED-CURRENT NETWORKS USING SIGNAL-FLOW

GRAPHS

MARKUS HELFENSTEIN*, ARNOLD MURALT, GEORGE S. MOSCHYTZs

ETH Zurich, Institute for Signal and Information Processing, ETF D 102, ETH-Zentrum, CH-8092 Zurich, Switzerland

SUMMARY

A by-inspection analysis and synthesis method for multiphase switched-current (SI) circuits using signal-flow graph(SFG) techniques is presented. The SFG is derived on the transistor level and the method is primarily useful for the handanalysis and design of small and medium-size SI circuits (e.g. SI filters, decimators, interpolators). Tables of commonlyused SI circuits, in which the corresponding SFGs and circuits are given, make the derivation easy and fast. From theSFGs, not only the overall discrete-time transfer function, but also those in-between individual switching phases, areobtainable. With the proposed method it is straightforward to include non-ideal effects, such as finite output resistance ofMOS transistors, clock-feedthrough and settling error. The method is also a useful tool for the synthesis of new SIcircuits. It is shown that every low-sensitivity switched-capacitor (SC) circuit can be mapped directly into a low-sensitivity SI circuit with a corresponding topology. Examples of transformed SC circuits are given and two new doublesampling integrators are introduced. ( 1998 John Wiley & Sons, Ltd.

KEY WORDS: switched-current filters; signal-flow graph techniques; nonidealities in SI; multirate techniques

1. INTRODUCTION

As already shown for switched-capacitor (SC) networks, SFG techniques have proven to be very useful forthe hand analysis of small and medium-size networks.1—3 Such techniques were further developed in Reference4, where a direct, by-inspection method of transforming a given SC network into the corresponding SFG wasdeveloped.

In the switched-current area, not much work on the analysis of circuits on the transistor level has yet beenpresented. In Reference 5, the focus is on the building block level (e.g., integrators) and in Reference 6 thenodal analysis of SI circuits for computer implementation is discussed. For switched-current circuit synthesis,Roberts et al. (Reference 7, Chapter 9) suggested a systematic approach using SFGs on the building blocklevel, and Hughes et al. (Reference 7, Chapter 3) replaced integrators in a voltage-based SFG with SI buildingblocks having the same transfer function.

In this paper, a SFG analysis and synthesis method is described which is applicable to general SI networks.The method operates on the transistor level and can readily be applied to N-phase circuits. The analysis isbased on the small-signal representation of a circuit, and thus, all relations are linear. It can serve asa practical tool both for hand analysis and, more importantly, for the synthesis of SI networks. In the firstcase, the appropriate discrete-time transfer functions can by calculated, e.g., using Masons’s rule, and it ispossible to include non-ideal behaviour, such as mismatch and finite output resistance of the MOS transistor,clock-feedthrough and settling error in the calculations. In the synthesis case, a circuit can be obtained from

Figure 1. Symmetrical N-phase clock

the corresponding switched-capacitor SFG by combining tabulated small-signal representations of com-monly used building blocks of transposed SC graphs. Since the approach is applicable on the transistor level,it is supplementary to the publications referred to above.

The method is particularly useful for the analysis of most general SI networks, so long as their complexityis limited and a hand calculation of the transfer function in closed form is desirable. However, for circuits ofhigher complexity, computer analysis methods for the derivation of transfer characteristics, such as ampli-tude and phase response or sensitivity analysis, are recommended.6,8,9

In Section 2, the paper first presents the analysis of multiphase SI networks on the SFG level. The inclusionof the linearized non-ideal behaviour of the circuit is considered in Section 3, where we show that such effectscan be included with simple modifications on the SFG level. Section 4 deals with the mapping of well-knownSC circuits into their SI counterparts, and with general issues relevant to synthesis. Using the proposedmethods two new double-sampling integrators are derived.

2. ANALYSIS OF SI NETWORKS

We consider multiphase SI networks driven by a symmetrical N-phase clock (Figure 1). All switches andsources in the network are assumed to be ideal. Furthermore, the network is assumed to contain two differenttypes of transistors, namely memory and scaling transistors. In a small-signal representation, memorytransistors are represented as voltage-controlled current sources with current sample-and-hold character-istics. The small-signal gate-source voltage of each memory transistor will be represented by N nodes in theSFG, one node for each switching phase. Scaling transistors are used to provide current outputs or currentfeedback. In a small-signal representation scaling transistors are represented by voltage-controlled currentsources. The current delivered by each of these sources will be represented by N nodes in the SFG, one nodefor each switching phase.

We restrict our considerations to networks containing only three types of nodes (except for the referencenode):

(i) nodes driven by ideal current or voltage sources, the source nodes;(ii) nodes collecting the source currents, the sink nodes;(iii) nodes representing the small-signal gate-source voltages of memory transistors, the memory nodes.

Note that the network topology of a SI network can change after each switching phase and therefore, thenodes can alter their node-type, e.g., from a source node to a sink node. This behaviour is different fromSC-type networks where the topology stays constant, and where a node retains its type throughout theoperation of the circuit (e.g. an op amp output always represents a source node). Figure 2 shows a compari-son between the block diagram of a SC and a SI network. In Figure 2, lowercase letters denoting small-signalvoltages and currents will be used whenever the linear behaviour of the circuit is under investigation. Totalsignal voltages and currents (bias and signal), represented by uppercase letters, will be used for analysing thenon-ideal behaviour of the circuit. As can be seen, the voltage input and output of the SC case change to

254 M. HELFENSTEIN, A. MURALT AND G. S. MOSCHYTZ

Int. J. Circ. ¹heor. Appl., 26, 253—280 (1998)( 1998 John Wiley & Sons, Ltd.

Figure 3. Second-generation bi-phase SI memory cell (type I): (a) its small-signal representation for both phases (b) and SFG (c)

Figure 2. Voltage domain, SC processor (upper diagram), current domain, SI processor (lower diagram)

current interfaces in the SI case, and the charge processor is replaced by a voltage processor. In SI networks,only small-signal currents produce linear nodal voltages, making it convenient to represent the small-signalcurrent by the small-signal gate-voltage of the appropriate memory transistor. The small-signal and SFGrepresentation of the basic SI memory cells are shown in Figures 3 and 4 (type I and type II). During thesampling phase /

1, a small-signal voltage v(1)

1is developed by the input current i (1)

*/over the transconductance

gm*/

in the type I case and gm1

in the type II case and held by the parasitic capacitances Cgs1

of the memorytransistors M

1. During the next switching phase, /

2, the output current i (2)

065is controlled by the sampled-

and-held voltage v(2)1

. During the sampling phase, the nodes v(1)*/

(type I) and v(1)1

(type II) act as sink nodes, andduring the hold phase the nodes v(2)

1(type I, II) act as source nodes.

ANALYSIS OF MULTIPHASE SI CIRCUITS USING SFG TECHNIQUES 255

( 1998 John Wiley & Sons, Ltd. Int. J. Circ. ¹heor. Appl., 26, 253—280 (1998)

Figure 4. Second-generation bi-phase SI memory cell (type II): (a) its small-signal representation for both phases (b) and SFG (c)

In what follows, we use the following conventions to denote sample sequences and their z-transforms.Sample sequences are denoted by lower-case letters, e.g., i

065(n). The samples are taken at intervals of q.

A superscript index is used to denote sequences containing samples taken every Nth phase interval, i.e., everyNq seconds, e.g. i(j)

065(n) is the sample of the sequence i

065(n) taken at the jth phase. The samples are taken at

intervals of Nq. All z-transformed signals are denoted by upper-case letters, e.g., I065

(z) and I(j)065

(z). Thez-transform of a sample sequence can be expressed in terms of its phase components, e.g.,I065

(z)"+Nj/1

I(j)065

(z). Furthermore, we define the overall transfer function H(z) as H(z)¢I065

(z)/I*/(z), where

I065

(z) and I*/(z) are the z-transforms of the samples at the output and input.

The following observations which hold for a general SI network can now be made.

(i) The SFG will contain only source and sink nodes; these correspond to the source and sink nodes ofthe SI network.

(ii) The type of a node can change from one clock phase to the next.(iii) At most N nodes (one for each of the N clock phases) will be needed to represent the small-signal gate

voltage of each memory transistor.(iv) At most N nodes (one for each of the N clock phases) will be needed to represent each input and each

output current.

We distinguish between three distinct switching situations: the charge phase n, the voltage-copy phasem and the discharge phase t. The corresponding small signal circuits and their SFG representations are given



Table I. Correspondences between particular switching situations and the SFG

in Table I. All memory transistors produce voltage nodes, cases (a) and (c). Current nodes appear only at theinput and output interfaces, cases (b) and (d). No SFG branch is used for the discharge phase, cases (e) and (f).

The following observations are direct consequences of the above.

(i) Charge phase: A current value is ‘stored’ on the gate-source capacitor of a memory transistor in the nthphase if the gate of the FET is connected to a diode-connected FET (type I) or if the FET is connected toa source node (type II).



Figure 5. Second-generation damped integrator

(ii) Scaled voltage-copy phase: The ‘stored’ current is transferred to a sink node during the mth phase if atleast one output-switch is connected to a sink node, and the gate still holds the stored voltage.

(iii) Discharge phase: The ‘stored’ current goes to zero during each phase t if the gate of the memorytransistor is grounded, or if the output is connected to the input after a storage phase.

(iv) In order for a memory FET to influence the surrounding network, it must be connected at least once asa sink and once as a source.

(v) A current ‘stored’ in the nth phase can only be transferred in the mth phase if there is no discharge phaset between phases n and m.

The procedure for the SFG derivation of an N-phase SI network and the calculation of its transfer functioncan be summarized as follows:

(i) Identify and number all memory transistors, input current sources, and output scaling transistors.(ii) Draw the small-signal circuit for every phase considering only memory and scaling transistors. The

small-signal equivalent circuit of each transistor consists of a voltage-controlled current source.(iii) For each memory transistor and scaling transistor find the corresponding SFG representations from

Table 1.(iv) Calculate the desired discrete-time transfer functions.10

With some practice, step (ii) may by omitted and the SFG can be obtained directly by inspection. Thefollowing examples illustrate the procedure.

2.1. Examples

We shall now provide three illustrative examples to demonstrate our by-inspection procedure for derivingthe SFG of a given SI circuit.

Example 1Consider the simple 2-phase second-generation damped discrete-time integrator in Figure 5.7By applying the procedure above, the memory transistors M

1and M

2and the scaling transistors Ma and

MA

can readily be identified (step i). For every clock phase, the small-signal circuit of each memory andscaling transistor has to be drawn (step ii). Using Table I, the corresponding SFG representation (Figure 6) is



Figure 6. Small-signal circuits for second-generation damped integrator for phase /1and /

2, (a) and (b), respectively, the corresponding

SFG (c) and the simplified SFG (d)



sNote that our analysis is based on a switching frequency defined by f#"1/2q where z~1 corresponds to the delay q, whereas the

literature cited defines f#"1/¹ where ¹"2q. This explains why the degree of our polynomials is twice the degree given in the references.

Figure 7. Double sampling bilinear integrator/summer after11

readily obtained (step iii). Using Mason’s rule, the discrete-time transfer functions with the input sampled atphase /

1can be obtained (equation (1), step iv). Both equations represent a damped discrete-time integrator,

the second with an output delay of half a sampling period. Furthermore, H12"H22"0. Notice that theSFG analysis permits the calculation of the transfer functions between any phase at the input and any phaseat the output.s (We shall show in Example 2 when it is possible to calculate the overall transfer function.)

H11(z)"I(1)065

I(1)*/

"

!A

1#a!z(1)

H21(z)"I(2)065

I(1)*/

"

!Az~1

1#a!z~2

Example 2Consider next the two-phase SI double-sampling integrator/summer (Figure 7) proposed by Hughes

et al.11 The usual way of calculating the transfer function for this type of circuit is to set up a number ofdifference equations using Kirchhoff ’s current law, and solving for a desired output variable. No insight intoindividual transfer functions, say between phases 1 and 2, is thereby obtained. Using the proposed SFGtechnique, every path corresponding to every possible set of switching phases is available. For convenience,Figure 8 shows the small-signal representation and the SFG of the circuit. Notice that the SFG issymmetrical with respect to phases 1 and 2, in the sense that we obtain exactly the same SFG when weinterchange the phases.

In general, an N-phase network can be described by equation (2), where the Hij are the transfer functionsbetween the outputs in phase i and the inputs in phase j. The overall transfer function I

065/I

*/can be obtained

as the column sum of [H], if all column sums of [H] are equal. [H] is Toeplitz for general N-phase circuitsand symmetrical for two-phase circuits.



Figure 8. Small signal representation for the double-sampling bilinear integrator/summer for both phases (a) and (b), respectively, andthe corresponding SFG (c)

I (1)065

F

I (N)065

"

H11 2 H1N

F 2 F

HN1 2 HNN

I (1)*/

F

I (N)*/

(2)

From the SFG in Figure 8c the transfer functions for Ib/I

*/can be calculated as H11

b"H22

b"!b. Thus, the

column sum of [H"] is !b. For the input—output relations I

0/I

*/, equation (3) holds, and the sum of the two



Table II. Commonly used SI integrators and their SFGs

Figure 9. Direct-form SI implementation of a simple polyphase structure for decimation12



Figure 10. Small-signal circuit for SI decimator /0

in (a), /1

in (b), and /2

in (c)

terms corresponds to a bilinear integrator at twice the sampling rate, i.e., equation (4).

H120

(z)"H210"

!2az~1

1!z~2(3)

H110

(z)"H220"!a

1#z~2

1#z~2

H0(z)"!a

1#z~1

1!z~1(4)

The SFG of commonly used SI integrators can be derived with the method under consideration. These aresummarized in Table II with their transfer functions for the corresponding paths. The SFG of all types ofintegrators consists of two S/H’s in a feedback configuration. The output of the loop has to be chosendepending on the desired integration type. Thus, output and input are common for backward differenceintegration (Table II, circuit 1, bd), one additional delay is needed in the loop for lossless discrete integration



Figure 11. SFG for SI decimator

(ldi), and two for forward difference integration (fd). Circuit 2 shows the implementation of the bilinearintegrator (bi). As pointed out in Referece 11, circuit 2 doubles the speed of the integrator if samples are takenduring both phases.

The method can be applied to general multiphase SI circuits such as the polyphase structures proposed inReference 12. The transfer function can be obtained by computing the transfer functions from all inputs to theoutput at one phase. In the following example, a direct-form SI implementation of a simple polyphasestructure for a decimator is given.

Example 3The circuit of a decimator with an input/output sampling ratio of 3 is given in Figure 9.12 Since the circuit

has 3 clock intervals, the small-signal representation has to be drawn for all phases and each memory nodemust be represented by 3 nodes in the SFG. Using the rules given in Table I, it is straightforward to map thederived small-signal representation (Figure 10) into the corresponding SFG (Figure 11). The prototype filtercan now be identified as

H(z)"h0#h

1z~1#h

2z~2 (5)

and the input-to-output relation as

I(0)065

"h0I (0)*/#h

1z~1I(1)

*/#h

2z~2I(2)

*/. (6)

The same procedure can be applied to circuits with larger oversampling ratios.13In the following section, we will derive SFG branches to include non-ideal behaviour of MOS transistors

in switched-current SFGs.

3. NON-IDEAL BEHAVIOUR USING SFGs

The treatment of non-ideal behaviour in SI circuits has already been discussed in detail in Reference7 (Chapters 4 and 5). However, using difference equations for medium scale networks makes calculationssomewhat tedious and prone to errors. Therefore, a more systematic approach is desirable. Starting from the



Figure 12. SFG for the integrator including mismatch of transistors M1, M

2and M

2, M

A

results derived in Reference 7, we will deduce a table to easily include non-ideal operation of the MOStransistor in the SFG.

3.1. Mismatch of MOS transistors

Since the small-signal representation of the circuit includes the transconductance value gm, mismatch of

MOS transistors due to process variations can be included in the SFG representation in a straightforwardway. By knowing the variance of the geometrical parameters of the transconductance value, the variance ofthe transfer function can be calculated. Since mismatch is a linear operation, frequency-domain, z-transformand SFG analysis can be applied.

The procedure is to replace the gLmi

of the appropriate transistor i with gmi

(1#*i), where *

idenotes the

mismatch between the nominal transistor’s transconductance value, i. e., gmi

, and the actual value gLmi

. Ina current mirror configuration, *

ican be replaced by the variance of the current ratio mismatch p2(I)/I2 to

calculate the influences of mismatch.14,15Consider the integrator example discussed in Section 2 with mismatch *

1in the sample-and-hold (S/H)

transistor M1

and mismatch *A

in the scaling transistor MA. For simplicity, no damping of the integrator

loop is assumed. The transfer function of the SFG given in Figure 12 is obtained directly as

H11(z)"I(1)065

I (1)*/

"

!(gmA

/gm2

) (1#*A)

1!z~2"!

A(1#*A)

1!z~2(7)

and results in a gain error due to the mismatch of transistor M2

and MA, where A"g

mA/g

m2expresses the

gain of the circuit.

3.2. Finite output resistance of MOS transistors

To include the effect of finite output resistance of MOS transistors in the SFG representation, we cansimply apply the rules for the transconductance g

mito the output conductances g

0iof the transistor i. Thus,

every gmi

in the graph has to be replaced by the sum of gmi

and all g0’s connected to the appropriate node of

the small signal circuit during the corresponding clock phase. The SFG for the integrator discussed above,including input source conductance g

*/and finite output conductances of the transistors M

1and M

2, is

shown in Figure 13. The transfer function in equation (8) shows a magnitude error e"(g*/#g

1#g

2)/g

m2,



tThe SFG method is also applicable to the recently proposed S2I memory cell.17,18. For both cases it can be shown that clock-feedthrough cancels if CFT

#0!34%CFT

&*/%;1.

Figure 13. SFG for second generation damped integrator including finite source and MOS output resistance

which results from the transmission error due to the non-ideal input—output conductance error ratio of theMOS transistor.

H11(z)"I(1)065

I(1)*/

"!

gmA

gm2

#g*/#g

01#g

02

1!gm1

(gm2

#g*/#g

01#g

02)

gm2

(gm1

#g01#g

02)z~2

+

A(1!e)1!az~2

. (8)

There is also a small damping a of the integrator caused by the finite input of the driving input currentsource and the output resistance of the S/H transistors. Usually, this can be neglected, since g

i;g

mi.

3.3. Small-signal approach for charge injection in memory cells

In this paragraph, we include an average clock-feedthrough (Reference 7, pp. 115) to the SFG. Clock-feedthrough (CFT) occurs from the injection of carriers from the switch channel and from coupling of theclock through the overlap capacitances and results in a strongly non-linear behaviour of the basic sample-and-hold cell. As a first-order approximation, CFT is proportional to the switch area and indirectlyproportional to the gate-source area of the memory transistor.16,7 Some additional error is caused by theclock signal through the overlap capacitances of the switch. The average charge injection introduces an erroron the gate-source capacitance of the memory transistor which can be given as

»CFT*

"

[d(»H!»

'40!»

TS)¸

S*C

09#(»

H!»

L)¸

07SC

0x]¼

S*¼

Mi¸Mi

C09

(9)

In equation (9), »H

denotes the high clock amplitude applied to the switch, »'40

the gate-source voltage ofthe memory transistor M

Mifor zero input current, ¼

S¸

Sthe area, and »

TSthe threshold voltage of the switch

Si. A fraction d of the switch charge flows into the memory capacitance, depending on the load of each side of

the switch. To include the CFT error in the signal-flow graph, an error term CFTi"»

CFT*/»

imust be added

to every memory node i, which can be interpreted as the average clock-feedthrough, i.e., as the percentage »i

gets changed. The inclusion can be accomplished after a sampling phase by modifying every memory nodewith a self-loop containing the value CFT

i.t Consider the two sample-and-holds in series in Figure 14. The

example clearly shows how the CFT error can be included at the appropriate nodes. By calculating thetransfer function, it can be seen that there are always some residual errors (memory) from the first S/H



Figure 15. SFG for second generation integrator including clock-feedthrough effects

Figure 14. SFG for two S/H cells including clock-feedthrough effects

(transistor 1) to the second one (transistor 2). We show this for the integrator of Figure 15. Based on the SFG,the transfer function for equal CFT error on k

1and k

2results in

H11(z)"I(1)065

I(1)*/

"

!A

1#2CFT#CFT2!z~2(10)

where the CFT2 is a consequence of the two sample-and-holds in the feedback configuration. Note that thefact that CFT appears squared does not imply that we are analysing a non-linear effect. It is simplya consequence of the fact that we have two phases, and that clock-feedthrough occurs in both.

We can obtain the frequency response by putting z"e(+uT@2), resulting in

H11(e+uT)"!A

1#2CFT#CFT2!e~+uT(11)

For low-frequencies, e.g. u¹;1, equation (11) simplifies to

H11(e+uT)"!

A

1#2CFT#CFT2#ju¹

(12)

which is a first-order low-pass response with low-frequency gain A/(2CFT#CFT2) and a cut-off frequencygiven by u

~3$B"(2CFT#CFT2)/¹. It can be seen that a small CFT error results in a shift of the !3 dB

frequency to the left, which is close to the behaviour of an ideal integrator.



Figure 17. SFG for non-inverting integrator including settling error effects

Figure 16. SFG for two S/H cells including settling error effects

3.4. Settling error of memory cells

In the following, we assume that the memory cell is ideal except for its settling error e4. The behaviour of

the basic memory cell has been shown in detail.7 It is demonstrated that a settling error produces not onlyattenuation of input signals but also residual errors (memory) related to signals from earlier clock cycles. Forconvenience, equation (13) gives the input—output operation of a S/H with settling error. The correspondingSFG is given in Figure 16.

i065

(n)"e4i065

(n!2)!(1!e4)i*/(n!1) (13)

By inspection, the current transfer function is

H12(z)"!

(1!e4)z~1

1!e4z~2

(14)

Applying the same procedure to the non-inverting integrator, the signal-flow graph of Figure 17 is obtained.Thus,

H12(z)"(1!e

4)2z~2

1!(1#e24)z~2#e2

4z~4

"

z~2

(1!z~2)

(1!e4)2

(1!e24z~2)

(15)

which is the same as published in Reference 7, but derived directly by SFG analysis.For typical SI configurations, the results are summarized in Table III. Other effects can easily be included

by calculating the behaviour of the basic building blocks under small-signal conditions and adding thegraphs found in Table III.



Table III. Correspondence for the inclusion of non-ideal effects



Figure 18. Martin-and-Sedra’s biquad in SC technique: (a) circuit, (b) corresponding SC SFG

4. SYNTHESIS OF SI NETWORKS

It has previously been shown5 that rather than re-inventing new sampled-data current-based filter circuits,the voltage-based counterparts can be obtained by network transposition.19,20 In doing so, networks havingthe same topology, i.e. two dual voltage- and current-based networks, have identical component sensitivities.This allows us to directly apply design and optimization procedures from voltage-based to current-basedfilters. This approach yields simple circuits and provides more insight compared to other proposals, such asthe direct implementation of bilinear transformed voltage-based signal-flow graphs.21

As in the analysis section, we consider multiphase networks driven by symmetrical clocks. The synthesismethod is related to the work of Reference 5, but the SFG representation is closer to the transistor level of thecircuit. Therefore, implementation issues, such as long signal paths due to serial connection of S/H’s withinone clock cycle, can be detected readily and avoided. The proposed method is not restricted to filterapplications and can be applied to any SI circuit.

4.1. Mapping of a SC circuit into a SI circuit

The method is explained by illustrative examples.

Example 4We start with the general-purpose SC biquad shown in Figure 18,22, which provides any second-order

function, including finite zeros. The signal-flow graph can be derived directly using tabulated circuit-to-SFGtransformations.1 These graphs not only represent the complete functionality of the circuit, but also containthe exact topology of the SC circuit. The transposed SFG can be derived by interchanging excitation and



Figure 19. SFG for Martin-and-Sedra’s biquad in SI technique: (a) transposed SC SFG, (b) expanded SI SFG

response, changing the direction of the signal paths and replacing voltage nodes by current nodes, and viceversa. The resulting graph (Figure 19a) can be expanded by first replacing the integrators in the transposedgraph by the appropriate loops derived in Table II. The input and output of each current integrator can beidentified by the corresponding voltage nodes of the transposed graph. Since only voltage nodes are availablein the SI representation, every voltage node in Figure 19a having at least one output and one input branchwith integrating characteristics will be expanded in a corresponding integrator. Thus, in Figure 19a theintegrator output nodes » (2)

4correspond to » (1)

M2in Figure 19b and » (1)

2to » (1)

M4, respectively. The half-delay

from the first integrator has been shifted to branch k5

for reasons to be explained later. Second, the weightedinterconnections have to be made. k

1, for example, is part of the output current during /

1and corresponds to

a weighted voltage-copy phase (Table Id). The same procedure applies to the coefficients k4

and k5, however,

keeping Masons’s rule in mind, k5

must be augmented by two half-delays. The case of the unswitchedcoupling capacitor k

3has already been described by Roberts et al.7 (Chapter 9) and results in multiple output

integration paths. Since the value k3

appears as an outgoing path from » (1)M1

and » (1)M2

, two circuit elementswill be needed for its realization. This procedure is repeated for every single path i in the transposed graphcontaining the transfer function k

i(1!z~2). Therefore, the branches with k

2and k

6occur twice in the

expanded SFG representation. Based on the SFG, the transfer function results as

I(1)065

I(1)*/

"

k3z4#(k

1k5#k

2k5!2k

3)z2#(k

3!k

2k5)

z4#(k4k5#k

5k6!2)z2#(1!k

5k6)

. (16)



Figure 20. Martin-and-Sedra’s biquad in SI technique

It is now straightforward to obtain the circuit for the SFG in Figure 19b by exchanging the SFG brancheswith the corresponding circuit parts given in Table I and Table II. The result is shown in Figure 20. Thederived circuit needs no input sample-and-hold and is especially useful for the realization of high-qualitybandpass filters.

As already mentioned, the two half-delays connected with the coefficient k5can also be shared between the

two integrator loops. As a consequence, k2, k

3, k

6will be shifted such that only one coefficient is needed for

the realization. The price to be paid is an additional S/H at each side of the integrator for the coefficients k2

and k3. For the realization of the k

6(1!z~2) term, the half-delays of the first integrator can be used21.

Figure 21 shows the SFG and Figure 22 the circuit of the modified Martin-and-Sedra biquad in SI technique.The three SI biquad circuits derived above have been simulated using WATSNAP.8 A Monte Carlo

analysis was carried out for uniformly distributed filter coefficients (capacitor and transistor area) of 1%. Allof the models were assumed to be ideal, except for their mismatch. As a reference filter function, a second-order bandpass with a centre frequency of 500 kHz and a pole-Q of 10 was chosen. The system was designedfor a sampling frequency of 5 MHz. The coefficients are given in Table IV. For 100 simulation runs, thestandard deviation of the gain (p

'!*/) and the centre-frequency was evaluated. The simulations showed that

the performance of the derived SI circuits is similar to the corresponding SC circuit. p'!*/

of the SC, SI andmodified SI bandpass filter can be given as 0)034, 0)044 and 0)034 dB, respectively, and p

f0as 1)4, 1)6 and

1)55 kHz, respectively. The SC circuit behaviour turned out to be superior to that of the SI circuit. However,under real conditions, with finite-bandwidth opamps, offset, clock-feedthrough and other design constraints,a more realistic comparison could be made. Nevertheless, the results demonstrate that the sensitivity of thetransfer characteristics with respect to coefficient mismatch between the doubled coefficient is small.Comparative measurements of these SC and SI circuits can be found in Reference 23.

Example 5The procedure described in Example 4 can also be applied to the general SC biquad graph proposed by

Fleischer and Laker.24 The general signal-flow graph and its transposed graph are shown in Figure 23. Theintegrator output nodes can be easily identified as the voltage nodes » (1)

*/512and » (1)

*/522respectively. Since all of

the integrators are of the backward-difference type, it is Table II, Circuit 1, which has to be used in the



Figure 21. Modified SFG for Martin-and-Sedra’s biquad in SI technique: No coefficient doubling at the price of two additional S/H’s

Figure 22. Modified Martin-and-Sedra’s biquad in SI technique

Table IV. Filter coefficients for simulated bandpass filter

Circuit Coefficient

SC-filter, Figure 18 k1"0 k

2"0)08930 k

3"0)02855 k

4"0)6004 k

5"0)6393 k

6"0)0924 C

1"1, C

2"1

SI-filter, Figure 20/ Figure 22 k1"0 k

2"0)08930 k

3"0)02855 k

4"0)6004 k

5"0)6393 k

6"0)0924 Mi"1 (i"124)



Figure 23. General SFG of SC biquad circuits (a) and transposed graph (b)

uWithout loss of generality, we may set B"D"1. Furthermore, the graph has been drawn under the assumption that M"¸"0 if thebranches J, ½ are non-zero.

expanded SFG. Figure 23b shows the transposed SI graph, and Figure 24 illustrates the expanded version.uAgain, the !Az~2 branch requires two additional half-delays to realize the forward-difference integration.Thus, the correct output for this branch is the left transistor of integrator 1 during the phase /

1, i.e. node

» (1)M1

. All the weighted interconnections can be drawn either directly (Table I, d) or, in the case of theki(1!z~2) branches, by a doubling of the coefficients. The resultant graph can be mapped directly into the

circuit shown in Figure 25 by using the transformations given in Tables I and II. Again, as in the case ofExample 4, additional half-delays can circumvent the coefficient doubling at the price of additional S/H’s.



Figure 24. Expanded general SFG of SI biquad circuits

Figure 25. Circuit of general SI biquad

Example 6Cutting down the signal-flow graph of the general SI biquad to the so-called ACF-biquad with IY-inputs24

(ACF/IY-type biquad in the voltage domain) results in the circuit proposed by Hughes et al.21 There, theSI realization of the voltage-based graph was chosen, resulting in an additional input S/H, and supple-mentary current mirrors to generate the weighted input currents (see Reference 7, Chapter 8). By using thetransposed graph, the extra building blocks can be avoided with the drawback that some additionalcoefficient doubling is required. For convenience, the expanded current-based SFG is redrawn in Figure 26using the notation in Reference 21. For the actual design one has to choose between imperfect input weightswith additional input S/H (as in the case of Reference 21) and doubling of only coefficient a

6and no extra

S/H, as in the modified case. The latter solution leads to the circuit shown in Figure 27. We obtain the



Figure 26. Current-based SFG of SI biquad (ACF/IY-type)

Figure 27. Current-based circuit of SI biquad (ACF/IY-type)

transfer function as

I(1)065

I(1)*/

"!

(a5#a

6)z4#(a

1a3!a

5!2a

6)z2#a

6(1#a

4) z4#(a

2a3!a

4!2)z2#1

. (17)

Again we can superimpose the simulated frequency behaviour of the SC/SI circuits obtained using WAT-SNAP. No difference between the transfer functions was noticeable when this was done.

4.2. Double-sampling forward difference and backward difference integrators

In the following two examples, two double-sampling integrators are derived and analysed by simulation.



Figure 28. SFG (a) and circuit (b) representation for the double sampling backward difference integrator

Example 7In this example, we derive a backward difference (bd) and forward difference (fd) discrete integrator

operating at double-sampling rate. From Table II, we consider the SFG of the bilinear integrator proposedby Hughes et al.11 We recognize that the speed-doubling results from the cancellation of the term (1#z~1) inthe overall transfer function. For the realization of a bd integrator operating at twice the sampling rate ofconventional integrators, we need a (1#z~1)-term for cancellation purposes in the numerator. It can be seenfrom Table II that a backward difference and a lossless (ldi) integrator is needed. The SFG in Figure 28a canbe obtained by inspection. The transfer function between the individual phases can be given as follows:

I(1)0

I(1)*/

"

I(2)0

I(2)*/

"

a1(1#a

2)

1#2a2#a2

2!z~2

"

a1/(1#a

2)

1!1

(1#a2)2

z~2

(18)I(1)0

I(1)*/

"

I(1)0

I(2)*/

"

a1z~1

1#2a2#a2

2!z~2

"

a1z~1/(1#a

2)2

1!1

(1#a2)2

z~2

.



Figure 29. Simulated response of double-sampling backward difference integrator: (a) without damping and (b) with damping

The overall transfer function is again the column-sum of the transfer matrix,

I0

I(1)*/

"

a1

1#a2!z~1

"

a1/(1#a

2)

1!1

1#a2

z~1

. (19)

As in Reference 11, the doubling of the frequency is achieved without reducing the bandwidth of the basicsample-and-hold cell and therefore either the bandwidth of the circuit is multiplied by 2 or the powerconsumption decreased considerably. Figure 29 shows the simulated amplitude response of the circuit(Figure 28b) for the lossless and the damped case for, a

1"1, a

2"0 or 0)1 and a clock frequency of 1 MHz.

The same procedure holds also for the fd integrator. For the cancellation of the denominator term(1#z~1) in the overall transfer function, the numerator has to contain at least z~1(1#z~1). This can beachieved by combining a bd and a fd integrator. Figure 30 shows the SFG and the proposed circuit for thelossy integrator. The transfer functions for the individual clock phases and for the overall behaviour are givenin equations (20) and (21), respectively.

I(1)0

I(1)*/

"

I(2)0

I(2)*/

"

!a1z~2

1#2a2#a2

2!z~2

"

!a1z~2/(1#a

2)2

1!1

(1#a2)2

z~2

(20)

I(2)0

I(1)*/

"

I(1)0

I(2)*/

"

!a1(1#a

2)z~1

1#2a2#a2

2!z~2

"

!a1z~1/(1#a

2)

1!1

(1#a2)2

z~2



Figure 30. SFG (a) and circuit (b) representation for the double-sampling forward difference integrator

I0

I*/

"

!a1z~1

1#a2!z~1

"

!a1z~1/(1#a

2)

1!1

1#a2

z~1

(21)

The simulated amplitude response showed no difference to the one of Figure 29.

5. CONCLUSIONS

A by-inspection method for the closed form analysis of multiphase SI networks on the transistor level usingSFG techniques has been presented. The derivation of the SFG is based on simple rules which are given inthe paper. Because inputs and outputs of the network are available during every switching phase, any desiredtransfer function can be obtained by using Mason’s formula. This circumvents the calculations of differenceequations and allows us to visualize the design. Examples illustrate the procedure and show that everyinput—output relationship for any combination of switching phases can be calculated. The method is alsoa useful tool for the calculation of non-ideal effects such as channel-length modulation, mismatch of MOStransistors, clock-feedthrough and settling error. Other effects can also be added by simple expansion of theexisting rules.



The same rules which apply to the SFG derivation can also be used in the synthesis of SI circuits froma given circuit or transfer function. Several circuits have been derived from their switched-capacitorcounterparts, maintaining not only the functionality, but also essentially conserving the topology. UsingSFG manipulations, two new double sampling switched-current integrators have been presented.

REFERENCES

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IEE, Part G, 133(3), 145—153 (June 1986).3. A. Dabrowski and G. S. Moschytz, ‘Direct by-inspection derivation of signal-flow graphs for multiphase stray-insensitive switched

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¹rans. Circuits and Systems, CAS-37(5), 594—607 (May 1990).5. G. W. Roberts and A. S. Sedra, ‘Synthesizing switched-current filters by transposing the SFG of switched-capacitor filter circuits’,

IEEE ¹rans. Circuits and Systems, CAS-38(3), 337—340 (March 1991).6. A. C. M. de Queiroz, P. R. M. Pinheiro and L. P. Caloba, ‘Systematic nodal analysis of switched-current filters’, Proc. IEEE Int.

Symp. on Circuits and Systems, Singapore, June 1991, pp. 1801—1804.7. C. Toumazou, J. B. Hughes, and N. C. Battersby, Switched-Currents, An Analogue ¹echnique for Digital ¹echnology. IEE Circuits

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switched-current filters’, IEEE J. Solid-State Circuits, vol. 31(7), 898—907 (July 1996).10. G. S. Moschytz, ¸inear Integrated Networks: Fundamentals. Bell Laboratories Series. Van Nostrand Reinhold Company, New

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direct analysis and synthesis of multiphase switched-current networks using signal-flow graphs

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