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1 Distributed Active Decoupling Capacitors for On-Chip Supply Noise Cancellation in Digital VLSI Circuits Jie Gu, Ramesh Harjani and Chris H. Kim Department of Electrical and Computer Engineering University of Minnesota, Minneapolis [email protected]

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Page 1: Distributed Active Decoupling Capacitors for On-Chip ...people.ece.umn.edu/groups/VLSIresearch/papers/conferences/VLSI06_presentation.pdfDistributed Active Decoupling Capacitors for

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Distributed Active Decoupling Capacitors for On-Chip Supply Noise Cancellation in Digital VLSI Circuits

Jie Gu, Ramesh Harjani and Chris H. Kim

Department of Electrical and Computer EngineeringUniversity of Minnesota, Minneapolis

[email protected]

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Outline

• Introduction

• Proposed active decap circuits

• Simulated supply noise suppression

• Test chip implementation

• Supply noise measurement results

• Conclusion

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Power Supply Noise• Current density keeps increasing• Wire impedance does not scale as desired• Larger IR and Ldi/dt noise in scaled technology• Causes timing, substrate noise, reliability issues

Technology Generation (nm)130 115 100 90 80 70 60Ti

min

g Im

pact

(%)

02468

1012

M. Saint-Laurent, Intel

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Problematic Decoupling Capacitor• 15% to 20% of die area occupied by decaps in

high-end microprocessor• 10% of total power due to decap leakage

T. Mak, Intel

Total Power @ T=30°C/Vcc=1.15V

Transistor Leakage Decap Leak.20%

10%Active Power

Transistor Gate Leakage

Burn-In Condition @ T=100°C/Vcc=1.61V

80%-75% 20%-25%Leakage Power

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Principle and Design Target

• New circuit technique to boost decap value• Decap area reduction• Self-biasing for implementation in digital IC

A(ω)

Cload (Miller Capacitor)

(A(ω) +1)Cload

VDD VDD

Gnd

+

Cload

GndGnd

A(ω)−

+

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Previous Work

Analog Area

• Active decap for crosstalk suppression (T. Tsakada, JSSC, 2005)

• On-chip voltage regulator using switched decaps(M. Ang, ISSCC, 2000)

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Proposed Use of Active Decap in Digital IC

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Design of Active Decap Circuits

• 10MHz~2.7GHz

• Current: 3.8mA

• C-coupled inputs

• Self-biasing

• On/Off switch

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Pdecap

Adecap_10pF

Adecap_20pF

Pdecap10pF20pF40pF80pF120pF150pF

Simulated Decoupling Effects0.18µm, 25°C, 1.8V

• Decap boost 4x ~ 11x up to 1GHz• Small pdecap required for high frequency noise

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Test Chip Organization

• Scan chain to activate each module of circuits• Selection of different values of pdecap and adecap• Adecap sensor to measure differential noise

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Noise Generation CircuitsNoise Injection CircuitsLFSR Circuits

• Capable of adjusting supply noise shape and frequency• Noise injection circuit can produce more ideal noise waveforms for testing purposes

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Supply Noise SensorsGnd sensorVDD sensor

T. Okumoto, VLSI Symp., 2004

• Placed at different locations• Adecap sensor for differential supply noise

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Measurement ResultAdecap Off Adecap On

150MHz150MHz

6dB Reduction

• Noise injection circuit clocked at 150MHz• Resonant supply noise at 70MHz• 6dB reduction of supply noise using adecap

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0 0.1 0.2 0.3

-0.05

0

0.05

Gnd

(V)

0 0.1 0.2 0.3

1.75

1.8

1.85

VDD

(V)

0 0.1 0.2 0.30

0.5

1

t (µs)

Diff

. Noi

se (V

)

w/o Decap 10pF Adecap

w/o Decap 10pF Adecap

w/o Decap 10pF Adecap

Measurement Results: Supply Noise Waveform

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Measured Decoupling Effect: Pdecap vs Adecap

(Noise generated by LFSR circuits)

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Local Supply Noise Measurement

• Larger noise at location closer to noise source

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Switching On/Off Active Decaps

• Ton ~ 200ns (can be improved to less than 10ns)• Toff < 10ns

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Die Photograph

Technology 0.18µmVDD 1.8V

Passive Decap (10pF) 44µm×41µm

Active Decap (10pF)25µm×44µm

(40% reduction)

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Conclusions• Passive decap occupies large area and

consumes gate tunneling leakage

• Self-biased active decoupling capacitor circuits proposed to boost decapperformance

• 4x ~ 11x boost in decap value up to 1GHz with 40% area saving

• Decap gating capability was tested for power saving