dj3 user's manual

Preliminary Users Manual

V850E/Dx332-bit Single-Chip Microcontroller Hardware PD70F3420, PD703420 PD70F3421, PD703421 PD70F3422, PD703422 PD70F3423 PD70F3424 PD70F3425 PD70F3426 PD70F3427

Document No. U17566EE2V0UM00 Date Published 19/9/06 NEC Electronics 2006 Printed in Germany

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V850E/Dx3 Preliminary Users Manual U17566EE2V0UM00

Notes for CMOS Devices1. Precaution against ESD for semiconductors Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2. Handling of unused input pins for CMOS No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pulldown circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3. Status before initialization of MOS devices Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

Preliminary Users Manual U17566EE2V0UM00

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Legal Notes The information in this document is current as of 19/9/06. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/ or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, firecontainment and anti-failure features. NEC Electronics products are classified into the following three quality grades: Standard, Special and Specific. The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated quality assurance program for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.

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The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics 's willingness to support a given application. Note 1. "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. 2. "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). 3. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. This product uses SuperFlash technology licensed from Silicon Storage Technology, Inc.


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Regional InformationSome information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 Sucursal en Espaa Madrid, Spain Tel: 091- 504 27 87 Fax: 091- 504 28 60 Succursale Franaise Vlizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 Branch Sweden Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 6V850E/Dx3 Preliminary Users Manual U17566EE2V0UM00

NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Singapore Pte. Ltd. Singapore Tel: 65-6253-8311 Fax: 65-6250-3583 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos, Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829

PrefaceReaders Purpose Organization This manual is intended for users who want to understand the functions of the concerned microcontrollers. This manual presents the hardware manual for the concerned microcontrollers. This system specification describes the following sections: Pin function CPU function Internal peripheral function These microcontrollers may contain several instances of a dedicated module. In general the different instances of such modules are identified by the index n, where n counts from 0 to the number of instances minus one. Symbols and notation are used as follows: Weight in data notation: Left is high order column, right is low order column Active low notation: xxx (pin or signal name is over-scored) or /xxx (slash before signal name) Memory map address: High order at high stage and low order at low stage Additional remark or tip

Module instances

Legend

Note

Caution

Item deserving extra attention

Numeric notation

Binary: Decimal: Hexadecimal:

xxxx or xxxB xxxx xxxxH or 0x xxxx

Prefixes

representing powers of 2 (address space, memory capacity): K (Kilo): 210 = 1024 M (Mega): 220 = 10242 = 1,048,576 G (Giga): 230 = 10243 = 1,073,741,824 X, x = dont care Block diagrams do not necessarily show the exact wiring in hardware but the functional structure. Timing diagrams are for functional explanation purposes only, without any relevance to the real hardware implementation.

Register contents Diagrams

Further information

For further information see http://www.eu.necel.com.


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Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.3 Product Series Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chapter 2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.1.1 2.1.2 2.1.3

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2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Noise elimination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.2 Port Group Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . 402.2.1 2.2.2 2.2.3 2.2.4 2.2.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pin data input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Configuration of electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Alternative input selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.3 Port Types Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.4 Port Group Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.4.13 2.4.14 2.4.15 2.4.16 2.4.17 2.4.18 Port group configuration lists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Alphabetic pin function list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 External memory interface of PD70F3427 . . . . . . . . . . . . . . . . . . . . . . . . . 71 Port group 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Port group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Port group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Port group 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Port group 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Port group 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Port group 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Port group 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Port group 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Port group 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Port group 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Port group 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Port group 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Port group 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Port group 14 (PD70F3427 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

2.5 Noise Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932.5.1 2.5.2 Analog filtered inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Digitally filtered inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Preliminary Users Manual U17566EE2V0UM00

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Table of Contents

2.6 Pin Functions in Reset and Power Save Modes. . . . . . . . . . . . 97 2.7 Recommended connection of unused pins . . . . . . . . . . . . . . . . 98 2.8 Package Pins Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992.8.1 2.8.2 2.8.3 PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 144 pin package99 PD70F3424, PD70F3425, PD70F3426 144 pin package. . . . . . . . . 100 PD70F3427 208 pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 103

Chapter 3 CPU System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.1

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.2 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053.2.1 3.2.2 General purpose registers (r0 to r31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

3.3 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1143.3.1 3.3.2 Normal operation mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Flash programming mode (flash memory devices only) . . . . . . . . . . . . . . . 115

3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153.4.1 3.4.2 CPU address space and physical address space . . . . . . . . . . . . . . . . . . . . 115 Program and data space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

3.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193.5.1 3.5.2 Memory areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Recommended use of data address space. . . . . . . . . . . . . . . . . . . . . . . . . 124

3.6 Write Protected Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 3.7 Instructions and Data Access Times . . . . . . . . . . . . . . . . . . . . . 127

Chapter 4 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.1.1 4.1.2 4.1.3 4.1.4 4.1.5

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4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Clock monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Power save modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Start-up guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4.2 Clock Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 General clock generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SSCG control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SCPS - SSCG post scaler control register . . . . . . . . . . . . . . . . . . . . . . . . . 149 Control registers for peripheral clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Control registers for power save modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Clock monitor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

4.3 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674.3.1 Power save modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

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Table of Contents 4.3.2 4.3.3 4.3.4 Clock Generator state transistions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Power save mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 CPU operation after power save mode release . . . . . . . . . . . . . . . . . . . . . 181

4.4 Clock Generator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844.4.1 4.4.2 4.4.3 4.4.4 Ring and sub oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Watch Timer and Watch Calibration Timer clocks . . . . . . . . . . . . . . . . . . . 184 Clock output FOUTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Operation of the Clock Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 187

Chapter 5 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 5.2 Non-Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975.2.1 5.2.2 5.2.3 5.2.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Non-maskable interrupt status flag (NP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 NMI0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

5.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2035.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 xxIC - Maskable interrupts control register . . . . . . . . . . . . . . . . . . . . . . . . . 210 IMR0 to IMR5 - Interrupt mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 ISPR - In-service priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Maskable interrupt status flag (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 External maskable interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

5.4 Edge and Level Detection Configuration . . . . . . . . . . . . . . . . . 218 5.5 Software Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2205.5.1 5.5.2 5.5.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Exception status flag (EP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

5.6 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225.6.1 5.6.2 Illegal opcode definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Debug trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

5.7 Multiple Interrupt Processing Control . . . . . . . . . . . . . . . . . . . . 225 5.8 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 5.9 Periods in Which Interrupts Are Not Acknowledged . . . . . . 228

Chapter 6 Flash Memory6.1.1 6.1.2 6.1.3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Flash memory address assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Flash memory erasure and rewrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233Preliminary Users Manual U17566EE2V0UM00

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Table of Contents 6.1.4 Boot block swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

6.2 Flash Self-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2346.2.1 6.2.2 Flash self-programming registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Interrupt handling during flash self-programming . . . . . . . . . . . . . . . . . . . . 236

6.3 Flash Programming via N-Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 6.4 Flash Programming with Flash Programmer. . . . . . . . . . . . . . 2386.4.1 6.4.2 6.4.3 6.4.4 Programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Pin connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Programming method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 249

Chapter 7 Bus and Memory Control (BCU, MEMC). . . . . . . . . . . .

7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2507.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 Memory banks and chip select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Chips select priority control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 NPB access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Bus properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Boundary operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Initialization for access to external devices . . . . . . . . . . . . . . . . . . . . . . . . . 259 External bus mute function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

7.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2607.3.1 7.3.2 BCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Memory controller registers (PD70F3427 only) . . . . . . . . . . . . . . . . . . . . 271

7.4 Page ROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 7.5 Configuration of Memory Access. . . . . . . . . . . . . . . . . . . . . . . . . 2817.5.1 7.5.2 7.5.3 Endian format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Idle state insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.6 External Devices Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 2837.6.1 7.6.2 7.6.3 7.6.4 Writing to external devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Reading from external devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Read-write operation on external devices . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Write-read operation on external devices . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.7 Page ROM Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2907.7.1 7.7.2 Half word/word access with 8-bit bus or word access with 16-bit bus . . . . 291 Byte access with 8-bit bus or byte/half word access with 16-bit bus. . . . . . 293

7.8 Data Access Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2957.8.1 7.8.2 Access to 8-bit data busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Access to 16-bit data busses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 307

Chapter 8 DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Preliminary Users Manual U17566EE2V0UM00

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8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 8.2 Peripheral and CPU Clock Settings . . . . . . . . . . . . . . . . . . . . . . . 308 8.3 DMAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3108.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 DMA Source address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 DMA destination address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 DBCn - DMA transfer count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 DADCn - DMA addressing control registers . . . . . . . . . . . . . . . . . . . . . . . . 315 DCHCn - DMA channel control registers . . . . . . . . . . . . . . . . . . . . . . . . . . 317 DRST - DMA restart register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 DTFRn - DMA trigger source select register . . . . . . . . . . . . . . . . . . . . . . . . 319

8.4 Automatic Restart Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 8.5 Transfer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 8.6 Transfer Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 8.7 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 8.8 DMA Transfer Start Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 8.9 Forcible Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 8.10 Forcible Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 8.11 DMA Transfer Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 8.12 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3268.12.1 8.12.2 Single transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Block transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 329

Chapter 9 ROM Correction Function (ROMC) . . . . . . . . . . . . . . . . . .

9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 9.2 DBTRAP ROM Correction Unit . . . . . . . . . . . . . . . . . . . . . . . . . 3309.2.1 9.2.2 DBTRAP ROM correction operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 DBTRAP ROM correction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 337

Chapter 10 Code Protection and Security . . . . . . . . . . . . . . . . . . . . . . .

10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 10.2 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 10.3 N-Wire Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 10.4 Flash Writer and Self-Programming Protection . . . . . . . . . . . 33910.4.1 Variable reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 341

Chapter 11 16-bit Timer/Event Counter P (TMP) . . . . . . . . . . . . . . . .

11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 11.2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342Preliminary Users Manual U17566EE2V0UM00

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11.4 TMP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 11.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35611.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.5.8 Interval timer mode (TPnMD2 to TPnMD0 = 000). . . . . . . . . . . . . . . . . . . . 356 External event count mode (TPnMD2 to TPnMD0 = 001). . . . . . . . . . . . . . 365 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010) . . . . . . . 374 One-shot pulse output mode (TPnMD2 to TPnMD0 = 011) . . . . . . . . . . . . 385 PWM output mode (TPnMD2 to TPnMD0 = 100) . . . . . . . . . . . . . . . . . . . . 392 Free-running timer mode (TPnMD2 to TPnMD0 = 101) . . . . . . . . . . . . . . . 401 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) . . . . . . . . . 418 Timer output operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

11.6 Operating Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42511.6.1 11.6.2 Capture operation in pulse width measurement and free-running mode . . 425 Count jitter for PCLK4 to PCLK7 count clocks . . . . . . . . . . . . . . . . . . . . . . 425 427

Chapter 12 16-bit Interval Timer Z (TMZ) . . . . . . . . . . . . . . . . . . . . . . . . .12.1.1 12.1.2

12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

12.2 TMZ Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 12.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43312.3.1 12.3.2 Steady operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Timer start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 435

Chapter 13 16-bit Multi-Purpose Timer G (TMG) . . . . . . . . . . . . . . . .

13.1 Features of Timer G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 13.2 Function Overview of Each Timer Gn. . . . . . . . . . . . . . . . . . . . . 436 13.3 Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 13.4 TMG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 13.5 Output Delay Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 13.6 Explanation of Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 448 13.7 Operation in Free-Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 13.8 Match and Clear Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 13.9 Edge Noise Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 13.10 Precautions Timer Gn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

Chapter 14 Watch Timer (WT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14.1.1 14.1.2

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14.2 Watch Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48014Preliminary Users Manual U17566EE2V0UM00

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14.3 Watch Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48414.3.1 14.3.2 Timing of steady operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 Watch Timer start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

14.4 Watch Calibration Timer Registers . . . . . . . . . . . . . . . . . . . . . . . 487 14.5 Watch Calibration Timer Operation . . . . . . . . . . . . . . . . . . . . . . . 49214.5.1 14.5.2 INTWT0UV interval measurement with free-running counter . . . . . . . . . . . 493 INTWT0UV interval measurement by restarting the counter . . . . . . . . . . . 494 495

Chapter 15 Watchdog Timer (WDT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15.1.1 15.1.2 15.1.3 15.1.4

15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Watchdog Timer clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

15.2 Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

Chapter 16 Asynchronous Serial Interface (UARTA) . . . . . . . . . . .

505

16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 16.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 16.3 UARTA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 16.4 Interrupt Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 16.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51716.5.1 16.5.2 16.5.3 16.5.4 16.5.5 16.5.6 16.5.7 16.5.8 16.5.9 16.5.10 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 SBF transmission/reception format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 SBF transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 SBF reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 UART transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Continuous transmission procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 UART reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Parity types and operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 Receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

16.6 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53016.6.1 16.6.2 16.6.3 16.6.4 16.6.5 16.6.6 16.6.7 Baud Rate Generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Baud Rate Generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Baud rate calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Baud rate setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 Allowable baud rate range during reception . . . . . . . . . . . . . . . . . . . . . . . . 534 Baud rate during continuous transmission . . . . . . . . . . . . . . . . . . . . . . . . . 536

16.7 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

Chapter 17 Clocked Serial Interface (CSIB)Preliminary Users Manual U17566EE2V0UM00

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17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 17.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 17.3 CSIB Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 17.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54817.4.1 17.4.2 17.4.3 17.4.4 17.4.5 17.4.6 17.4.7 17.4.8 Single transfer mode (master mode, transmission/reception mode). . . . . . 548 Single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . 550 Continuous mode (master mode, transmission/reception mode) . . . . . . . . 551 Continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 552 Continuous reception mode (error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 Continuous mode (slave mode, transmission/reception mode) . . . . . . . . . 554 Continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . 556 Clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

17.5 Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 17.6 Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 17.7 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56617.7.1 17.7.2 17.7.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Baud Rate Generator registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Baud rate calculation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 569

Chapter 18 I2C Bus (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 18.2 I2C Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 18.3 I2C Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 18.4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 18.5 IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 18.6 I2C Bus Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 18.7 I2C Bus Definitions and Control Methods . . . . . . . . . . . . . . . . . 59018.7.1 18.7.2 18.7.3 18.7.4 18.7.5 18.7.6 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Transfer direction specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Acknowledge signal (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 Wait signal (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 I2C Interrupt Request Signals (INTIICn) . . . . . . . . . . . . . . . . . . . 598 Master device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 Slave device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 Slave device operation (when receiving extension code) . . . . . . . . . . . . . . 605 Operation without communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 Arbitration loss operation (operation as slave after arbitration loss) . . . . . . 609 Operation when arbitration loss occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

18.818.8.1 18.8.2 18.8.3 18.8.4 18.8.5 18.8.6

18.9 Interrupt Request Signal (INTIICn) . . . . . . . . . . . . . . . . . . . . . . . . 61616Preliminary Users Manual U17566EE2V0UM00

Table of Contents

18.10 Address Match Detection Method . . . . . . . . . . . . . . . . . . . . . . . . 617 18.11 Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 18.12 Extension Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 18.13 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 18.14 Wakeup Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 18.15 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 18.16 Communication Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62118.16.1 18.16.2 18.16.3 Master operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 Master operation 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 Slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

18.17 Timing of Data Communication . . . . . . . . . . . . . . . . . . . . . . . . . . 628

Chapter 19 CAN Controller (CAN)19.1.1 19.1.2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636Overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

19.2 CAN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63919.2.1 19.2.2 19.2.3 19.2.4 19.2.5 Frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 Frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 Data frame and remote frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 Error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 Overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

19.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64819.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 Determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 Bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 Multi masters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 Multi cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 CAN sleep mode/CAN stop mode function . . . . . . . . . . . . . . . . . . . . . . . . . 650 Error control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 Baud rate control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

19.4 Connection with Target System . . . . . . . . . . . . . . . . . . . . . . . . . . 660 19.5 Internal Registers of CAN Controller . . . . . . . . . . . . . . . . . . . . . 66119.5.1 19.5.2 19.5.3 19.5.4 CAN module register and message buffer addresses . . . . . . . . . . . . . . . . 661 CAN Controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 CAN registers overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

19.6 Bit Set/Clear Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 19.7 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 19.8 CAN Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70819.8.1 19.8.2 Initialization of CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 Initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708


17

Table of Contents 19.8.3 19.8.4 19.8.5 Redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 Transition from initialization mode to operation mode. . . . . . . . . . . . . . . . . 710 Resetting error counter CnERC of CAN module. . . . . . . . . . . . . . . . . . . . . 711

19.9 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71219.9.1 19.9.2 19.9.3 19.9.4 19.9.5 19.9.6 Message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 Receive data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 Receive history list function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 Mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 Multi buffer receive block function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 Remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

19.10 Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72019.10.1 19.10.2 19.10.3 19.10.4 19.10.5 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 Transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 Automatic block transmission (ABT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 Transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

19.11 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72819.11.1 19.11.2 19.11.3 CAN sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 CAN stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 Example of using power saving modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

19.12 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 19.13 Diagnosis Functions and Special Operational Modes. . . . . 73419.13.1 19.13.2 19.13.3 19.13.4 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 Single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 Self-test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 Receive/transmit operation in each operation mode. . . . . . . . . . . . . . . . . . 737

19.14 Time Stamp Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73819.14.1 Time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

19.15 Baud Rate Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73919.15.1 19.15.2 Baud rate setting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 Representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . 743

19.16 Operation of CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747

Chapter 20 A/D Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

773

20.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 20.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 20.3 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 20.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78520.4.1 20.4.2 20.4.3 20.4.4 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 Trigger mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 Operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 Power-fail compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

18


Table of Contents

20.5 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 20.6 How to Read A/D Converter Characteristics Table . . . . . . . . 794

Chapter 21 Stepper Motor Controller/Driver (Stepper-C/D) . . . .21.1.1

799

21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799Driver overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799

21.2 Stepper Motor Controller/Driver Registers. . . . . . . . . . . . . . . . 801 21.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80721.3.1 Stepper Motor Controller/Driver operation . . . . . . . . . . . . . . . . . . . . . . . . . 807

21.4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81021.4.1 21.4.2 Timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 Automatic PWM phase shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 813

Chapter 22 LCD Controller/Driver (LCD-C/D) . . . . . . . . . . . . . . . . . . . .22.1.1 22.1.2

22.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 LCD panel addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815

22.2 LCD-C/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 22.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82022.3.1 22.3.2 Common signals and segment signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 Activation of LCD segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

22.4 Display Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

Chapter 23 LCD Bus Interface (LCD-I/F) . . . . . . . . . . . . . . . . . . . . . . . . .23.1.1 23.1.2 23.1.3 23.1.4

827

23.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 LCD Bus Interface access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 Access types to the LBDATA0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 Interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

23.2 LCD Bus Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 23.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83823.3.1 23.3.2 23.3.3 23.3.4 23.3.5 Timing dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 LCD Bus I/F states during and after accesses . . . . . . . . . . . . . . . . . . . . . . 839 Writing to the LCD bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 Reading from the LCD bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842 Write-Read-Write sequence on the LCD bus . . . . . . . . . . . . . . . . . . . . . . . 844 845

Chapter 24 Sound Generator (SG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24.1.1 24.1.2



19

Table of Contents

24.2 Sound Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 24.3 Sound Generator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85324.3.1 24.3.2 Generating the tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 Generating the volume information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854

24.4 Sound Generator Application Hints . . . . . . . . . . . . . . . . . . . . . . 85724.4.1 24.4.2 24.4.3 24.4.4 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 Start and stop sound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 Change sound volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 Generate special sounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

Chapter 25 Power Supply Scheme

25.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 25.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86125.2.1 25.2.2 25.2.3 Devices PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 . . 861 Devices PD70F3424, PD70F3425, PD70F3426. . . . . . . . . . . . . . . . . . 862 Device PD70F3427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

25.3 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864

Chapter 26 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26.1.1 26.1.2 26.1.3 26.1.4 26.1.5

865

26.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865General reset performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 Reset at power-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869 External RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 Reset by Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 Reset by Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

26.2 Reset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871

Chapter 27 Voltage Comparator27.1.1 27.1.2 27.1.3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

27.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 Comparison results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876

27.2 Voltage Comparator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 877 27.3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879

Chapter 28 On-Chip Debug Unit28.1.1 28.1.2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

28.1 Functional Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881Debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 Security function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883

28.2 Controlling the N-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 886 28.3 N-Wire Enabling Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88828.3.1 20 Starting normal operation after RESET and RESPOC . . . . . . . . . . . . . . . . 888Preliminary Users Manual U17566EE2V0UM00

28.3.2 28.3.3

Starting debugger after RESET and RESPOC . . . . . . . . . . . . . . . . . . . . . . 888 N-Wire activation by RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889

28.4 Connection to N-Wire Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . 89028.4.1 KEL connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890

28.5 Restrictions and Cautions on On-Chip Debug Function . . 894

Appendix A Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix B Registers Access Times

895

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 925 929

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


21

22


Chapter 1 IntroductionThe V850E/Dx3 is a product line in NEC Electronics V850 family of single-chip microcontrollers designed for automotive applications.

1.1 GeneralThe V850E/Dx3 single-chip microcontroller devices make the performance gains attainable with 32-bit RISC-based controllers available for embedded control applications. The integrated V850 CPU offers easy pipeline handling and programming, resulting in compact code size comparable to 16-bit CISC CPUs. The V850E/Dx3 provide an excellent combination of general purpose peripheral functions, like serial communication interfaces (UARTs, Clocked Serial Interfaces), timers, and measurement inputs (A/D Converter), with dedicated CAN network support. The devices offer specific power-saving modes to manage the power consumption effectively under varying conditions. Thus equipped, the V850E/Dx3 product line is ideally suited for automotive applications, like dashboard or body. It is also an excellent choice for other applications where a combination of sophisticated peripheral functions and CAN network support is required. (1) V850E CPU The V850E CPU core is a RISC processor. Through the use of basic instructions that can be executed in one clock period combined with an optimized pipeline architecture, it achieves marked improvements in instruction execution speed. In addition, to make it ideal for use in digital control applications, a 32-bit hardware multiplier enables this CPU to support multiply instructions, saturated multiply instructions, bit operation instructions, etc. Through two-byte basic instructions and instructions compatible with high level languages, the object code efficiency in a C compiler is increased, and program size can be reduced. Further, because the on-chip interrupt controller provides high-speed interrupt response and processing, this device is well suited for high level real-time control applications. (2) On-chip flash memory The V850E/Dx3 microcontrollers have on-chip flash memory. It is possible to program the controllers directly in the target environment where they are mounted. With this feature, system development time can be reduced and system maintainability after shipping can be markedly improved.


23

Chapter 1 (3) A full range of software development tools

Introduction

A development system is available that includes an optimized C compiler, debugger, in-circuit emulator, simulator, system performance analyzer, and other elements.

1.2 Features SummaryThe following table provides a quick summary of the most outstanding features. Table 1-1CPU Core Number of instructions Minimum instruction execution time V850E1 81 14.881 ns (@ = 67.2 MHz) (PD70F3424, PD70F3425, PD70F3426, PD70F3427) a 29.762 ns (@ = 33.6 MHz) (PD70F3420, PD70F3421, PD70F3422, PD70F3423) 39.683 ns (@ = 25.2 MHz) (PD703420, PD703421, PD703422) 32 registers (32 bits each)

V850E/Dx3 features summary (1/4)

General registers Instruction set

V850E (compatible with V850 plus additional powerful instructions for reducing code and increasing execution speed) Signed multiplication (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits): 1 to 2 clocks Saturated operation instructions (with overflow/underflow detection) 32-bit shift instructions: 1 clock Bit manipulation instructions Load/store instructions with long/short format Signed load instructions Internal flash memory Size 2 MB (PD70F3426) 1 MB (PD70F3427, PD70F3425) 512 KB (PD70F3424, PD70F3423) 384 KB (PD70F3422) 256 KB (PD70F3421) 128 KB (PD70F3420)

Flash protection Secure self programming Internal mask ROM memory Size

N-Wire security function external programmer security function

384 KB (PD703422) 256 KB (PD703421) 128 KB (PD703420)

24


Introduction Table 1-1Internal data RAM Size 84 KB (PD70F3426) 60 KB (PD70F3427) 32KB (PD70F3425) 24 KB (PD70F3424) 20 KB (PD70F3423) 16 KB (PD70(F)3422) 12 KB (PD70(F)3421) 6 KB (PD70(F)3420)

Chapter 1 V850E/Dx3 features summary (2/4)

Clock Generator Internal spread-spectrum PLL (SSCG) Internal PLL CPU frequency range 12-fold/16-fold, up to 64 MHz 5 % a 8-fold, 32 MHz up to 67.2 MHz (PD70F3424, PD70F3425, PD70F3426, PD70F3427) a up to 33.6 MHz (PD70F3420, PD70F3421, PD70F3422, PD70F3423) up to 25.2 MHz (PD703420, PD703421, PD703422) up to 16 MHz 4 MHz 32 KHz (typ.) 240 KHz (typ.) 2 channels: main oscillator monitor sub oscillator monitor

Peripheral frequency range Main crystal frequency range (main oscillator) Sub oscillator Ring oscillator Clock supervision

Auxiliary frequency output Built-in power saving modes HALT / IDLE / WATCH / Sub-WATCH / STOP External memory bus interface (PD70F3427 only) Address/data separated busses Chip select signals DMA Controller Number of channels I/O ports Input/output ports Input ports A/D Converter Number of channels 16 (PD70F3424, PD70F3425, PD70F3426, PD70F3427) 12 (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423) 10-bit Continuous select mode Continuous scan mode Timer trigger mode Software trigger mode PD70F3427: 101 all others: 98 16 4 24/32-bit 4

Resolution Conversion modes

Analog input channels shared with digital input port functionalityPreliminary Users Manual U17566EE2V0UM00

25

Chapter 1 Table 1-1Serial interfaces Synchroneous: CSI (CSIB)

Introduction V850E/Dx3 features summary (3/4)

3 channels (PD70F3424, PD70F3425, PD70F3426, PD70F3427) 2 channels (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423) 2 channels with LIN support 2 channels 2 channels with 32 message buffers each

Asynchroneous: UART (UARTA) I2 C (IIC)

CAN (CAN) Timers 16-bit multi purpose timer/event counter (TMP) 16-bit multi purpose timer/counter (TMG) 16-bit multi purpose timer/counter (TMZ)

4 channels 3 channels 10 channels (PD70F3424, PD70F3425, PD70F3426, PD70F3427) 6 channels (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423) 1 channel 1 channel 1 channel

Watch Timer (WT) Watch Calibration Timer (WCT) Watchdog Timer (WDT)

LCD Controller/Driver (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423) Segment signal output Common signal output Modes LCD Bus Interface Bus width Bus control modes 8-bit parallel 2 modes: RD strobe and WR strobe (mod80) RD/WR signal and data strobe (mod68) 100 KHz to 3.2 MHz max. 40 max. 4 1/4 duty, 1/3 bias

Transfer speed Stepper Motor Controller/Driver Number of channels Resolution Sound Generator Number of channels Volume Sound frequency Sound duration Interrupts and exceptions Non-maskable interrupts Maskable interrupts

6 8-bit and 8-bit + 1

1 9-bit volume level accuracy 245 Hz to 6 KHz with min. resolution of 20 Hz 256 steps

2 sources 92 sources (PD70F3424, PD70F3425, PD70F3426, PD70F3427) 84 sources (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423) 32 sources 2 sources

Software exceptions Exception trap

26


Introduction Table 1-1ROM Correction Number of channels On-chip debug interface Number of interfaces Connection of an external N-Wire emulator Internal Voltage Comparators Number of channels Power supply supervision Power-On-Clear Single supply operating voltage Range Temperature range Range 2 1 8 channels by DBTRAP

Chapter 1 V850E/Dx3 features summary (4/4)

Generates reset at power-up and in case of power loss

4.0 V to 5.5 V (refer to Electrical Target Specification)

Ta = 40 to +85C @ = 64 MHz) (PD70F3424, PD70F3425, PD70F3426, PD70F3427) a @ = 32 MHz) (PD70F3420, PD70F3421, PD70F3422, PD70F3423) @ = 24 MHz) (PD703420, PD703421, PD703422)

Package Package Package size Pin pitch CMOS technologya)

PD70F3427: 208-pin QFP all others: 144-pin QFP PD70F3427: 28 mm 28 mm all others: 20 mm 20 mm 0.5 mm

The minimum instruction execution time of 1/67.2 MHz = 14.881 ns (typical 1/64 MHz = 15.625 ns) is under evaluation and thus may be changed in future.

Note

The CAN controller of this device fulfils the requirements according ISO 11898. Additionally, the CAN controller was tested according to the test procedures required by ISO 16845. The CAN controller has successfully passed all test patterns. Beyond these test patterns, other tests like robustness tests and processor interface tests as recommended by C&S/FH Wolfenbuettel have been performed with success.


27

28PD703422none 384 KB 24 KB 4 ch 32 MHz typ., 33.6 MHz max.d 240 KHz typ. 32 KHz typ. 98 16 16 channels 10 channels 4 channels 3 channels 1 channel provided provided 2 channels 2 channels 3 channels 2 channels 2 channels 12 channels 6 channels 24 MHz typ., 25.2 MHz max.d 32 MHz typ., 33.6 MHz max.d 24 MHz typ., 25.2 MHz max.d 32 MHz typ., 33.6 MHz max.d 24 MHz typ., 25.2 MHz max.d 20 KB 16 KB 12 KB none 256 KB 256 KB none

1.3 Product Series Overview

Chapter 1

Table 1-2 shows the common and different features of the microcontrollers.

An overview of the feature differences gives Table 1-3.

Table 1-2PD70F3421 PD703421

V850E/Dx3 product series overview (1/2)PD70F3420128 KB none 6 KB

Part number1 MB none 32 KB 512 KB 384 KB

PD70F3427 PD70F3426 PD70F3425 PD70F3424 PD70F3423 PD70F3422

PD703420none 128 KB

Internal memory

Flash

1 MB

1 MB + 1 MBa

ROM

RAM

60 KB

60 KB + 24 KBa

External memory interface

provided

DMA

Operating clock

Main oscillator with SSCGb

64 MHz typ., 67.2 MHz max.c

Ring oscillator


Sub oscillator

I/O ports

Input/Output

101

Input

A/D converter

Timers

TMZ

TMP

TMG

WDT

Watch

Watch calibration

Serial CAN interfaces UARTA

CSIB

Introduction

I2C

Table 1-2PD7034227 channels 91 channels 2 channels 83 channels 79 channels 75 channels 79 channels 75 channels

V850E/Dx3 product series overview (2/2)PD70F3421 PD703421 PD70F3420 PD703420

298 channels 87 channels 8 channels provided 2 channels 2 channels 1 channel 6 channels none provided provided provided 3.5 V to 5.5 Vd 144-pin QFP 40 x 4

Part number

PD70F3427 PD70F3426 PD70F3425 PD70F3424 PD70F3423 PD70F3422

Chapter 1

Interrupts

External

Internal

91 channels

NMI

Other functions

ROM Correction by DBTRAP

8 channels

2 x 8 channels

Power-On-Clear

Voltage Comparator

Clock supervision

Sound Generator

Stepper Motor Controller/Driver

LCD-Controller/Driver

LCD Bus Interface

Auxiliary frequency output

On-Chip debug

Operating voltage


Package

208-pin QFP

a)

b)

c)

d)

The additional 1 MB flash memory respectively 24 KB RAM is accessible via the VSB, and thus requires an additional CPU clock cycle. SSCG: spread spectrum clock generator The operation clock of typ. 64 MHz (max. 67.2 MHz) is under evaluation and thus may be changed in future. Refer to the Electrical Target Specification. Refer to the Electrical Target Specification.

Introduction

Chapter 1

Introduction

1.4 DescriptionFigure 1-1 provides a functional block diagram of the V850E/DJ3 PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423, PD70F3424, PD70F3425, PD70F3426 microcontrollers.

Power and ResetVCMP0, VCMP1 VCMPO0, VCMPO1

2 x Voltage Comparator

Reset

POC

Power supply

NMI INTP0 to INTP6 INTP7Note 1

Note 1

CPU CPU Core

Interrupt Controller

ROM CorrectionNote 8

Note 6

Memory

FlashNote 7

VSB (V850 System Bus)

Serial InterfacesRXDA0, RXDA1 TXDA0, TXDA1 SIB0, SIB1, SIB2Note 2 SOB0, SOB1, SOB2Note 2 SCKB0, SCKB1, SCKB2Note 2 CRXD0, CRXD1 CTXD0, CTXD1 SDA0, SDA1 SCL0, SCL1

System Controller2 x UARTABRG

ROM correction

RAM

ROM

Note 9

1 MB VSB FlashNote 10

Standby Controller Bus Control UnitDMA

Note 2

3/2 x CSIBBRG

On-Chip Debug Unit2 x CAN 2 x I2C

16 KB VSB RAM

Bus Bridge

NPB (NEC Peripheral Bus) Control InterfacesANI0-ANI11 ANI12-ANI15Note 3

Note 3

10-bit ADC 16/12 channels

Ports

AVREFSM11 to SM14 SM21 to SM24 SM31 to SM34 SM41 to SM44 SM51 to SM54 SM61 to SM64 SGO/SGOF SGOA SEG0 to SEG39 COM0 to COM3 DBD0 to DBD7 DBRD DBWR P00 to P07 P16 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P715 P80 to P87 P90 to P97 P100 to P107 P110 to P117 P120 to P127 P130 to P137

Stepper Motor C/D

Clock Generator Ring oscillator

SG0 LCD C/DNote 4 Note 2

Sub oscillator

XT1 XT2

Note 1

Main oscillator16-bit Timer TMZ0 - TMZ5Note 5

X1 X2

LCD Bus I/F

Clock GeneratorRESETSpread Spectrum PLL PLL

TimersTIG01 to TIG04 TIG11 to TIG14 TIG21 to TIG24

16-bit Timer TMZ6 - TMZ9 16-bit Timer TMG0 - TMG2 Watch and Watch Correction Timer

FOUT FOUT

TOG01 to TOG04 TOG11 to TOG14 TOG21 to TOG24 TIP00, TIP01 TIP10, TIP11 TIP20, TIP21 TIP30, TIP31 TOP00, TOP01 TOP10, TOP11 TOP20, TOP21 TOP30, TOP31

16-bit Timer WCT

Main and Sub oscillator Supervision

16-bit Timer WT 16-bit Timer TMP0 - TMP3

Auxiliary FunctionsDMS DRST DDI DDO DCK

Watchdog Timer

N-Wire debug I/F

Figure 1-1

V850E/DJ3 PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423, PD70F3424, PD70F3425, PD70F3426 block diagram

30


Introduction

Chapter 1 Table 1-3 summarizes the different features of the of the V850E/DJ3 PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423, PD70F3424, PD70F3425, PD70F3426 microcontrollers, marked as Notes in Figure 1-1.

Table 1-3Note 1 2 3 4 5 6 7 8 9 10 Feature INTP7 CSIB2 ANI12 to ANI15 LCD-C/D TMZ6 to TMZ9 Flash ROM RAM VSB Flash VSB RAM

Feature set differencesF3425 1 MB 32 KB F3424 512 KB 24 KB F3423 512 KB 20 KB F3422 384 KB 16 KB 3422 384 KB 16 KB F3421 256 KB 12 KB 3421 256 KB 12 KB F3420 128 KB 6 KB 3420 128 KB 6 KB

F3426

1 MB 60 KB 1 MB 24 KB


31

Chapter 1

Introduction Figure 1-2 provides a functional block diagram of the V850E/DL3 PD70F3427 microcontroller.

Power and ResetVCMP0, VCMP1 VCMPO0, VCMPO1

2 x Voltage Comparator

Reset

POC

Power supply

CPUNMI INTP0 to INTP7

MemoryROM Correction

Interrupt Controller

Flash

CPU Core

Serial InterfacesRXDA0, RXDA1 TXDA0, TXDA1 SIB0, SIB1, SIB2 SOB0, SOB1, SOB2 SCKB0, SCKB1, SCKB2 CRXD0, CRXD1 CTXD0, CTXD1 SDA0, SDA1 SCL0, SCL1

RAM System Controller2 x UARTABRG

Standby Controller Bus Control UnitDMA

Memory Controller

3 x CSIBBRG

On-Chip Debug Unit2 x CAN 2 x I2C

A0 to A23 D0 to D15 D16 to D31 CS0, CS1 CS3, CS4 BE3 to BE0 RD WR WAIT BCLK

Bus Bridge

NPB (NEC Peripheral Bus) Control Interfaces10-bit ADC 16 channels Ports

ANI0-ANI15

SM11 to SM14 SM21 to SM24 SM31 to SM34 SM41 to SM44 SM51 to SM54 SM61 to SM64 SGO/SGOF SGOA DBD0 to DBD7 DBRD DBWR

Stepper Motor C/D

P00 to P07 P16 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P715 P80 to P87 P90 to P97 P100 to P107 P110 to P117 P120 to P127 P130 to P137 P140 to P142

Clock Generator Ring oscillator

Sound Generator

Sub oscillator

XT1 XT2

LCD Bus I/F

Main oscillator

X1 X2

Clock Generator TimersTIG01 to TIG04 TIG11 to TIG14 TIG20 to TIG25RESETSpread Spectrum PLL

16-bit Timer TMZ0 - TMZ9 16-bit Timer TMG0 - TMG2 Watch and Watch Correction Timer

PLL

FOUT FOUT

TOG01 to TOG04 TOG11 to TOG14 TOG21 to TOG24 TIP00, TIP01 TIP10, TIP11 TIP20, TIP21 TIP30, TIP31 TOP00, TOP01 TOP10, TOP11 TOP20, TOP21 TOP30, TOP31

16-bit Timer WCT

Main and Sub oscillator Supervision

16-bit Timer WT 16-bit Timer TMP0 - TMP3

Auxiliary FunctionsDMS DRST DDI DDO DCK

Watchdog Timer

N-Wire debug I/F

Figure 1-2

V850E/DL3 PD70F3427 block diagram

32


Introduction Structure of the diagram

Chapter 1 In the diagram, the building blocks are grouped according to their function. At the top of the diagram, you find the functions for controlling power supply and reset. The upper right-hand section shows the building blocks of the CPU system and the memory interface components. The I/O ports are summarized below that section. The left-hand section of the block diagram identifies the interfaces to peripherals and also the built-in timers. All these components are connected to and can be controlled via the internal bus. The Clock Generator, depicted in the lower right-hand section, plays a central role. It generates and monitors not only the clocks for the CPU and the peripheral interfaces, but also governs the power save modes that can be entered when the device is not in use.

Structure of the manual

This manual explains how to use the V850E/Dx3 microcontroller devices. It provides comprehensive information about the building blocks, their features, and how to set registers in order to enable or disable specific functions. The manual provides individual chapters for the building blocks. These chapters are organized according to the grouping in the diagram. Core functions Pin Functions on page 33 CPU System Functions on page 103 Clock Generator on page 129 Interrupt Controller (INTC) on page 187 Memory access Flash Memory on page 229 Bus Control Unit (BCU) on page 211 DMA Controller (DMAC) on page 307 ROM Correction Function (ROMC) on page 329 Code Protection and Security on page 337 Timers 16-bit Timer/Event Counter P (TMP) on page 341 16-bit Interval Timer Z (TMZ) on page 427 16-bit Multi-Purpose Timer G (TMG) on page 435 Watch Timer (WT) on page 475 Watchdog Timer (WDT) on page 495 Serial interfaces Asynchronous Serial Interface (UARTA) on page 505 Clocked Serial Interface (CSIB) on page 537 I2C Bus (IIC) on page 569 CAN Controller (CAN) on page 635 Control interfaces A/D Converter (ADC) on page 773 Stepper Motor Controller/Driver (Stepper-C/D) on page 799 LCD Controller/Driver (LCD-C/D) on page 813 LCD Bus Interface (LCD-I/F) on page 827 Sound Generator (SG) on page 845Preliminary Users Manual U17566EE2V0UM00

33

Chapter 1 Power and reset Power Supply Scheme on page 859 Reset on page 865 Voltage Comparator on page 875 Auxiliary functions On-Chip Debug Unit on page 881

Introduction

1.5 Ordering InformationTable 1-4NEC order code UPD703420GJ(A)-GAE-QS-AX UPD70F3420GJ(A)-GAE-QS-AX UPD703421GJ(A)-GAE-QS-AX UPD70F3421GJ(A)-GAE-QS-AX UPD703422GJ(A)-GAE-QS-AX UPD70F3422GJ(A)-GAE-QS-AX UPD70F3423GJ(A)-GAE-QS-AX UPD70F3424GJ(A)-GAE-QS-AX UPD70F3425GJ(A)-GAE-QS-AX UPD70F3426GJ(A)-GAE-QS-AX UPD70F3427GD(A)-LML-QS-AX

V850E/Dx3 ordering informationPin/package 144 pin LQFP 144 pin LQFP 144 pin LQFP 144 pin LQFP 144 pin LQFP 144 pin LQFP 144 pin LQFP 144 pin LQFP 144 pin LQFP 144 pin LQFP 208 pin QFP Memory size 128 KB ROM 128 KB flash 256 KB ROM 256 KB flash 384 KB ROM 384 KB flash 512 KB flash 512 KB flash 1 MB flash 2 MB flash 1 MB flash Remarks VSB flash and RAM External bus I/F

34


Chapter 2 Pin FunctionsThis chapter lists the ports of the microcontroller. It presents the configuration of the ports for alternative functions. Noise elimination on input signals is explained and a recommendation for the connection of unused pins is given at the end of the chapter.

2.1 OverviewThe microcontroller offers various pins for input/output functions, so-called ports. The ports are organized in port groups. To allocate other than general purpose input/output functions to the pins, several control registers are provided. For a description of the terms pin, port or port group, see Terms on page 39. Features summary Number of ports and port groups:Device Number of ports I/O ports 101 98 Input ports 16 16 Number of port groups 15 14

PD70F3427 all others

5V I/O: Can be used as 3V I/O with degraded electrical parameters. Please refer to the Electrical Target Specification. 24 high-drive ports for direct stepper motor drive. Configuration possible for individual pins. The following features can be selected for most of the pins: One out of two input thresholds Output current limit Open drain emulation 8 ports for Schmitt and non-Schmitt chararacteristic configurable. The following registers are offered for most of the ports: Direct register for reading the pin values Port register with selectable read source (for improved bit set / bit clear capabilities)


35

Chapter 2

Pin Functions

2.1.1 DescriptionThis microcontroller has the port groups shown below.

P00 Port group 0 to P07

P70 to P715 P80 Port group 7

Port group 1

P16 P17

to P87

Port group 8

P20 Port group 2 to P27 P30 Port group 3 to P37 P40 Port group 4 to P47 P50 Port group 5 to P57 P60 Port group 6 to P67

P90 to P97 P100 to P107 P110 to P117 P120 to P127 P130 to P137 P140 to P142 Port group 14 (PD70F3427 only) Port group 13 Port group 12 Port group 11 Port group 10 Port group 9

MEM-I/F

External memory interface (PD70F3427 only)

Figure 2-1

Port groups

36


Pin Functions Port group overview

Chapter 2 Table 2-1 gives an overview of the port groups. For each port group it shows the supported functions in port mode and in alternative mode. Any port group can operate in 8-bit or 1-bit units. Port group 7 can additionally operate in 16-bit units. Functions of each port group (1/2)Port group name 0 Function Port mode 8-bit input/output Alternative mode External interrupt 0 to 6 Non maskable interrupt N-Wire debug interface reset Output state of internal Voltage Comparators 0

Table 2-1

1 2

2-bit input/output 8-bit input/output

I2C0 data/clock line Timer TMG0 to TMG1 channels I2C1 data/clock line LCD controller segment signal output (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 only) UARTA0 transmit/receive data, UARTA1 transmit/receive data I2C1 data/clock line LCD controller segment signal output (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 only) Timer TMG2 channels Timer TMP0 to TMP3 channels

3

8-bit input/output

4

8-bit input/output

Clocked Serial Interface CSIB0 data/clock line Clocked Serial Interface CSIB1 data/clock line LCD controller segment signal output (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 only) CAN0 transmit/receive data External interrupt 7 (PD70F3424, PD70F3425, PD70F3426, PD70F3427 only) Sound Generator outputs Frequency output N-Wire interface signals CAN1 transmit/receive data UARTA1 transmit/receive data Timer TMP0 to TMP3 channels Timer TMG2 channels LCD controller segment signal output (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 only) I2C0 data/clock line A/D Converter input - PD70F3424, PD70F3425, PD70F3426, PD70F3427: 16 channels - PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423: 12 channels

5

8-bit input/output

6

8-bit input/output

7

16-bit input


37

Chapter 2 Table 2-1 Functions of each port group (2/2)Port group name 8 Function Port mode 8-bit input/output Alternative mode

Pin Functions

Clocked Serial Interface CSIB2 data/clock line (PD70F3424, PD70F3425, PD70F3426, PD70F3427 only) LCD controller segment signal output (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 only) Frequency output UARTA0 transmit/receive data LCD Bus I/F data lines LCD controller segment/common signal output (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 only) Timer TMP0 to TMP3 channels LCD Bus I/F read/write strobe LCD controller segment signal output (PD70(F)3420, PD70(F)3421, PD70(F)3422, PD70F3423 only) Clocked Serial Interface CSIB0 data/clock line Stepper Motor Controller/Driver outputs Stepper Motor Controller/Driver outputs Stepper Motor Controller/Driver outputs Timer TMG0 to TMG1 channels External memory interface (PD70F3427 only): Bus clock Byte enable 2, 3 External memory interface (PD70F3427 only): Address lines 0 to 23 Chip selects 0, 1, 3, 4 Read/write strobe Data wait request Byte enable 0, 1 Data lines 0 to 31

9

8-bit input/output

10

8-bit input/output

11 12 13 14

8-bit input/output 8-bit input/output 8-bit input/output 3-bit input/output

MEM-I/F

Pin configuration

To define the function and the electrical characteristics of a pin, several control registers are provided. For a general description of the registers, see Port Group Configuration Registers on page 40. For every port, detailed information on the configuration registers is given in Port Group Configuration on page 56. There are three types of control circuits, defined as port types. For a description of the port types, see Port Types Diagrams on page 52.

38


Pin Functions

Chapter 2

2.1.2 TermsIn this section, the following terms are used: Pin Denotes the physical pin. Every pin is uniquely denoted by its pin number. A pin can be used in several modes. Depending on the selected mode, a pin name is allocated to the pin. Port group Denotes a group of pins. The pins of a port group have a common set of port mode control registers. Port mode / Port A pin in port mode works as a general purpose input/output pin. It is then called port. The corresponding name is Pnm. For example, P07 denotes port 7 of port group 0. It is referenced as port P07. Alternative mode In alternative mode, a pin can work in various non-general purpose input/ output functions, for example, as the input/output pin of on-chip peripherals. The corresponding pin name depends on the selected function. For example, pin INTP0 denotes the pin for one of the external interrupt inputs. Note that for example P00

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